drivers/clk/sunxi-ng/ccu-sun5i.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2016 Maxime Ripard. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/io.h>
   8 #include <linux/of_address.h>
   9
  10 #include "ccu_common.h"
  11 #include "ccu_reset.h"
  12
  13 #include "ccu_div.h"
  14 #include "ccu_gate.h"
  15 #include "ccu_mp.h"
  16 #include "ccu_mult.h"
  17 #include "ccu_nk.h"
  18 #include "ccu_nkm.h"
  19 #include "ccu_nkmp.h"
  20 #include "ccu_nm.h"
  21 #include "ccu_phase.h"
  22 #include "ccu_sdm.h"
  23
  24 #include "ccu-sun5i.h"
  25
  26 static struct ccu_nkmp pll_core_clk = {
  27         .enable         = BIT(31),
  28         .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
  29         .k              = _SUNXI_CCU_MULT(4, 2),
  30         .m              = _SUNXI_CCU_DIV(0, 2),
  31         .p              = _SUNXI_CCU_DIV(16, 2),
  32         .common         = {
  33                 .reg            = 0x000,
  34                 .hw.init        = CLK_HW_INIT("pll-core",
  35                                               "hosc",
  36                                               &ccu_nkmp_ops,
  37                                               0),
  38         },
  39 };
  40
  41 /*
  42  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
  43  * the base (2x, 4x and 8x), and one variable divider (the one true
  44  * pll audio).
  45  *
  46  * With sigma-delta modulation for fractional-N on the audio PLL,
  47  * we have to use specific dividers. This means the variable divider
  48  * can no longer be used, as the audio codec requests the exact clock
  49  * rates we support through this mechanism. So we now hard code the
  50  * variable divider to 1. This means the clock rates will no longer
  51  * match the clock names.
  52  */
  53 #define SUN5I_PLL_AUDIO_REG     0x008
  54
  55 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
  56         { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
  57         { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
  58 };
  59
  60 static struct ccu_nm pll_audio_base_clk = {
  61         .enable         = BIT(31),
  62         .n              = _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
  63
  64         /*
  65          * The datasheet is wrong here, this doesn't have any
  66          * offset
  67          */
  68         .m              = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
  69         .sdm            = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,
  70                                          0x00c, BIT(31)),
  71         .common         = {
  72                 .reg            = 0x008,
  73                 .features       = CCU_FEATURE_SIGMA_DELTA_MOD,
  74                 .hw.init        = CLK_HW_INIT("pll-audio-base",
  75                                               "hosc",
  76                                               &ccu_nm_ops,
  77                                               0),
  78         },
  79 };
  80
  81 static struct ccu_mult pll_video0_clk = {
  82         .enable         = BIT(31),
  83         .mult           = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
  84         .frac           = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
  85                                           270000000, 297000000),
  86         .common         = {
  87                 .reg            = 0x010,
  88                 .features       = (CCU_FEATURE_FRACTIONAL |
  89                                    CCU_FEATURE_ALL_PREDIV),
  90                 .prediv         = 8,
  91                 .hw.init        = CLK_HW_INIT("pll-video0",
  92                                               "hosc",
  93                                               &ccu_mult_ops,
  94                                               0),
  95         },
  96 };
  97
  98 static struct ccu_nkmp pll_ve_clk = {
  99         .enable         = BIT(31),
 100         .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
 101         .k              = _SUNXI_CCU_MULT(4, 2),
 102         .m              = _SUNXI_CCU_DIV(0, 2),
 103         .p              = _SUNXI_CCU_DIV(16, 2),
 104         .common         = {
 105                 .reg            = 0x018,
 106                 .hw.init        = CLK_HW_INIT("pll-ve",
 107                                               "hosc",
 108                                               &ccu_nkmp_ops,
 109                                               0),
 110         },
 111 };
 112
 113 static struct ccu_nk pll_ddr_base_clk = {
 114         .enable         = BIT(31),
 115         .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
 116         .k              = _SUNXI_CCU_MULT(4, 2),
 117         .common         = {
 118                 .reg            = 0x020,
 119                 .hw.init        = CLK_HW_INIT("pll-ddr-base",
 120                                               "hosc",
 121                                               &ccu_nk_ops,
 122                                               0),
 123         },
 124 };
 125
 126 static SUNXI_CCU_M(pll_ddr_clk, "pll-ddr", "pll-ddr-base", 0x020, 0, 2,
 127                    CLK_IS_CRITICAL);
 128
 129 static struct ccu_div pll_ddr_other_clk = {
 130         .div            = _SUNXI_CCU_DIV_FLAGS(16, 2, CLK_DIVIDER_POWER_OF_TWO),
 131
 132         .common         = {
 133                 .reg            = 0x020,
 134                 .hw.init        = CLK_HW_INIT("pll-ddr-other", "pll-ddr-base",
 135                                               &ccu_div_ops,
 136                                               0),
 137         },
 138 };
 139
 140 static struct ccu_nk pll_periph_clk = {
 141         .enable         = BIT(31),
 142         .n              = _SUNXI_CCU_MULT_OFFSET(8, 5, 0),
 143         .k              = _SUNXI_CCU_MULT(4, 2),
 144         .fixed_post_div = 2,
 145         .common         = {
 146                 .reg            = 0x028,
 147                 .features       = CCU_FEATURE_FIXED_POSTDIV,
 148                 .hw.init        = CLK_HW_INIT("pll-periph",
 149                                               "hosc",
 150                                               &ccu_nk_ops,
 151                                               0),
 152         },
 153 };
 154
 155 static struct ccu_mult pll_video1_clk = {
 156         .enable         = BIT(31),
 157         .mult           = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(0, 7, 0, 9, 127),
 158         .frac           = _SUNXI_CCU_FRAC(BIT(15), BIT(14),
 159                                   270000000, 297000000),
 160         .common         = {
 161                 .reg            = 0x030,
 162                 .features       = (CCU_FEATURE_FRACTIONAL |
 163                                    CCU_FEATURE_ALL_PREDIV),
 164                 .prediv         = 8,
 165                 .hw.init        = CLK_HW_INIT("pll-video1",
 166                                               "hosc",
 167                                               &ccu_mult_ops,
 168                                               0),
 169         },
 170 };
 171
 172 static SUNXI_CCU_GATE(hosc_clk, "hosc", "osc24M", 0x050, BIT(0), 0);
 173
 174 #define SUN5I_AHB_REG   0x054
 175 static const char * const cpu_parents[] = { "osc32k", "hosc",
 176                                             "pll-core" , "pll-periph" };
 177 static const struct ccu_mux_fixed_prediv cpu_predivs[] = {
 178         { .index = 3, .div = 3, },
 179 };
 180 static struct ccu_mux cpu_clk = {
 181         .mux            = {
 182                 .shift          = 16,
 183                 .width          = 2,
 184                 .fixed_predivs  = cpu_predivs,
 185                 .n_predivs      = ARRAY_SIZE(cpu_predivs),
 186         },
 187         .common         = {
 188                 .reg            = 0x054,
 189                 .features       = CCU_FEATURE_FIXED_PREDIV,
 190                 .hw.init        = CLK_HW_INIT_PARENTS("cpu",
 191                                                       cpu_parents,
 192                                                       &ccu_mux_ops,
 193                                                       CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
 194         }
 195 };
 196
 197 static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x054, 0, 2, 0);
 198
 199 static const char * const ahb_parents[] = { "axi" , "cpu", "pll-periph" };
 200 static const struct ccu_mux_fixed_prediv ahb_predivs[] = {
 201         { .index = 2, .div = 2, },
 202 };
 203 static struct ccu_div ahb_clk = {
 204         .div            = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
 205         .mux            = {
 206                 .shift          = 6,
 207                 .width          = 2,
 208                 .fixed_predivs  = ahb_predivs,
 209                 .n_predivs      = ARRAY_SIZE(ahb_predivs),
 210         },
 211
 212         .common         = {
 213                 .reg            = 0x054,
 214                 .hw.init        = CLK_HW_INIT_PARENTS("ahb",
 215                                                       ahb_parents,
 216                                                       &ccu_div_ops,
 217                                                       0),
 218         },
 219 };
 220
 221 static struct clk_div_table apb0_div_table[] = {
 222         { .val = 0, .div = 2 },
 223         { .val = 1, .div = 2 },
 224         { .val = 2, .div = 4 },
 225         { .val = 3, .div = 8 },
 226         { /* Sentinel */ },
 227 };
 228 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
 229                            0x054, 8, 2, apb0_div_table, 0);
 230
 231 static const char * const apb1_parents[] = { "hosc", "pll-periph", "osc32k" };
 232 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", apb1_parents, 0x058,
 233                              0, 5,      /* M */
 234                              16, 2,     /* P */
 235                              24, 2,     /* mux */
 236                              0);
 237
 238 static SUNXI_CCU_GATE(axi_dram_clk,     "axi-dram",     "axi",
 239                       0x05c, BIT(0), 0);
 240
 241 static SUNXI_CCU_GATE(ahb_otg_clk,      "ahb-otg",      "ahb",
 242                       0x060, BIT(0), 0);
 243 static SUNXI_CCU_GATE(ahb_ehci_clk,     "ahb-ehci",     "ahb",
 244                       0x060, BIT(1), 0);
 245 static SUNXI_CCU_GATE(ahb_ohci_clk,     "ahb-ohci",     "ahb",
 246                       0x060, BIT(2), 0);
 247 static SUNXI_CCU_GATE(ahb_ss_clk,       "ahb-ss",       "ahb",
 248                       0x060, BIT(5), 0);
 249 static SUNXI_CCU_GATE(ahb_dma_clk,      "ahb-dma",      "ahb",
 250                       0x060, BIT(6), 0);
 251 static SUNXI_CCU_GATE(ahb_bist_clk,     "ahb-bist",     "ahb",
 252                       0x060, BIT(7), 0);
 253 static SUNXI_CCU_GATE(ahb_mmc0_clk,     "ahb-mmc0",     "ahb",
 254                       0x060, BIT(8), 0);
 255 static SUNXI_CCU_GATE(ahb_mmc1_clk,     "ahb-mmc1",     "ahb",
 256                       0x060, BIT(9), 0);
 257 static SUNXI_CCU_GATE(ahb_mmc2_clk,     "ahb-mmc2",     "ahb",
 258                       0x060, BIT(10), 0);
 259 static SUNXI_CCU_GATE(ahb_nand_clk,     "ahb-nand",     "ahb",
 260                       0x060, BIT(13), 0);
 261 static SUNXI_CCU_GATE(ahb_sdram_clk,    "ahb-sdram",    "ahb",
 262                       0x060, BIT(14), CLK_IS_CRITICAL);
 263 static SUNXI_CCU_GATE(ahb_emac_clk,     "ahb-emac",     "ahb",
 264                       0x060, BIT(17), 0);
 265 static SUNXI_CCU_GATE(ahb_ts_clk,       "ahb-ts",       "ahb",
 266                       0x060, BIT(18), 0);
 267 static SUNXI_CCU_GATE(ahb_spi0_clk,     "ahb-spi0",     "ahb",
 268                       0x060, BIT(20), 0);
 269 static SUNXI_CCU_GATE(ahb_spi1_clk,     "ahb-spi1",     "ahb",
 270                       0x060, BIT(21), 0);
 271 static SUNXI_CCU_GATE(ahb_spi2_clk,     "ahb-spi2",     "ahb",
 272                       0x060, BIT(22), 0);
 273 static SUNXI_CCU_GATE(ahb_gps_clk,      "ahb-gps",      "ahb",
 274                       0x060, BIT(26), 0);
 275 static SUNXI_CCU_GATE(ahb_hstimer_clk,  "ahb-hstimer",  "ahb",
 276                       0x060, BIT(28), 0);
 277
 278 static SUNXI_CCU_GATE(ahb_ve_clk,       "ahb-ve",       "ahb",
 279                       0x064, BIT(0), 0);
 280 static SUNXI_CCU_GATE(ahb_tve_clk,      "ahb-tve",      "ahb",
 281                       0x064, BIT(2), 0);
 282 static SUNXI_CCU_GATE(ahb_lcd_clk,      "ahb-lcd",      "ahb",
 283                       0x064, BIT(4), 0);
 284 static SUNXI_CCU_GATE(ahb_csi_clk,      "ahb-csi",      "ahb",
 285                       0x064, BIT(8), 0);
 286 static SUNXI_CCU_GATE(ahb_hdmi_clk,     "ahb-hdmi",     "ahb",
 287                       0x064, BIT(11), 0);
 288 static SUNXI_CCU_GATE(ahb_de_be_clk,    "ahb-de-be",    "ahb",
 289                       0x064, BIT(12), 0);
 290 static SUNXI_CCU_GATE(ahb_de_fe_clk,    "ahb-de-fe",    "ahb",
 291                       0x064, BIT(14), 0);
 292 static SUNXI_CCU_GATE(ahb_iep_clk,      "ahb-iep",      "ahb",
 293                       0x064, BIT(19), 0);
 294 static SUNXI_CCU_GATE(ahb_gpu_clk,      "ahb-gpu",      "ahb",
 295                       0x064, BIT(20), 0);
 296
 297 static SUNXI_CCU_GATE(apb0_codec_clk,   "apb0-codec",   "apb0",
 298                       0x068, BIT(0), 0);
 299 static SUNXI_CCU_GATE(apb0_spdif_clk,   "apb0-spdif",   "apb0",
 300                       0x068, BIT(1), 0);
 301 static SUNXI_CCU_GATE(apb0_i2s_clk,     "apb0-i2s",     "apb0",
 302                       0x068, BIT(3), 0);
 303 static SUNXI_CCU_GATE(apb0_pio_clk,     "apb0-pio",     "apb0",
 304                       0x068, BIT(5), 0);
 305 static SUNXI_CCU_GATE(apb0_ir_clk,      "apb0-ir",      "apb0",
 306                       0x068, BIT(6), 0);
 307 static SUNXI_CCU_GATE(apb0_keypad_clk,  "apb0-keypad",  "apb0",
 308                       0x068, BIT(10), 0);
 309
 310 static SUNXI_CCU_GATE(apb1_i2c0_clk,    "apb1-i2c0",    "apb1",
 311                       0x06c, BIT(0), 0);
 312 static SUNXI_CCU_GATE(apb1_i2c1_clk,    "apb1-i2c1",    "apb1",
 313                       0x06c, BIT(1), 0);
 314 static SUNXI_CCU_GATE(apb1_i2c2_clk,    "apb1-i2c2",    "apb1",
 315                       0x06c, BIT(2), 0);
 316 static SUNXI_CCU_GATE(apb1_uart0_clk,   "apb1-uart0",   "apb1",
 317                       0x06c, BIT(16), 0);
 318 static SUNXI_CCU_GATE(apb1_uart1_clk,   "apb1-uart1",   "apb1",
 319                       0x06c, BIT(17), 0);
 320 static SUNXI_CCU_GATE(apb1_uart2_clk,   "apb1-uart2",   "apb1",
 321                       0x06c, BIT(18), 0);
 322 static SUNXI_CCU_GATE(apb1_uart3_clk,   "apb1-uart3",   "apb1",
 323                       0x06c, BIT(19), 0);
 324
 325 static const char * const mod0_default_parents[] = { "hosc", "pll-periph",
 326                                                      "pll-ddr-other" };
 327 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
 328                                   0, 4,         /* M */
 329                                   16, 2,        /* P */
 330                                   24, 2,        /* mux */
 331                                   BIT(31),      /* gate */
 332                                   0);
 333
 334 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
 335                                   0, 4,         /* M */
 336                                   16, 2,        /* P */
 337                                   24, 2,        /* mux */
 338                                   BIT(31),      /* gate */
 339                                   0);
 340
 341 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
 342                                   0, 4,         /* M */
 343                                   16, 2,        /* P */
 344                                   24, 2,        /* mux */
 345                                   BIT(31),      /* gate */
 346                                   0);
 347
 348 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
 349                                   0, 4,         /* M */
 350                                   16, 2,        /* P */
 351                                   24, 2,        /* mux */
 352                                   BIT(31),      /* gate */
 353                                   0);
 354
 355 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", mod0_default_parents, 0x098,
 356                                   0, 4,         /* M */
 357                                   16, 2,        /* P */
 358                                   24, 2,        /* mux */
 359                                   BIT(31),      /* gate */
 360                                   0);
 361
 362 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
 363                                   0, 4,         /* M */
 364                                   16, 2,        /* P */
 365                                   24, 2,        /* mux */
 366                                   BIT(31),      /* gate */
 367                                   0);
 368
 369 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
 370                                   0, 4,         /* M */
 371                                   16, 2,        /* P */
 372                                   24, 2,        /* mux */
 373                                   BIT(31),      /* gate */
 374                                   0);
 375
 376 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
 377                                   0, 4,         /* M */
 378                                   16, 2,        /* P */
 379                                   24, 2,        /* mux */
 380                                   BIT(31),      /* gate */
 381                                   0);
 382
 383 static SUNXI_CCU_MP_WITH_MUX_GATE(spi2_clk, "spi2", mod0_default_parents, 0x0a8,
 384                                   0, 4,         /* M */
 385                                   16, 2,        /* P */
 386                                   24, 2,        /* mux */
 387                                   BIT(31),      /* gate */
 388                                   0);
 389
 390 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir", mod0_default_parents, 0x0b0,
 391                                   0, 4,         /* M */
 392                                   16, 2,        /* P */
 393                                   24, 2,        /* mux */
 394                                   BIT(31),      /* gate */
 395                                   0);
 396
 397 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
 398                                             "pll-audio-2x", "pll-audio" };
 399 static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s", i2s_parents,
 400                                0x0b8, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 401
 402 static const char * const spdif_parents[] = { "pll-audio-8x", "pll-audio-4x",
 403                                             "pll-audio-2x", "pll-audio" };
 404 static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", spdif_parents,
 405                                0x0c0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
 406
 407 static const char * const keypad_parents[] = { "hosc", "losc"};
 408 static const u8 keypad_table[] = { 0, 2 };
 409 static struct ccu_mp keypad_clk = {
 410         .enable         = BIT(31),
 411         .m              = _SUNXI_CCU_DIV(8, 5),
 412         .p              = _SUNXI_CCU_DIV(20, 2),
 413         .mux            = _SUNXI_CCU_MUX_TABLE(24, 2, keypad_table),
 414
 415         .common         = {
 416                 .reg            = 0x0c4,
 417                 .hw.init        = CLK_HW_INIT_PARENTS("keypad",
 418                                                       keypad_parents,
 419                                                       &ccu_mp_ops,
 420                                                       0),
 421         },
 422 };
 423
 424 static SUNXI_CCU_GATE(usb_ohci_clk,     "usb-ohci",     "pll-periph",
 425                       0x0cc, BIT(6), 0);
 426 static SUNXI_CCU_GATE(usb_phy0_clk,     "usb-phy0",     "pll-periph",
 427                       0x0cc, BIT(8), 0);
 428 static SUNXI_CCU_GATE(usb_phy1_clk,     "usb-phy1",     "pll-periph",
 429                       0x0cc, BIT(9), 0);
 430
 431 static const char * const gps_parents[] = { "hosc", "pll-periph",
 432                                             "pll-video1", "pll-ve" };
 433 static SUNXI_CCU_M_WITH_MUX_GATE(gps_clk, "gps", gps_parents,
 434                                  0x0d0, 0, 3, 24, 2, BIT(31), 0);
 435
 436 static SUNXI_CCU_GATE(dram_ve_clk,      "dram-ve",      "pll-ddr",
 437                       0x100, BIT(0), 0);
 438 static SUNXI_CCU_GATE(dram_csi_clk,     "dram-csi",     "pll-ddr",
 439                       0x100, BIT(1), 0);
 440 static SUNXI_CCU_GATE(dram_ts_clk,      "dram-ts",      "pll-ddr",
 441                       0x100, BIT(3), 0);
 442 static SUNXI_CCU_GATE(dram_tve_clk,     "dram-tve",     "pll-ddr",
 443                       0x100, BIT(5), 0);
 444 static SUNXI_CCU_GATE(dram_de_fe_clk,   "dram-de-fe",   "pll-ddr",
 445                       0x100, BIT(25), 0);
 446 static SUNXI_CCU_GATE(dram_de_be_clk,   "dram-de-be",   "pll-ddr",
 447                       0x100, BIT(26), 0);
 448 static SUNXI_CCU_GATE(dram_ace_clk,     "dram-ace",     "pll-ddr",
 449                       0x100, BIT(29), 0);
 450 static SUNXI_CCU_GATE(dram_iep_clk,     "dram-iep",     "pll-ddr",
 451                       0x100, BIT(31), 0);
 452
 453 static const char * const de_parents[] = { "pll-video0", "pll-video1",
 454                                            "pll-ddr-other" };
 455 static SUNXI_CCU_M_WITH_MUX_GATE(de_be_clk, "de-be", de_parents,
 456                                  0x104, 0, 4, 24, 2, BIT(31), 0);
 457
 458 static SUNXI_CCU_M_WITH_MUX_GATE(de_fe_clk, "de-fe", de_parents,
 459                                  0x10c, 0, 4, 24, 2, BIT(31), 0);
 460
 461 static const char * const tcon_parents[] = { "pll-video0", "pll-video1",
 462                                              "pll-video0-2x", "pll-video1-2x" };
 463 static SUNXI_CCU_MUX_WITH_GATE(tcon_ch0_clk, "tcon-ch0-sclk", tcon_parents,
 464                                0x118, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
 465
 466 static SUNXI_CCU_M_WITH_MUX_GATE(tcon_ch1_sclk2_clk, "tcon-ch1-sclk2",
 467                                  tcon_parents,
 468                                  0x12c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
 469
 470 static SUNXI_CCU_M_WITH_GATE(tcon_ch1_sclk1_clk, "tcon-ch1-sclk1", "tcon-ch1-sclk2",
 471                              0x12c, 11, 1, BIT(15), CLK_SET_RATE_PARENT);
 472
 473 static const char * const csi_parents[] = { "hosc", "pll-video0", "pll-video1",
 474                                             "pll-video0-2x", "pll-video1-2x" };
 475 static const u8 csi_table[] = { 0, 1, 2, 5, 6 };
 476 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_clk, "csi",
 477                                        csi_parents, csi_table,
 478                                        0x134, 0, 5, 24, 3, BIT(31), 0);
 479
 480 static SUNXI_CCU_GATE(ve_clk,           "ve",           "pll-ve",
 481                       0x13c, BIT(31), CLK_SET_RATE_PARENT);
 482
 483 static SUNXI_CCU_GATE(codec_clk,        "codec",        "pll-audio",
 484                       0x140, BIT(31), CLK_SET_RATE_PARENT);
 485
 486 static SUNXI_CCU_GATE(avs_clk,          "avs",          "hosc",
 487                       0x144, BIT(31), 0);
 488
 489 static const char * const hdmi_parents[] = { "pll-video0", "pll-video0-2x" };
 490 static const u8 hdmi_table[] = { 0, 2 };
 491 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(hdmi_clk, "hdmi",
 492                                        hdmi_parents, hdmi_table,
 493                                        0x150, 0, 4, 24, 2, BIT(31),
 494                                        CLK_SET_RATE_PARENT);
 495
 496 static const char * const gpu_parents[] = { "pll-video0", "pll-ve",
 497                                             "pll-ddr-other", "pll-video1",
 498                                             "pll-video1-2x" };
 499 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents,
 500                                  0x154, 0, 4, 24, 3, BIT(31), 0);
 501
 502 static const char * const mbus_parents[] = { "hosc", "pll-periph", "pll-ddr" };
 503 static SUNXI_CCU_MP_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
 504                                   0x15c, 0, 4, 16, 2, 24, 2, BIT(31), CLK_IS_CRITICAL);
 505
 506 static SUNXI_CCU_GATE(iep_clk,          "iep",          "de-be",
 507                       0x160, BIT(31), 0);
 508
 509 static struct ccu_common *sun5i_a10s_ccu_clks[] = {
 510         &hosc_clk.common,
 511         &pll_core_clk.common,
 512         &pll_audio_base_clk.common,
 513         &pll_video0_clk.common,
 514         &pll_ve_clk.common,
 515         &pll_ddr_base_clk.common,
 516         &pll_ddr_clk.common,
 517         &pll_ddr_other_clk.common,
 518         &pll_periph_clk.common,
 519         &pll_video1_clk.common,
 520         &cpu_clk.common,
 521         &axi_clk.common,
 522         &ahb_clk.common,
 523         &apb0_clk.common,
 524         &apb1_clk.common,
 525         &axi_dram_clk.common,
 526         &ahb_otg_clk.common,
 527         &ahb_ehci_clk.common,
 528         &ahb_ohci_clk.common,
 529         &ahb_ss_clk.common,
 530         &ahb_dma_clk.common,
 531         &ahb_bist_clk.common,
 532         &ahb_mmc0_clk.common,
 533         &ahb_mmc1_clk.common,
 534         &ahb_mmc2_clk.common,
 535         &ahb_nand_clk.common,
 536         &ahb_sdram_clk.common,
 537         &ahb_emac_clk.common,
 538         &ahb_ts_clk.common,
 539         &ahb_spi0_clk.common,
 540         &ahb_spi1_clk.common,
 541         &ahb_spi2_clk.common,
 542         &ahb_gps_clk.common,
 543         &ahb_hstimer_clk.common,
 544         &ahb_ve_clk.common,
 545         &ahb_tve_clk.common,
 546         &ahb_lcd_clk.common,
 547         &ahb_csi_clk.common,
 548         &ahb_hdmi_clk.common,
 549         &ahb_de_be_clk.common,
 550         &ahb_de_fe_clk.common,
 551         &ahb_iep_clk.common,
 552         &ahb_gpu_clk.common,
 553         &apb0_codec_clk.common,
 554         &apb0_spdif_clk.common,
 555         &apb0_i2s_clk.common,
 556         &apb0_pio_clk.common,
 557         &apb0_ir_clk.common,
 558         &apb0_keypad_clk.common,
 559         &apb1_i2c0_clk.common,
 560         &apb1_i2c1_clk.common,
 561         &apb1_i2c2_clk.common,
 562         &apb1_uart0_clk.common,
 563         &apb1_uart1_clk.common,
 564         &apb1_uart2_clk.common,
 565         &apb1_uart3_clk.common,
 566         &nand_clk.common,
 567         &mmc0_clk.common,
 568         &mmc1_clk.common,
 569         &mmc2_clk.common,
 570         &ts_clk.common,
 571         &ss_clk.common,
 572         &spi0_clk.common,
 573         &spi1_clk.common,
 574         &spi2_clk.common,
 575         &ir_clk.common,
 576         &i2s_clk.common,
 577         &spdif_clk.common,
 578         &keypad_clk.common,
 579         &usb_ohci_clk.common,
 580         &usb_phy0_clk.common,
 581         &usb_phy1_clk.common,
 582         &gps_clk.common,
 583         &dram_ve_clk.common,
 584         &dram_csi_clk.common,
 585         &dram_ts_clk.common,
 586         &dram_tve_clk.common,
 587         &dram_de_fe_clk.common,
 588         &dram_de_be_clk.common,
 589         &dram_ace_clk.common,
 590         &dram_iep_clk.common,
 591         &de_be_clk.common,
 592         &de_fe_clk.common,
 593         &tcon_ch0_clk.common,
 594         &tcon_ch1_sclk2_clk.common,
 595         &tcon_ch1_sclk1_clk.common,
 596         &csi_clk.common,
 597         &ve_clk.common,
 598         &codec_clk.common,
 599         &avs_clk.common,
 600         &hdmi_clk.common,
 601         &gpu_clk.common,
 602         &mbus_clk.common,
 603         &iep_clk.common,
 604 };
 605
 606 static const struct clk_hw *clk_parent_pll_audio[] = {
 607         &pll_audio_base_clk.common.hw
 608 };
 609
 610 /* We hardcode the divider to 1 for now */
 611 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
 612                             clk_parent_pll_audio,
 613                             1, 1, CLK_SET_RATE_PARENT);
 614 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
 615                             clk_parent_pll_audio,
 616                             2, 1, CLK_SET_RATE_PARENT);
 617 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
 618                             clk_parent_pll_audio,
 619                             1, 1, CLK_SET_RATE_PARENT);
 620 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
 621                             clk_parent_pll_audio,
 622                             1, 2, CLK_SET_RATE_PARENT);
 623 static CLK_FIXED_FACTOR_HW(pll_video0_2x_clk, "pll-video0-2x",
 624                            &pll_video0_clk.common.hw,
 625                            1, 2, CLK_SET_RATE_PARENT);
 626 static CLK_FIXED_FACTOR_HW(pll_video1_2x_clk, "pll-video1-2x",
 627                            &pll_video1_clk.common.hw,
 628                            1, 2, CLK_SET_RATE_PARENT);
 629
 630 static struct clk_hw_onecell_data sun5i_a10s_hw_clks = {
 631         .hws    = {
 632                 [CLK_HOSC]              = &hosc_clk.common.hw,
 633                 [CLK_PLL_CORE]          = &pll_core_clk.common.hw,
 634                 [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
 635                 [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
 636                 [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
 637                 [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
 638                 [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
 639                 [CLK_PLL_VIDEO0]        = &pll_video0_clk.common.hw,
 640                 [CLK_PLL_VIDEO0_2X]     = &pll_video0_2x_clk.hw,
 641                 [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
 642                 [CLK_PLL_DDR_BASE]      = &pll_ddr_base_clk.common.hw,
 643                 [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
 644                 [CLK_PLL_DDR_OTHER]     = &pll_ddr_other_clk.common.hw,
 645                 [CLK_PLL_PERIPH]        = &pll_periph_clk.common.hw,
 646                 [CLK_PLL_VIDEO1]        = &pll_video1_clk.common.hw,
 647                 [CLK_PLL_VIDEO1_2X]     = &pll_video1_2x_clk.hw,
 648                 [CLK_CPU]               = &cpu_clk.common.hw,
 649                 [CLK_AXI]               = &axi_clk.common.hw,
 650                 [CLK_AHB]               = &ahb_clk.common.hw,
 651                 [CLK_APB0]              = &apb0_clk.common.hw,
 652                 [CLK_APB1]              = &apb1_clk.common.hw,
 653                 [CLK_DRAM_AXI]          = &axi_dram_clk.common.hw,
 654                 [CLK_AHB_OTG]           = &ahb_otg_clk.common.hw,
 655                 [CLK_AHB_EHCI]          = &ahb_ehci_clk.common.hw,
 656                 [CLK_AHB_OHCI]          = &ahb_ohci_clk.common.hw,
 657                 [CLK_AHB_SS]            = &ahb_ss_clk.common.hw,
 658                 [CLK_AHB_DMA]           = &ahb_dma_clk.common.hw,
 659                 [CLK_AHB_BIST]          = &ahb_bist_clk.common.hw,
 660                 [CLK_AHB_MMC0]          = &ahb_mmc0_clk.common.hw,
 661                 [CLK_AHB_MMC1]          = &ahb_mmc1_clk.common.hw,
 662                 [CLK_AHB_MMC2]          = &ahb_mmc2_clk.common.hw,
 663                 [CLK_AHB_NAND]          = &ahb_nand_clk.common.hw,
 664                 [CLK_AHB_SDRAM]         = &ahb_sdram_clk.common.hw,
 665                 [CLK_AHB_EMAC]          = &ahb_emac_clk.common.hw,
 666                 [CLK_AHB_TS]            = &ahb_ts_clk.common.hw,
 667                 [CLK_AHB_SPI0]          = &ahb_spi0_clk.common.hw,
 668                 [CLK_AHB_SPI1]          = &ahb_spi1_clk.common.hw,
 669                 [CLK_AHB_SPI2]          = &ahb_spi2_clk.common.hw,
 670                 [CLK_AHB_GPS]           = &ahb_gps_clk.common.hw,
 671                 [CLK_AHB_HSTIMER]       = &ahb_hstimer_clk.common.hw,
 672                 [CLK_AHB_VE]            = &ahb_ve_clk.common.hw,
 673                 [CLK_AHB_TVE]           = &ahb_tve_clk.common.hw,
 674                 [CLK_AHB_LCD]           = &ahb_lcd_clk.common.hw,
 675                 [CLK_AHB_CSI]           = &ahb_csi_clk.common.hw,
 676                 [CLK_AHB_HDMI]          = &ahb_hdmi_clk.common.hw,
 677                 [CLK_AHB_DE_BE]         = &ahb_de_be_clk.common.hw,
 678                 [CLK_AHB_DE_FE]         = &ahb_de_fe_clk.common.hw,
 679                 [CLK_AHB_IEP]           = &ahb_iep_clk.common.hw,
 680                 [CLK_AHB_GPU]           = &ahb_gpu_clk.common.hw,
 681                 [CLK_APB0_CODEC]        = &apb0_codec_clk.common.hw,
 682                 [CLK_APB0_I2S]          = &apb0_i2s_clk.common.hw,
 683                 [CLK_APB0_PIO]          = &apb0_pio_clk.common.hw,
 684                 [CLK_APB0_IR]           = &apb0_ir_clk.common.hw,
 685                 [CLK_APB0_KEYPAD]       = &apb0_keypad_clk.common.hw,
 686                 [CLK_APB1_I2C0]         = &apb1_i2c0_clk.common.hw,
 687                 [CLK_APB1_I2C1]         = &apb1_i2c1_clk.common.hw,
 688                 [CLK_APB1_I2C2]         = &apb1_i2c2_clk.common.hw,
 689                 [CLK_APB1_UART0]        = &apb1_uart0_clk.common.hw,
 690                 [CLK_APB1_UART1]        = &apb1_uart1_clk.common.hw,
 691                 [CLK_APB1_UART2]        = &apb1_uart2_clk.common.hw,
 692                 [CLK_APB1_UART3]        = &apb1_uart3_clk.common.hw,
 693                 [CLK_NAND]              = &nand_clk.common.hw,
 694                 [CLK_MMC0]              = &mmc0_clk.common.hw,
 695                 [CLK_MMC1]              = &mmc1_clk.common.hw,
 696                 [CLK_MMC2]              = &mmc2_clk.common.hw,
 697                 [CLK_TS]                = &ts_clk.common.hw,
 698                 [CLK_SS]                = &ss_clk.common.hw,
 699                 [CLK_SPI0]              = &spi0_clk.common.hw,
 700                 [CLK_SPI1]              = &spi1_clk.common.hw,
 701                 [CLK_SPI2]              = &spi2_clk.common.hw,
 702                 [CLK_IR]                = &ir_clk.common.hw,
 703                 [CLK_I2S]               = &i2s_clk.common.hw,
 704                 [CLK_KEYPAD]            = &keypad_clk.common.hw,
 705                 [CLK_USB_OHCI]          = &usb_ohci_clk.common.hw,
 706                 [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
 707                 [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
 708                 [CLK_GPS]               = &gps_clk.common.hw,
 709                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
 710                 [CLK_DRAM_CSI]          = &dram_csi_clk.common.hw,
 711                 [CLK_DRAM_TS]           = &dram_ts_clk.common.hw,
 712                 [CLK_DRAM_TVE]          = &dram_tve_clk.common.hw,
 713                 [CLK_DRAM_DE_FE]        = &dram_de_fe_clk.common.hw,
 714                 [CLK_DRAM_DE_BE]        = &dram_de_be_clk.common.hw,
 715                 [CLK_DRAM_ACE]          = &dram_ace_clk.common.hw,
 716                 [CLK_DRAM_IEP]          = &dram_iep_clk.common.hw,
 717                 [CLK_DE_BE]             = &de_be_clk.common.hw,
 718                 [CLK_DE_FE]             = &de_fe_clk.common.hw,
 719                 [CLK_TCON_CH0]          = &tcon_ch0_clk.common.hw,
 720                 [CLK_TCON_CH1_SCLK]     = &tcon_ch1_sclk2_clk.common.hw,
 721                 [CLK_TCON_CH1]          = &tcon_ch1_sclk1_clk.common.hw,
 722                 [CLK_CSI]               = &csi_clk.common.hw,
 723                 [CLK_VE]                = &ve_clk.common.hw,
 724                 [CLK_CODEC]             = &codec_clk.common.hw,
 725                 [CLK_AVS]               = &avs_clk.common.hw,
 726                 [CLK_HDMI]              = &hdmi_clk.common.hw,
 727                 [CLK_GPU]               = &gpu_clk.common.hw,
 728                 [CLK_MBUS]              = &mbus_clk.common.hw,
 729                 [CLK_IEP]               = &iep_clk.common.hw,
 730         },
 731         .num    = CLK_NUMBER,
 732 };
 733
 734 static struct ccu_reset_map sun5i_a10s_ccu_resets[] = {
 735         [RST_USB_PHY0]          =  { 0x0cc, BIT(0) },
 736         [RST_USB_PHY1]          =  { 0x0cc, BIT(1) },
 737
 738         [RST_GPS]               =  { 0x0d0, BIT(30) },
 739
 740         [RST_DE_BE]             =  { 0x104, BIT(30) },
 741
 742         [RST_DE_FE]             =  { 0x10c, BIT(30) },
 743
 744         [RST_TVE]               =  { 0x118, BIT(29) },
 745         [RST_LCD]               =  { 0x118, BIT(30) },
 746
 747         [RST_CSI]               =  { 0x134, BIT(30) },
 748
 749         [RST_VE]                =  { 0x13c, BIT(0) },
 750
 751         [RST_GPU]               =  { 0x154, BIT(30) },
 752
 753         [RST_IEP]               =  { 0x160, BIT(30) },
 754 };
 755
 756 static const struct sunxi_ccu_desc sun5i_a10s_ccu_desc = {
 757         .ccu_clks       = sun5i_a10s_ccu_clks,
 758         .num_ccu_clks   = ARRAY_SIZE(sun5i_a10s_ccu_clks),
 759
 760         .hw_clks        = &sun5i_a10s_hw_clks,
 761
 762         .resets         = sun5i_a10s_ccu_resets,
 763         .num_resets     = ARRAY_SIZE(sun5i_a10s_ccu_resets),
 764 };
 765
 766 /*
 767  * The A13 is the A10s minus the TS, GPS, HDMI, I2S and the keypad
 768  */
 769 static struct clk_hw_onecell_data sun5i_a13_hw_clks = {
 770         .hws    = {
 771                 [CLK_HOSC]              = &hosc_clk.common.hw,
 772                 [CLK_PLL_CORE]          = &pll_core_clk.common.hw,
 773                 [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
 774                 [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
 775                 [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
 776                 [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
 777                 [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
 778                 [CLK_PLL_VIDEO0]        = &pll_video0_clk.common.hw,
 779                 [CLK_PLL_VIDEO0_2X]     = &pll_video0_2x_clk.hw,
 780                 [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
 781                 [CLK_PLL_DDR_BASE]      = &pll_ddr_base_clk.common.hw,
 782                 [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
 783                 [CLK_PLL_DDR_OTHER]     = &pll_ddr_other_clk.common.hw,
 784                 [CLK_PLL_PERIPH]        = &pll_periph_clk.common.hw,
 785                 [CLK_PLL_VIDEO1]        = &pll_video1_clk.common.hw,
 786                 [CLK_PLL_VIDEO1_2X]     = &pll_video1_2x_clk.hw,
 787                 [CLK_CPU]               = &cpu_clk.common.hw,
 788                 [CLK_AXI]               = &axi_clk.common.hw,
 789                 [CLK_AHB]               = &ahb_clk.common.hw,
 790                 [CLK_APB0]              = &apb0_clk.common.hw,
 791                 [CLK_APB1]              = &apb1_clk.common.hw,
 792                 [CLK_DRAM_AXI]          = &axi_dram_clk.common.hw,
 793                 [CLK_AHB_OTG]           = &ahb_otg_clk.common.hw,
 794                 [CLK_AHB_EHCI]          = &ahb_ehci_clk.common.hw,
 795                 [CLK_AHB_OHCI]          = &ahb_ohci_clk.common.hw,
 796                 [CLK_AHB_SS]            = &ahb_ss_clk.common.hw,
 797                 [CLK_AHB_DMA]           = &ahb_dma_clk.common.hw,
 798                 [CLK_AHB_BIST]          = &ahb_bist_clk.common.hw,
 799                 [CLK_AHB_MMC0]          = &ahb_mmc0_clk.common.hw,
 800                 [CLK_AHB_MMC1]          = &ahb_mmc1_clk.common.hw,
 801                 [CLK_AHB_MMC2]          = &ahb_mmc2_clk.common.hw,
 802                 [CLK_AHB_NAND]          = &ahb_nand_clk.common.hw,
 803                 [CLK_AHB_SDRAM]         = &ahb_sdram_clk.common.hw,
 804                 [CLK_AHB_EMAC]          = &ahb_emac_clk.common.hw,
 805                 [CLK_AHB_SPI0]          = &ahb_spi0_clk.common.hw,
 806                 [CLK_AHB_SPI1]          = &ahb_spi1_clk.common.hw,
 807                 [CLK_AHB_SPI2]          = &ahb_spi2_clk.common.hw,
 808                 [CLK_AHB_HSTIMER]       = &ahb_hstimer_clk.common.hw,
 809                 [CLK_AHB_VE]            = &ahb_ve_clk.common.hw,
 810                 [CLK_AHB_TVE]           = &ahb_tve_clk.common.hw,
 811                 [CLK_AHB_LCD]           = &ahb_lcd_clk.common.hw,
 812                 [CLK_AHB_CSI]           = &ahb_csi_clk.common.hw,
 813                 [CLK_AHB_DE_BE]         = &ahb_de_be_clk.common.hw,
 814                 [CLK_AHB_DE_FE]         = &ahb_de_fe_clk.common.hw,
 815                 [CLK_AHB_IEP]           = &ahb_iep_clk.common.hw,
 816                 [CLK_AHB_GPU]           = &ahb_gpu_clk.common.hw,
 817                 [CLK_APB0_CODEC]        = &apb0_codec_clk.common.hw,
 818                 [CLK_APB0_PIO]          = &apb0_pio_clk.common.hw,
 819                 [CLK_APB0_IR]           = &apb0_ir_clk.common.hw,
 820                 [CLK_APB1_I2C0]         = &apb1_i2c0_clk.common.hw,
 821                 [CLK_APB1_I2C1]         = &apb1_i2c1_clk.common.hw,
 822                 [CLK_APB1_I2C2]         = &apb1_i2c2_clk.common.hw,
 823                 [CLK_APB1_UART0]        = &apb1_uart0_clk.common.hw,
 824                 [CLK_APB1_UART1]        = &apb1_uart1_clk.common.hw,
 825                 [CLK_APB1_UART2]        = &apb1_uart2_clk.common.hw,
 826                 [CLK_APB1_UART3]        = &apb1_uart3_clk.common.hw,
 827                 [CLK_NAND]              = &nand_clk.common.hw,
 828                 [CLK_MMC0]              = &mmc0_clk.common.hw,
 829                 [CLK_MMC1]              = &mmc1_clk.common.hw,
 830                 [CLK_MMC2]              = &mmc2_clk.common.hw,
 831                 [CLK_SS]                = &ss_clk.common.hw,
 832                 [CLK_SPI0]              = &spi0_clk.common.hw,
 833                 [CLK_SPI1]              = &spi1_clk.common.hw,
 834                 [CLK_SPI2]              = &spi2_clk.common.hw,
 835                 [CLK_IR]                = &ir_clk.common.hw,
 836                 [CLK_USB_OHCI]          = &usb_ohci_clk.common.hw,
 837                 [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
 838                 [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
 839                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
 840                 [CLK_DRAM_CSI]          = &dram_csi_clk.common.hw,
 841                 [CLK_DRAM_TVE]          = &dram_tve_clk.common.hw,
 842                 [CLK_DRAM_DE_FE]        = &dram_de_fe_clk.common.hw,
 843                 [CLK_DRAM_DE_BE]        = &dram_de_be_clk.common.hw,
 844                 [CLK_DRAM_ACE]          = &dram_ace_clk.common.hw,
 845                 [CLK_DRAM_IEP]          = &dram_iep_clk.common.hw,
 846                 [CLK_DE_BE]             = &de_be_clk.common.hw,
 847                 [CLK_DE_FE]             = &de_fe_clk.common.hw,
 848                 [CLK_TCON_CH0]          = &tcon_ch0_clk.common.hw,
 849                 [CLK_TCON_CH1_SCLK]     = &tcon_ch1_sclk2_clk.common.hw,
 850                 [CLK_TCON_CH1]          = &tcon_ch1_sclk1_clk.common.hw,
 851                 [CLK_CSI]               = &csi_clk.common.hw,
 852                 [CLK_VE]                = &ve_clk.common.hw,
 853                 [CLK_CODEC]             = &codec_clk.common.hw,
 854                 [CLK_AVS]               = &avs_clk.common.hw,
 855                 [CLK_GPU]               = &gpu_clk.common.hw,
 856                 [CLK_MBUS]              = &mbus_clk.common.hw,
 857                 [CLK_IEP]               = &iep_clk.common.hw,
 858         },
 859         .num    = CLK_NUMBER,
 860 };
 861
 862 static const struct sunxi_ccu_desc sun5i_a13_ccu_desc = {
 863         .ccu_clks       = sun5i_a10s_ccu_clks,
 864         .num_ccu_clks   = ARRAY_SIZE(sun5i_a10s_ccu_clks),
 865
 866         .hw_clks        = &sun5i_a13_hw_clks,
 867
 868         .resets         = sun5i_a10s_ccu_resets,
 869         .num_resets     = ARRAY_SIZE(sun5i_a10s_ccu_resets),
 870 };
 871
 872 /*
 873  * The GR8 is the A10s CCU minus the HDMI and keypad, plus SPDIF
 874  */
 875 static struct clk_hw_onecell_data sun5i_gr8_hw_clks = {
 876         .hws    = {
 877                 [CLK_HOSC]              = &hosc_clk.common.hw,
 878                 [CLK_PLL_CORE]          = &pll_core_clk.common.hw,
 879                 [CLK_PLL_AUDIO_BASE]    = &pll_audio_base_clk.common.hw,
 880                 [CLK_PLL_AUDIO]         = &pll_audio_clk.hw,
 881                 [CLK_PLL_AUDIO_2X]      = &pll_audio_2x_clk.hw,
 882                 [CLK_PLL_AUDIO_4X]      = &pll_audio_4x_clk.hw,
 883                 [CLK_PLL_AUDIO_8X]      = &pll_audio_8x_clk.hw,
 884                 [CLK_PLL_VIDEO0]        = &pll_video0_clk.common.hw,
 885                 [CLK_PLL_VIDEO0_2X]     = &pll_video0_2x_clk.hw,
 886                 [CLK_PLL_VE]            = &pll_ve_clk.common.hw,
 887                 [CLK_PLL_DDR_BASE]      = &pll_ddr_base_clk.common.hw,
 888                 [CLK_PLL_DDR]           = &pll_ddr_clk.common.hw,
 889                 [CLK_PLL_DDR_OTHER]     = &pll_ddr_other_clk.common.hw,
 890                 [CLK_PLL_PERIPH]        = &pll_periph_clk.common.hw,
 891                 [CLK_PLL_VIDEO1]        = &pll_video1_clk.common.hw,
 892                 [CLK_PLL_VIDEO1_2X]     = &pll_video1_2x_clk.hw,
 893                 [CLK_CPU]               = &cpu_clk.common.hw,
 894                 [CLK_AXI]               = &axi_clk.common.hw,
 895                 [CLK_AHB]               = &ahb_clk.common.hw,
 896                 [CLK_APB0]              = &apb0_clk.common.hw,
 897                 [CLK_APB1]              = &apb1_clk.common.hw,
 898                 [CLK_DRAM_AXI]          = &axi_dram_clk.common.hw,
 899                 [CLK_AHB_OTG]           = &ahb_otg_clk.common.hw,
 900                 [CLK_AHB_EHCI]          = &ahb_ehci_clk.common.hw,
 901                 [CLK_AHB_OHCI]          = &ahb_ohci_clk.common.hw,
 902                 [CLK_AHB_SS]            = &ahb_ss_clk.common.hw,
 903                 [CLK_AHB_DMA]           = &ahb_dma_clk.common.hw,
 904                 [CLK_AHB_BIST]          = &ahb_bist_clk.common.hw,
 905                 [CLK_AHB_MMC0]          = &ahb_mmc0_clk.common.hw,
 906                 [CLK_AHB_MMC1]          = &ahb_mmc1_clk.common.hw,
 907                 [CLK_AHB_MMC2]          = &ahb_mmc2_clk.common.hw,
 908                 [CLK_AHB_NAND]          = &ahb_nand_clk.common.hw,
 909                 [CLK_AHB_SDRAM]         = &ahb_sdram_clk.common.hw,
 910                 [CLK_AHB_EMAC]          = &ahb_emac_clk.common.hw,
 911                 [CLK_AHB_TS]            = &ahb_ts_clk.common.hw,
 912                 [CLK_AHB_SPI0]          = &ahb_spi0_clk.common.hw,
 913                 [CLK_AHB_SPI1]          = &ahb_spi1_clk.common.hw,
 914                 [CLK_AHB_SPI2]          = &ahb_spi2_clk.common.hw,
 915                 [CLK_AHB_GPS]           = &ahb_gps_clk.common.hw,
 916                 [CLK_AHB_HSTIMER]       = &ahb_hstimer_clk.common.hw,
 917                 [CLK_AHB_VE]            = &ahb_ve_clk.common.hw,
 918                 [CLK_AHB_TVE]           = &ahb_tve_clk.common.hw,
 919                 [CLK_AHB_LCD]           = &ahb_lcd_clk.common.hw,
 920                 [CLK_AHB_CSI]           = &ahb_csi_clk.common.hw,
 921                 [CLK_AHB_DE_BE]         = &ahb_de_be_clk.common.hw,
 922                 [CLK_AHB_DE_FE]         = &ahb_de_fe_clk.common.hw,
 923                 [CLK_AHB_IEP]           = &ahb_iep_clk.common.hw,
 924                 [CLK_AHB_GPU]           = &ahb_gpu_clk.common.hw,
 925                 [CLK_APB0_CODEC]        = &apb0_codec_clk.common.hw,
 926                 [CLK_APB0_SPDIF]        = &apb0_spdif_clk.common.hw,
 927                 [CLK_APB0_I2S]          = &apb0_i2s_clk.common.hw,
 928                 [CLK_APB0_PIO]          = &apb0_pio_clk.common.hw,
 929                 [CLK_APB0_IR]           = &apb0_ir_clk.common.hw,
 930                 [CLK_APB1_I2C0]         = &apb1_i2c0_clk.common.hw,
 931                 [CLK_APB1_I2C1]         = &apb1_i2c1_clk.common.hw,
 932                 [CLK_APB1_I2C2]         = &apb1_i2c2_clk.common.hw,
 933                 [CLK_APB1_UART0]        = &apb1_uart0_clk.common.hw,
 934                 [CLK_APB1_UART1]        = &apb1_uart1_clk.common.hw,
 935                 [CLK_APB1_UART2]        = &apb1_uart2_clk.common.hw,
 936                 [CLK_APB1_UART3]        = &apb1_uart3_clk.common.hw,
 937                 [CLK_NAND]              = &nand_clk.common.hw,
 938                 [CLK_MMC0]              = &mmc0_clk.common.hw,
 939                 [CLK_MMC1]              = &mmc1_clk.common.hw,
 940                 [CLK_MMC2]              = &mmc2_clk.common.hw,
 941                 [CLK_TS]                = &ts_clk.common.hw,
 942                 [CLK_SS]                = &ss_clk.common.hw,
 943                 [CLK_SPI0]              = &spi0_clk.common.hw,
 944                 [CLK_SPI1]              = &spi1_clk.common.hw,
 945                 [CLK_SPI2]              = &spi2_clk.common.hw,
 946                 [CLK_IR]                = &ir_clk.common.hw,
 947                 [CLK_I2S]               = &i2s_clk.common.hw,
 948                 [CLK_SPDIF]             = &spdif_clk.common.hw,
 949                 [CLK_USB_OHCI]          = &usb_ohci_clk.common.hw,
 950                 [CLK_USB_PHY0]          = &usb_phy0_clk.common.hw,
 951                 [CLK_USB_PHY1]          = &usb_phy1_clk.common.hw,
 952                 [CLK_GPS]               = &gps_clk.common.hw,
 953                 [CLK_DRAM_VE]           = &dram_ve_clk.common.hw,
 954                 [CLK_DRAM_CSI]          = &dram_csi_clk.common.hw,
 955                 [CLK_DRAM_TS]           = &dram_ts_clk.common.hw,
 956                 [CLK_DRAM_TVE]          = &dram_tve_clk.common.hw,
 957                 [CLK_DRAM_DE_FE]        = &dram_de_fe_clk.common.hw,
 958                 [CLK_DRAM_DE_BE]        = &dram_de_be_clk.common.hw,
 959                 [CLK_DRAM_ACE]          = &dram_ace_clk.common.hw,
 960                 [CLK_DRAM_IEP]          = &dram_iep_clk.common.hw,
 961                 [CLK_DE_BE]             = &de_be_clk.common.hw,
 962                 [CLK_DE_FE]             = &de_fe_clk.common.hw,
 963                 [CLK_TCON_CH0]          = &tcon_ch0_clk.common.hw,
 964                 [CLK_TCON_CH1_SCLK]     = &tcon_ch1_sclk2_clk.common.hw,
 965                 [CLK_TCON_CH1]          = &tcon_ch1_sclk1_clk.common.hw,
 966                 [CLK_CSI]               = &csi_clk.common.hw,
 967                 [CLK_VE]                = &ve_clk.common.hw,
 968                 [CLK_CODEC]             = &codec_clk.common.hw,
 969                 [CLK_AVS]               = &avs_clk.common.hw,
 970                 [CLK_GPU]               = &gpu_clk.common.hw,
 971                 [CLK_MBUS]              = &mbus_clk.common.hw,
 972                 [CLK_IEP]               = &iep_clk.common.hw,
 973         },
 974         .num    = CLK_NUMBER,
 975 };
 976
 977 static const struct sunxi_ccu_desc sun5i_gr8_ccu_desc = {
 978         .ccu_clks       = sun5i_a10s_ccu_clks,
 979         .num_ccu_clks   = ARRAY_SIZE(sun5i_a10s_ccu_clks),
 980
 981         .hw_clks        = &sun5i_gr8_hw_clks,
 982
 983         .resets         = sun5i_a10s_ccu_resets,
 984         .num_resets     = ARRAY_SIZE(sun5i_a10s_ccu_resets),
 985 };
 986
 987 static void __init sun5i_ccu_init(struct device_node *node,
 988                                   const struct sunxi_ccu_desc *desc)
 989 {
 990         void __iomem *reg;
 991         u32 val;
 992
 993         reg = of_io_request_and_map(node, 0, of_node_full_name(node));
 994         if (IS_ERR(reg)) {
 995                 pr_err("%pOF: Could not map the clock registers\n", node);
 996                 return;
 997         }
 998
 999         /* Force the PLL-Audio-1x divider to 1 */
1000         val = readl(reg + SUN5I_PLL_AUDIO_REG);
1001         val &= ~GENMASK(29, 26);
1002         writel(val | (0 << 26), reg + SUN5I_PLL_AUDIO_REG);
1003
1004         /*
1005          * Use the peripheral PLL as the AHB parent, instead of CPU /
1006          * AXI which have rate changes due to cpufreq.
1007          *
1008          * This is especially a big deal for the HS timer whose parent
1009          * clock is AHB.
1010          */
1011         val = readl(reg + SUN5I_AHB_REG);
1012         val &= ~GENMASK(7, 6);
1013         writel(val | (2 << 6), reg + SUN5I_AHB_REG);
1014
1015         sunxi_ccu_probe(node, reg, desc);
1016 }
1017
1018 static void __init sun5i_a10s_ccu_setup(struct device_node *node)
1019 {
1020         sun5i_ccu_init(node, &sun5i_a10s_ccu_desc);
1021 }
1022 CLK_OF_DECLARE(sun5i_a10s_ccu, "allwinner,sun5i-a10s-ccu",
1023                sun5i_a10s_ccu_setup);
1024
1025 static void __init sun5i_a13_ccu_setup(struct device_node *node)
1026 {
1027         sun5i_ccu_init(node, &sun5i_a13_ccu_desc);
1028 }
1029 CLK_OF_DECLARE(sun5i_a13_ccu, "allwinner,sun5i-a13-ccu",
1030                sun5i_a13_ccu_setup);
1031
1032 static void __init sun5i_gr8_ccu_setup(struct device_node *node)
1033 {
1034         sun5i_ccu_init(node, &sun5i_gr8_ccu_desc);
1035 }
1036 CLK_OF_DECLARE(sun5i_gr8_ccu, "nextthing,gr8-ccu",
1037                sun5i_gr8_ccu_setup);