drivers/clk/qcom/mmcc-msm8974.c

   1 /*
   2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
  26 #include <dt-bindings/reset/qcom,mmcc-msm8974.h>
  27
  28 #include "clk-regmap.h"
  29 #include "clk-pll.h"
  30 #include "clk-rcg.h"
  31 #include "clk-branch.h"
  32 #include "reset.h"
  33
  34 #define P_XO            0
  35 #define P_MMPLL0        1
  36 #define P_EDPLINK       1
  37 #define P_MMPLL1        2
  38 #define P_HDMIPLL       2
  39 #define P_GPLL0         3
  40 #define P_EDPVCO        3
  41 #define P_GPLL1         4
  42 #define P_DSI0PLL       4
  43 #define P_MMPLL2        4
  44 #define P_MMPLL3        4
  45 #define P_DSI1PLL       5
  46
  47 static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
  48         [P_XO]          = 0,
  49         [P_MMPLL0]      = 1,
  50         [P_MMPLL1]      = 2,
  51         [P_GPLL0]       = 5,
  52 };
  53
  54 static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
  55         "xo",
  56         "mmpll0_vote",
  57         "mmpll1_vote",
  58         "mmss_gpll0_vote",
  59 };
  60
  61 static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
  62         [P_XO]          = 0,
  63         [P_MMPLL0]      = 1,
  64         [P_HDMIPLL]     = 4,
  65         [P_GPLL0]       = 5,
  66         [P_DSI0PLL]     = 2,
  67         [P_DSI1PLL]     = 3,
  68 };
  69
  70 static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
  71         "xo",
  72         "mmpll0_vote",
  73         "hdmipll",
  74         "mmss_gpll0_vote",
  75         "dsi0pll",
  76         "dsi1pll",
  77 };
  78
  79 static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
  80         [P_XO]          = 0,
  81         [P_MMPLL0]      = 1,
  82         [P_MMPLL1]      = 2,
  83         [P_GPLL0]       = 5,
  84         [P_MMPLL2]      = 3,
  85 };
  86
  87 static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
  88         "xo",
  89         "mmpll0_vote",
  90         "mmpll1_vote",
  91         "mmss_gpll0_vote",
  92         "mmpll2",
  93 };
  94
  95 static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
  96         [P_XO]          = 0,
  97         [P_MMPLL0]      = 1,
  98         [P_MMPLL1]      = 2,
  99         [P_GPLL0]       = 5,
 100         [P_MMPLL3]      = 3,
 101 };
 102
 103 static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
 104         "xo",
 105         "mmpll0_vote",
 106         "mmpll1_vote",
 107         "mmss_gpll0_vote",
 108         "mmpll3",
 109 };
 110
 111 static const u8 mmcc_xo_mmpll0_1_gpll1_0_map[] = {
 112         [P_XO]          = 0,
 113         [P_MMPLL0]      = 1,
 114         [P_MMPLL1]      = 2,
 115         [P_GPLL0]       = 5,
 116         [P_GPLL1]       = 4,
 117 };
 118
 119 static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
 120         "xo",
 121         "mmpll0_vote",
 122         "mmpll1_vote",
 123         "mmss_gpll0_vote",
 124         "gpll1_vote",
 125 };
 126
 127 static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
 128         [P_XO]          = 0,
 129         [P_EDPLINK]     = 4,
 130         [P_HDMIPLL]     = 3,
 131         [P_EDPVCO]      = 5,
 132         [P_DSI0PLL]     = 1,
 133         [P_DSI1PLL]     = 2,
 134 };
 135
 136 static const char *mmcc_xo_dsi_hdmi_edp[] = {
 137         "xo",
 138         "edp_link_clk",
 139         "hdmipll",
 140         "edp_vco_div",
 141         "dsi0pll",
 142         "dsi1pll",
 143 };
 144
 145 static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
 146         [P_XO]          = 0,
 147         [P_EDPLINK]     = 4,
 148         [P_HDMIPLL]     = 3,
 149         [P_GPLL0]       = 5,
 150         [P_DSI0PLL]     = 1,
 151         [P_DSI1PLL]     = 2,
 152 };
 153
 154 static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
 155         "xo",
 156         "edp_link_clk",
 157         "hdmipll",
 158         "gpll0_vote",
 159         "dsi0pll",
 160         "dsi1pll",
 161 };
 162
 163 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 164
 165 static struct clk_pll mmpll0 = {
 166         .l_reg = 0x0004,
 167         .m_reg = 0x0008,
 168         .n_reg = 0x000c,
 169         .config_reg = 0x0014,
 170         .mode_reg = 0x0000,
 171         .status_reg = 0x001c,
 172         .status_bit = 17,
 173         .clkr.hw.init = &(struct clk_init_data){
 174                 .name = "mmpll0",
 175                 .parent_names = (const char *[]){ "xo" },
 176                 .num_parents = 1,
 177                 .ops = &clk_pll_ops,
 178         },
 179 };
 180
 181 static struct clk_regmap mmpll0_vote = {
 182         .enable_reg = 0x0100,
 183         .enable_mask = BIT(0),
 184         .hw.init = &(struct clk_init_data){
 185                 .name = "mmpll0_vote",
 186                 .parent_names = (const char *[]){ "mmpll0" },
 187                 .num_parents = 1,
 188                 .ops = &clk_pll_vote_ops,
 189         },
 190 };
 191
 192 static struct clk_pll mmpll1 = {
 193         .l_reg = 0x0044,
 194         .m_reg = 0x0048,
 195         .n_reg = 0x004c,
 196         .config_reg = 0x0050,
 197         .mode_reg = 0x0040,
 198         .status_reg = 0x005c,
 199         .status_bit = 17,
 200         .clkr.hw.init = &(struct clk_init_data){
 201                 .name = "mmpll1",
 202                 .parent_names = (const char *[]){ "xo" },
 203                 .num_parents = 1,
 204                 .ops = &clk_pll_ops,
 205         },
 206 };
 207
 208 static struct clk_regmap mmpll1_vote = {
 209         .enable_reg = 0x0100,
 210         .enable_mask = BIT(1),
 211         .hw.init = &(struct clk_init_data){
 212                 .name = "mmpll1_vote",
 213                 .parent_names = (const char *[]){ "mmpll1" },
 214                 .num_parents = 1,
 215                 .ops = &clk_pll_vote_ops,
 216         },
 217 };
 218
 219 static struct clk_pll mmpll2 = {
 220         .l_reg = 0x4104,
 221         .m_reg = 0x4108,
 222         .n_reg = 0x410c,
 223         .config_reg = 0x4110,
 224         .mode_reg = 0x4100,
 225         .status_reg = 0x411c,
 226         .clkr.hw.init = &(struct clk_init_data){
 227                 .name = "mmpll2",
 228                 .parent_names = (const char *[]){ "xo" },
 229                 .num_parents = 1,
 230                 .ops = &clk_pll_ops,
 231         },
 232 };
 233
 234 static struct clk_pll mmpll3 = {
 235         .l_reg = 0x0084,
 236         .m_reg = 0x0088,
 237         .n_reg = 0x008c,
 238         .config_reg = 0x0090,
 239         .mode_reg = 0x0080,
 240         .status_reg = 0x009c,
 241         .status_bit = 17,
 242         .clkr.hw.init = &(struct clk_init_data){
 243                 .name = "mmpll3",
 244                 .parent_names = (const char *[]){ "xo" },
 245                 .num_parents = 1,
 246                 .ops = &clk_pll_ops,
 247         },
 248 };
 249
 250 static struct clk_rcg2 mmss_ahb_clk_src = {
 251         .cmd_rcgr = 0x5000,
 252         .hid_width = 5,
 253         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 254         .clkr.hw.init = &(struct clk_init_data){
 255                 .name = "mmss_ahb_clk_src",
 256                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 257                 .num_parents = 4,
 258                 .ops = &clk_rcg2_ops,
 259         },
 260 };
 261
 262 static struct freq_tbl ftbl_mmss_axi_clk[] = {
 263         F( 19200000, P_XO, 1, 0, 0),
 264         F( 37500000, P_GPLL0, 16, 0, 0),
 265         F( 50000000, P_GPLL0, 12, 0, 0),
 266         F( 75000000, P_GPLL0, 8, 0, 0),
 267         F(100000000, P_GPLL0, 6, 0, 0),
 268         F(150000000, P_GPLL0, 4, 0, 0),
 269         F(291750000, P_MMPLL1, 4, 0, 0),
 270         F(400000000, P_MMPLL0, 2, 0, 0),
 271         F(466800000, P_MMPLL1, 2.5, 0, 0),
 272 };
 273
 274 static struct clk_rcg2 mmss_axi_clk_src = {
 275         .cmd_rcgr = 0x5040,
 276         .hid_width = 5,
 277         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 278         .freq_tbl = ftbl_mmss_axi_clk,
 279         .clkr.hw.init = &(struct clk_init_data){
 280                 .name = "mmss_axi_clk_src",
 281                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 282                 .num_parents = 4,
 283                 .ops = &clk_rcg2_ops,
 284         },
 285 };
 286
 287 static struct freq_tbl ftbl_ocmemnoc_clk[] = {
 288         F( 19200000, P_XO, 1, 0, 0),
 289         F( 37500000, P_GPLL0, 16, 0, 0),
 290         F( 50000000, P_GPLL0, 12, 0, 0),
 291         F( 75000000, P_GPLL0, 8, 0, 0),
 292         F(100000000, P_GPLL0, 6, 0, 0),
 293         F(150000000, P_GPLL0, 4, 0, 0),
 294         F(291750000, P_MMPLL1, 4, 0, 0),
 295         F(400000000, P_MMPLL0, 2, 0, 0),
 296 };
 297
 298 static struct clk_rcg2 ocmemnoc_clk_src = {
 299         .cmd_rcgr = 0x5090,
 300         .hid_width = 5,
 301         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 302         .freq_tbl = ftbl_ocmemnoc_clk,
 303         .clkr.hw.init = &(struct clk_init_data){
 304                 .name = "ocmemnoc_clk_src",
 305                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 306                 .num_parents = 4,
 307                 .ops = &clk_rcg2_ops,
 308         },
 309 };
 310
 311 static struct freq_tbl ftbl_camss_csi0_3_clk[] = {
 312         F(100000000, P_GPLL0, 6, 0, 0),
 313         F(200000000, P_MMPLL0, 4, 0, 0),
 314         { }
 315 };
 316
 317 static struct clk_rcg2 csi0_clk_src = {
 318         .cmd_rcgr = 0x3090,
 319         .hid_width = 5,
 320         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 321         .freq_tbl = ftbl_camss_csi0_3_clk,
 322         .clkr.hw.init = &(struct clk_init_data){
 323                 .name = "csi0_clk_src",
 324                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 325                 .num_parents = 4,
 326                 .ops = &clk_rcg2_ops,
 327         },
 328 };
 329
 330 static struct clk_rcg2 csi1_clk_src = {
 331         .cmd_rcgr = 0x3100,
 332         .hid_width = 5,
 333         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 334         .freq_tbl = ftbl_camss_csi0_3_clk,
 335         .clkr.hw.init = &(struct clk_init_data){
 336                 .name = "csi1_clk_src",
 337                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 338                 .num_parents = 4,
 339                 .ops = &clk_rcg2_ops,
 340         },
 341 };
 342
 343 static struct clk_rcg2 csi2_clk_src = {
 344         .cmd_rcgr = 0x3160,
 345         .hid_width = 5,
 346         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 347         .freq_tbl = ftbl_camss_csi0_3_clk,
 348         .clkr.hw.init = &(struct clk_init_data){
 349                 .name = "csi2_clk_src",
 350                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 351                 .num_parents = 4,
 352                 .ops = &clk_rcg2_ops,
 353         },
 354 };
 355
 356 static struct clk_rcg2 csi3_clk_src = {
 357         .cmd_rcgr = 0x31c0,
 358         .hid_width = 5,
 359         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 360         .freq_tbl = ftbl_camss_csi0_3_clk,
 361         .clkr.hw.init = &(struct clk_init_data){
 362                 .name = "csi3_clk_src",
 363                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 364                 .num_parents = 4,
 365                 .ops = &clk_rcg2_ops,
 366         },
 367 };
 368
 369 static struct freq_tbl ftbl_camss_vfe_vfe0_1_clk[] = {
 370         F(37500000, P_GPLL0, 16, 0, 0),
 371         F(50000000, P_GPLL0, 12, 0, 0),
 372         F(60000000, P_GPLL0, 10, 0, 0),
 373         F(80000000, P_GPLL0, 7.5, 0, 0),
 374         F(100000000, P_GPLL0, 6, 0, 0),
 375         F(109090000, P_GPLL0, 5.5, 0, 0),
 376         F(133330000, P_GPLL0, 4.5, 0, 0),
 377         F(200000000, P_GPLL0, 3, 0, 0),
 378         F(228570000, P_MMPLL0, 3.5, 0, 0),
 379         F(266670000, P_MMPLL0, 3, 0, 0),
 380         F(320000000, P_MMPLL0, 2.5, 0, 0),
 381         F(400000000, P_MMPLL0, 2, 0, 0),
 382         F(465000000, P_MMPLL3, 2, 0, 0),
 383         { }
 384 };
 385
 386 static struct clk_rcg2 vfe0_clk_src = {
 387         .cmd_rcgr = 0x3600,
 388         .hid_width = 5,
 389         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 390         .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 391         .clkr.hw.init = &(struct clk_init_data){
 392                 .name = "vfe0_clk_src",
 393                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 394                 .num_parents = 4,
 395                 .ops = &clk_rcg2_ops,
 396         },
 397 };
 398
 399 static struct clk_rcg2 vfe1_clk_src = {
 400         .cmd_rcgr = 0x3620,
 401         .hid_width = 5,
 402         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 403         .freq_tbl = ftbl_camss_vfe_vfe0_1_clk,
 404         .clkr.hw.init = &(struct clk_init_data){
 405                 .name = "vfe1_clk_src",
 406                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 407                 .num_parents = 4,
 408                 .ops = &clk_rcg2_ops,
 409         },
 410 };
 411
 412 static struct freq_tbl ftbl_mdss_mdp_clk[] = {
 413         F(37500000, P_GPLL0, 16, 0, 0),
 414         F(60000000, P_GPLL0, 10, 0, 0),
 415         F(75000000, P_GPLL0, 8, 0, 0),
 416         F(85710000, P_GPLL0, 7, 0, 0),
 417         F(100000000, P_GPLL0, 6, 0, 0),
 418         F(133330000, P_MMPLL0, 6, 0, 0),
 419         F(160000000, P_MMPLL0, 5, 0, 0),
 420         F(200000000, P_MMPLL0, 4, 0, 0),
 421         F(228570000, P_MMPLL0, 3.5, 0, 0),
 422         F(240000000, P_GPLL0, 2.5, 0, 0),
 423         F(266670000, P_MMPLL0, 3, 0, 0),
 424         F(320000000, P_MMPLL0, 2.5, 0, 0),
 425         { }
 426 };
 427
 428 static struct clk_rcg2 mdp_clk_src = {
 429         .cmd_rcgr = 0x2040,
 430         .hid_width = 5,
 431         .parent_map = mmcc_xo_mmpll0_dsi_hdmi_gpll0_map,
 432         .freq_tbl = ftbl_mdss_mdp_clk,
 433         .clkr.hw.init = &(struct clk_init_data){
 434                 .name = "mdp_clk_src",
 435                 .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
 436                 .num_parents = 6,
 437                 .ops = &clk_rcg2_ops,
 438         },
 439 };
 440
 441 static struct clk_rcg2 gfx3d_clk_src = {
 442         .cmd_rcgr = 0x4000,
 443         .hid_width = 5,
 444         .parent_map = mmcc_xo_mmpll0_1_2_gpll0_map,
 445         .clkr.hw.init = &(struct clk_init_data){
 446                 .name = "gfx3d_clk_src",
 447                 .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
 448                 .num_parents = 5,
 449                 .ops = &clk_rcg2_ops,
 450         },
 451 };
 452
 453 static struct freq_tbl ftbl_camss_jpeg_jpeg0_2_clk[] = {
 454         F(75000000, P_GPLL0, 8, 0, 0),
 455         F(133330000, P_GPLL0, 4.5, 0, 0),
 456         F(200000000, P_GPLL0, 3, 0, 0),
 457         F(228570000, P_MMPLL0, 3.5, 0, 0),
 458         F(266670000, P_MMPLL0, 3, 0, 0),
 459         F(320000000, P_MMPLL0, 2.5, 0, 0),
 460         { }
 461 };
 462
 463 static struct clk_rcg2 jpeg0_clk_src = {
 464         .cmd_rcgr = 0x3500,
 465         .hid_width = 5,
 466         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 467         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 468         .clkr.hw.init = &(struct clk_init_data){
 469                 .name = "jpeg0_clk_src",
 470                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 471                 .num_parents = 4,
 472                 .ops = &clk_rcg2_ops,
 473         },
 474 };
 475
 476 static struct clk_rcg2 jpeg1_clk_src = {
 477         .cmd_rcgr = 0x3520,
 478         .hid_width = 5,
 479         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 480         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 481         .clkr.hw.init = &(struct clk_init_data){
 482                 .name = "jpeg1_clk_src",
 483                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 484                 .num_parents = 4,
 485                 .ops = &clk_rcg2_ops,
 486         },
 487 };
 488
 489 static struct clk_rcg2 jpeg2_clk_src = {
 490         .cmd_rcgr = 0x3540,
 491         .hid_width = 5,
 492         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 493         .freq_tbl = ftbl_camss_jpeg_jpeg0_2_clk,
 494         .clkr.hw.init = &(struct clk_init_data){
 495                 .name = "jpeg2_clk_src",
 496                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 497                 .num_parents = 4,
 498                 .ops = &clk_rcg2_ops,
 499         },
 500 };
 501
 502 static struct freq_tbl ftbl_mdss_pclk0_clk[] = {
 503         F(125000000, P_DSI0PLL, 2, 0, 0),
 504         F(250000000, P_DSI0PLL, 1, 0, 0),
 505         { }
 506 };
 507
 508 static struct freq_tbl ftbl_mdss_pclk1_clk[] = {
 509         F(125000000, P_DSI1PLL, 2, 0, 0),
 510         F(250000000, P_DSI1PLL, 1, 0, 0),
 511         { }
 512 };
 513
 514 static struct clk_rcg2 pclk0_clk_src = {
 515         .cmd_rcgr = 0x2000,
 516         .mnd_width = 8,
 517         .hid_width = 5,
 518         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 519         .freq_tbl = ftbl_mdss_pclk0_clk,
 520         .clkr.hw.init = &(struct clk_init_data){
 521                 .name = "pclk0_clk_src",
 522                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 523                 .num_parents = 6,
 524                 .ops = &clk_rcg2_ops,
 525         },
 526 };
 527
 528 static struct clk_rcg2 pclk1_clk_src = {
 529         .cmd_rcgr = 0x2020,
 530         .mnd_width = 8,
 531         .hid_width = 5,
 532         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 533         .freq_tbl = ftbl_mdss_pclk1_clk,
 534         .clkr.hw.init = &(struct clk_init_data){
 535                 .name = "pclk1_clk_src",
 536                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 537                 .num_parents = 6,
 538                 .ops = &clk_rcg2_ops,
 539         },
 540 };
 541
 542 static struct freq_tbl ftbl_venus0_vcodec0_clk[] = {
 543         F(50000000, P_GPLL0, 12, 0, 0),
 544         F(100000000, P_GPLL0, 6, 0, 0),
 545         F(133330000, P_MMPLL0, 6, 0, 0),
 546         F(200000000, P_MMPLL0, 4, 0, 0),
 547         F(266670000, P_MMPLL0, 3, 0, 0),
 548         F(465000000, P_MMPLL3, 2, 0, 0),
 549         { }
 550 };
 551
 552 static struct clk_rcg2 vcodec0_clk_src = {
 553         .cmd_rcgr = 0x1000,
 554         .mnd_width = 8,
 555         .hid_width = 5,
 556         .parent_map = mmcc_xo_mmpll0_1_3_gpll0_map,
 557         .freq_tbl = ftbl_venus0_vcodec0_clk,
 558         .clkr.hw.init = &(struct clk_init_data){
 559                 .name = "vcodec0_clk_src",
 560                 .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
 561                 .num_parents = 5,
 562                 .ops = &clk_rcg2_ops,
 563         },
 564 };
 565
 566 static struct freq_tbl ftbl_camss_cci_cci_clk[] = {
 567         F(19200000, P_XO, 1, 0, 0),
 568         { }
 569 };
 570
 571 static struct clk_rcg2 cci_clk_src = {
 572         .cmd_rcgr = 0x3300,
 573         .hid_width = 5,
 574         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 575         .freq_tbl = ftbl_camss_cci_cci_clk,
 576         .clkr.hw.init = &(struct clk_init_data){
 577                 .name = "cci_clk_src",
 578                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 579                 .num_parents = 4,
 580                 .ops = &clk_rcg2_ops,
 581         },
 582 };
 583
 584 static struct freq_tbl ftbl_camss_gp0_1_clk[] = {
 585         F(10000, P_XO, 16, 1, 120),
 586         F(24000, P_XO, 16, 1, 50),
 587         F(6000000, P_GPLL0, 10, 1, 10),
 588         F(12000000, P_GPLL0, 10, 1, 5),
 589         F(13000000, P_GPLL0, 4, 13, 150),
 590         F(24000000, P_GPLL0, 5, 1, 5),
 591         { }
 592 };
 593
 594 static struct clk_rcg2 camss_gp0_clk_src = {
 595         .cmd_rcgr = 0x3420,
 596         .mnd_width = 8,
 597         .hid_width = 5,
 598         .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
 599         .freq_tbl = ftbl_camss_gp0_1_clk,
 600         .clkr.hw.init = &(struct clk_init_data){
 601                 .name = "camss_gp0_clk_src",
 602                 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
 603                 .num_parents = 5,
 604                 .ops = &clk_rcg2_ops,
 605         },
 606 };
 607
 608 static struct clk_rcg2 camss_gp1_clk_src = {
 609         .cmd_rcgr = 0x3450,
 610         .mnd_width = 8,
 611         .hid_width = 5,
 612         .parent_map = mmcc_xo_mmpll0_1_gpll1_0_map,
 613         .freq_tbl = ftbl_camss_gp0_1_clk,
 614         .clkr.hw.init = &(struct clk_init_data){
 615                 .name = "camss_gp1_clk_src",
 616                 .parent_names = mmcc_xo_mmpll0_1_gpll1_0,
 617                 .num_parents = 5,
 618                 .ops = &clk_rcg2_ops,
 619         },
 620 };
 621
 622 static struct freq_tbl ftbl_camss_mclk0_3_clk[] = {
 623         F(4800000, P_XO, 4, 0, 0),
 624         F(6000000, P_GPLL0, 10, 1, 10),
 625         F(8000000, P_GPLL0, 15, 1, 5),
 626         F(9600000, P_XO, 2, 0, 0),
 627         F(16000000, P_GPLL0, 12.5, 1, 3),
 628         F(19200000, P_XO, 1, 0, 0),
 629         F(24000000, P_GPLL0, 5, 1, 5),
 630         F(32000000, P_MMPLL0, 5, 1, 5),
 631         F(48000000, P_GPLL0, 12.5, 0, 0),
 632         F(64000000, P_MMPLL0, 12.5, 0, 0),
 633         F(66670000, P_GPLL0, 9, 0, 0),
 634         { }
 635 };
 636
 637 static struct clk_rcg2 mclk0_clk_src = {
 638         .cmd_rcgr = 0x3360,
 639         .hid_width = 5,
 640         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 641         .freq_tbl = ftbl_camss_mclk0_3_clk,
 642         .clkr.hw.init = &(struct clk_init_data){
 643                 .name = "mclk0_clk_src",
 644                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 645                 .num_parents = 4,
 646                 .ops = &clk_rcg2_ops,
 647         },
 648 };
 649
 650 static struct clk_rcg2 mclk1_clk_src = {
 651         .cmd_rcgr = 0x3390,
 652         .hid_width = 5,
 653         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 654         .freq_tbl = ftbl_camss_mclk0_3_clk,
 655         .clkr.hw.init = &(struct clk_init_data){
 656                 .name = "mclk1_clk_src",
 657                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 658                 .num_parents = 4,
 659                 .ops = &clk_rcg2_ops,
 660         },
 661 };
 662
 663 static struct clk_rcg2 mclk2_clk_src = {
 664         .cmd_rcgr = 0x33c0,
 665         .hid_width = 5,
 666         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 667         .freq_tbl = ftbl_camss_mclk0_3_clk,
 668         .clkr.hw.init = &(struct clk_init_data){
 669                 .name = "mclk2_clk_src",
 670                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 671                 .num_parents = 4,
 672                 .ops = &clk_rcg2_ops,
 673         },
 674 };
 675
 676 static struct clk_rcg2 mclk3_clk_src = {
 677         .cmd_rcgr = 0x33f0,
 678         .hid_width = 5,
 679         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 680         .freq_tbl = ftbl_camss_mclk0_3_clk,
 681         .clkr.hw.init = &(struct clk_init_data){
 682                 .name = "mclk3_clk_src",
 683                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 684                 .num_parents = 4,
 685                 .ops = &clk_rcg2_ops,
 686         },
 687 };
 688
 689 static struct freq_tbl ftbl_camss_phy0_2_csi0_2phytimer_clk[] = {
 690         F(100000000, P_GPLL0, 6, 0, 0),
 691         F(200000000, P_MMPLL0, 4, 0, 0),
 692         { }
 693 };
 694
 695 static struct clk_rcg2 csi0phytimer_clk_src = {
 696         .cmd_rcgr = 0x3000,
 697         .hid_width = 5,
 698         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 699         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 700         .clkr.hw.init = &(struct clk_init_data){
 701                 .name = "csi0phytimer_clk_src",
 702                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 703                 .num_parents = 4,
 704                 .ops = &clk_rcg2_ops,
 705         },
 706 };
 707
 708 static struct clk_rcg2 csi1phytimer_clk_src = {
 709         .cmd_rcgr = 0x3030,
 710         .hid_width = 5,
 711         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 712         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 713         .clkr.hw.init = &(struct clk_init_data){
 714                 .name = "csi1phytimer_clk_src",
 715                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 716                 .num_parents = 4,
 717                 .ops = &clk_rcg2_ops,
 718         },
 719 };
 720
 721 static struct clk_rcg2 csi2phytimer_clk_src = {
 722         .cmd_rcgr = 0x3060,
 723         .hid_width = 5,
 724         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 725         .freq_tbl = ftbl_camss_phy0_2_csi0_2phytimer_clk,
 726         .clkr.hw.init = &(struct clk_init_data){
 727                 .name = "csi2phytimer_clk_src",
 728                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 729                 .num_parents = 4,
 730                 .ops = &clk_rcg2_ops,
 731         },
 732 };
 733
 734 static struct freq_tbl ftbl_camss_vfe_cpp_clk[] = {
 735         F(133330000, P_GPLL0, 4.5, 0, 0),
 736         F(266670000, P_MMPLL0, 3, 0, 0),
 737         F(320000000, P_MMPLL0, 2.5, 0, 0),
 738         F(400000000, P_MMPLL0, 2, 0, 0),
 739         F(465000000, P_MMPLL3, 2, 0, 0),
 740         { }
 741 };
 742
 743 static struct clk_rcg2 cpp_clk_src = {
 744         .cmd_rcgr = 0x3640,
 745         .hid_width = 5,
 746         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 747         .freq_tbl = ftbl_camss_vfe_cpp_clk,
 748         .clkr.hw.init = &(struct clk_init_data){
 749                 .name = "cpp_clk_src",
 750                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 751                 .num_parents = 4,
 752                 .ops = &clk_rcg2_ops,
 753         },
 754 };
 755
 756 static struct freq_tbl ftbl_mdss_byte0_clk[] = {
 757         F(93750000, P_DSI0PLL, 8, 0, 0),
 758         F(187500000, P_DSI0PLL, 4, 0, 0),
 759         { }
 760 };
 761
 762 static struct freq_tbl ftbl_mdss_byte1_clk[] = {
 763         F(93750000, P_DSI1PLL, 8, 0, 0),
 764         F(187500000, P_DSI1PLL, 4, 0, 0),
 765         { }
 766 };
 767
 768 static struct clk_rcg2 byte0_clk_src = {
 769         .cmd_rcgr = 0x2120,
 770         .hid_width = 5,
 771         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 772         .freq_tbl = ftbl_mdss_byte0_clk,
 773         .clkr.hw.init = &(struct clk_init_data){
 774                 .name = "byte0_clk_src",
 775                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 776                 .num_parents = 6,
 777                 .ops = &clk_rcg2_ops,
 778         },
 779 };
 780
 781 static struct clk_rcg2 byte1_clk_src = {
 782         .cmd_rcgr = 0x2140,
 783         .hid_width = 5,
 784         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 785         .freq_tbl = ftbl_mdss_byte1_clk,
 786         .clkr.hw.init = &(struct clk_init_data){
 787                 .name = "byte1_clk_src",
 788                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 789                 .num_parents = 6,
 790                 .ops = &clk_rcg2_ops,
 791         },
 792 };
 793
 794 static struct freq_tbl ftbl_mdss_edpaux_clk[] = {
 795         F(19200000, P_XO, 1, 0, 0),
 796         { }
 797 };
 798
 799 static struct clk_rcg2 edpaux_clk_src = {
 800         .cmd_rcgr = 0x20e0,
 801         .hid_width = 5,
 802         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 803         .freq_tbl = ftbl_mdss_edpaux_clk,
 804         .clkr.hw.init = &(struct clk_init_data){
 805                 .name = "edpaux_clk_src",
 806                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 807                 .num_parents = 4,
 808                 .ops = &clk_rcg2_ops,
 809         },
 810 };
 811
 812 static struct freq_tbl ftbl_mdss_edplink_clk[] = {
 813         F(135000000, P_EDPLINK, 2, 0, 0),
 814         F(270000000, P_EDPLINK, 11, 0, 0),
 815         { }
 816 };
 817
 818 static struct clk_rcg2 edplink_clk_src = {
 819         .cmd_rcgr = 0x20c0,
 820         .hid_width = 5,
 821         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 822         .freq_tbl = ftbl_mdss_edplink_clk,
 823         .clkr.hw.init = &(struct clk_init_data){
 824                 .name = "edplink_clk_src",
 825                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 826                 .num_parents = 6,
 827                 .ops = &clk_rcg2_ops,
 828         },
 829 };
 830
 831 static struct freq_tbl ftbl_mdss_edppixel_clk[] = {
 832         F(175000000, P_EDPVCO, 2, 0, 0),
 833         F(350000000, P_EDPVCO, 11, 0, 0),
 834         { }
 835 };
 836
 837 static struct clk_rcg2 edppixel_clk_src = {
 838         .cmd_rcgr = 0x20a0,
 839         .mnd_width = 8,
 840         .hid_width = 5,
 841         .parent_map = mmcc_xo_dsi_hdmi_edp_map,
 842         .freq_tbl = ftbl_mdss_edppixel_clk,
 843         .clkr.hw.init = &(struct clk_init_data){
 844                 .name = "edppixel_clk_src",
 845                 .parent_names = mmcc_xo_dsi_hdmi_edp,
 846                 .num_parents = 6,
 847                 .ops = &clk_rcg2_ops,
 848         },
 849 };
 850
 851 static struct freq_tbl ftbl_mdss_esc0_1_clk[] = {
 852         F(19200000, P_XO, 1, 0, 0),
 853         { }
 854 };
 855
 856 static struct clk_rcg2 esc0_clk_src = {
 857         .cmd_rcgr = 0x2160,
 858         .hid_width = 5,
 859         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 860         .freq_tbl = ftbl_mdss_esc0_1_clk,
 861         .clkr.hw.init = &(struct clk_init_data){
 862                 .name = "esc0_clk_src",
 863                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 864                 .num_parents = 6,
 865                 .ops = &clk_rcg2_ops,
 866         },
 867 };
 868
 869 static struct clk_rcg2 esc1_clk_src = {
 870         .cmd_rcgr = 0x2180,
 871         .hid_width = 5,
 872         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 873         .freq_tbl = ftbl_mdss_esc0_1_clk,
 874         .clkr.hw.init = &(struct clk_init_data){
 875                 .name = "esc1_clk_src",
 876                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 877                 .num_parents = 6,
 878                 .ops = &clk_rcg2_ops,
 879         },
 880 };
 881
 882 static struct freq_tbl ftbl_mdss_extpclk_clk[] = {
 883         F(25200000, P_HDMIPLL, 1, 0, 0),
 884         F(27000000, P_HDMIPLL, 1, 0, 0),
 885         F(27030000, P_HDMIPLL, 1, 0, 0),
 886         F(65000000, P_HDMIPLL, 1, 0, 0),
 887         F(74250000, P_HDMIPLL, 1, 0, 0),
 888         F(108000000, P_HDMIPLL, 1, 0, 0),
 889         F(148500000, P_HDMIPLL, 1, 0, 0),
 890         F(268500000, P_HDMIPLL, 1, 0, 0),
 891         F(297000000, P_HDMIPLL, 1, 0, 0),
 892         { }
 893 };
 894
 895 static struct clk_rcg2 extpclk_clk_src = {
 896         .cmd_rcgr = 0x2060,
 897         .hid_width = 5,
 898         .parent_map = mmcc_xo_dsi_hdmi_edp_gpll0_map,
 899         .freq_tbl = ftbl_mdss_extpclk_clk,
 900         .clkr.hw.init = &(struct clk_init_data){
 901                 .name = "extpclk_clk_src",
 902                 .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
 903                 .num_parents = 6,
 904                 .ops = &clk_rcg2_ops,
 905         },
 906 };
 907
 908 static struct freq_tbl ftbl_mdss_hdmi_clk[] = {
 909         F(19200000, P_XO, 1, 0, 0),
 910         { }
 911 };
 912
 913 static struct clk_rcg2 hdmi_clk_src = {
 914         .cmd_rcgr = 0x2100,
 915         .hid_width = 5,
 916         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 917         .freq_tbl = ftbl_mdss_hdmi_clk,
 918         .clkr.hw.init = &(struct clk_init_data){
 919                 .name = "hdmi_clk_src",
 920                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 921                 .num_parents = 4,
 922                 .ops = &clk_rcg2_ops,
 923         },
 924 };
 925
 926 static struct freq_tbl ftbl_mdss_vsync_clk[] = {
 927         F(19200000, P_XO, 1, 0, 0),
 928         { }
 929 };
 930
 931 static struct clk_rcg2 vsync_clk_src = {
 932         .cmd_rcgr = 0x2080,
 933         .hid_width = 5,
 934         .parent_map = mmcc_xo_mmpll0_mmpll1_gpll0_map,
 935         .freq_tbl = ftbl_mdss_vsync_clk,
 936         .clkr.hw.init = &(struct clk_init_data){
 937                 .name = "vsync_clk_src",
 938                 .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
 939                 .num_parents = 4,
 940                 .ops = &clk_rcg2_ops,
 941         },
 942 };
 943
 944 static struct clk_branch camss_cci_cci_ahb_clk = {
 945         .halt_reg = 0x3348,
 946         .clkr = {
 947                 .enable_reg = 0x3348,
 948                 .enable_mask = BIT(0),
 949                 .hw.init = &(struct clk_init_data){
 950                         .name = "camss_cci_cci_ahb_clk",
 951                         .parent_names = (const char *[]){
 952                                 "mmss_ahb_clk_src",
 953                         },
 954                         .num_parents = 1,
 955                         .ops = &clk_branch2_ops,
 956                 },
 957         },
 958 };
 959
 960 static struct clk_branch camss_cci_cci_clk = {
 961         .halt_reg = 0x3344,
 962         .clkr = {
 963                 .enable_reg = 0x3344,
 964                 .enable_mask = BIT(0),
 965                 .hw.init = &(struct clk_init_data){
 966                         .name = "camss_cci_cci_clk",
 967                         .parent_names = (const char *[]){
 968                                 "cci_clk_src",
 969                         },
 970                         .num_parents = 1,
 971                         .flags = CLK_SET_RATE_PARENT,
 972                         .ops = &clk_branch2_ops,
 973                 },
 974         },
 975 };
 976
 977 static struct clk_branch camss_csi0_ahb_clk = {
 978         .halt_reg = 0x30bc,
 979         .clkr = {
 980                 .enable_reg = 0x30bc,
 981                 .enable_mask = BIT(0),
 982                 .hw.init = &(struct clk_init_data){
 983                         .name = "camss_csi0_ahb_clk",
 984                         .parent_names = (const char *[]){
 985                                 "mmss_ahb_clk_src",
 986                         },
 987                         .num_parents = 1,
 988                         .ops = &clk_branch2_ops,
 989                 },
 990         },
 991 };
 992
 993 static struct clk_branch camss_csi0_clk = {
 994         .halt_reg = 0x30b4,
 995         .clkr = {
 996                 .enable_reg = 0x30b4,
 997                 .enable_mask = BIT(0),
 998                 .hw.init = &(struct clk_init_data){
 999                         .name = "camss_csi0_clk",
1000                         .parent_names = (const char *[]){
1001                                 "csi0_clk_src",
1002                         },
1003                         .num_parents = 1,
1004                         .flags = CLK_SET_RATE_PARENT,
1005                         .ops = &clk_branch2_ops,
1006                 },
1007         },
1008 };
1009
1010 static struct clk_branch camss_csi0phy_clk = {
1011         .halt_reg = 0x30c4,
1012         .clkr = {
1013                 .enable_reg = 0x30c4,
1014                 .enable_mask = BIT(0),
1015                 .hw.init = &(struct clk_init_data){
1016                         .name = "camss_csi0phy_clk",
1017                         .parent_names = (const char *[]){
1018                                 "csi0_clk_src",
1019                         },
1020                         .num_parents = 1,
1021                         .flags = CLK_SET_RATE_PARENT,
1022                         .ops = &clk_branch2_ops,
1023                 },
1024         },
1025 };
1026
1027 static struct clk_branch camss_csi0pix_clk = {
1028         .halt_reg = 0x30e4,
1029         .clkr = {
1030                 .enable_reg = 0x30e4,
1031                 .enable_mask = BIT(0),
1032                 .hw.init = &(struct clk_init_data){
1033                         .name = "camss_csi0pix_clk",
1034                         .parent_names = (const char *[]){
1035                                 "csi0_clk_src",
1036                         },
1037                         .num_parents = 1,
1038                         .flags = CLK_SET_RATE_PARENT,
1039                         .ops = &clk_branch2_ops,
1040                 },
1041         },
1042 };
1043
1044 static struct clk_branch camss_csi0rdi_clk = {
1045         .halt_reg = 0x30d4,
1046         .clkr = {
1047                 .enable_reg = 0x30d4,
1048                 .enable_mask = BIT(0),
1049                 .hw.init = &(struct clk_init_data){
1050                         .name = "camss_csi0rdi_clk",
1051                         .parent_names = (const char *[]){
1052                                 "csi0_clk_src",
1053                         },
1054                         .num_parents = 1,
1055                         .flags = CLK_SET_RATE_PARENT,
1056                         .ops = &clk_branch2_ops,
1057                 },
1058         },
1059 };
1060
1061 static struct clk_branch camss_csi1_ahb_clk = {
1062         .halt_reg = 0x3128,
1063         .clkr = {
1064                 .enable_reg = 0x3128,
1065                 .enable_mask = BIT(0),
1066                 .hw.init = &(struct clk_init_data){
1067                         .name = "camss_csi1_ahb_clk",
1068                         .parent_names = (const char *[]){
1069                                 "mmss_ahb_clk_src",
1070                         },
1071                         .num_parents = 1,
1072                         .ops = &clk_branch2_ops,
1073                 },
1074         },
1075 };
1076
1077 static struct clk_branch camss_csi1_clk = {
1078         .halt_reg = 0x3124,
1079         .clkr = {
1080                 .enable_reg = 0x3124,
1081                 .enable_mask = BIT(0),
1082                 .hw.init = &(struct clk_init_data){
1083                         .name = "camss_csi1_clk",
1084                         .parent_names = (const char *[]){
1085                                 "csi1_clk_src",
1086                         },
1087                         .num_parents = 1,
1088                         .flags = CLK_SET_RATE_PARENT,
1089                         .ops = &clk_branch2_ops,
1090                 },
1091         },
1092 };
1093
1094 static struct clk_branch camss_csi1phy_clk = {
1095         .halt_reg = 0x3134,
1096         .clkr = {
1097                 .enable_reg = 0x3134,
1098                 .enable_mask = BIT(0),
1099                 .hw.init = &(struct clk_init_data){
1100                         .name = "camss_csi1phy_clk",
1101                         .parent_names = (const char *[]){
1102                                 "csi1_clk_src",
1103                         },
1104                         .num_parents = 1,
1105                         .flags = CLK_SET_RATE_PARENT,
1106                         .ops = &clk_branch2_ops,
1107                 },
1108         },
1109 };
1110
1111 static struct clk_branch camss_csi1pix_clk = {
1112         .halt_reg = 0x3154,
1113         .clkr = {
1114                 .enable_reg = 0x3154,
1115                 .enable_mask = BIT(0),
1116                 .hw.init = &(struct clk_init_data){
1117                         .name = "camss_csi1pix_clk",
1118                         .parent_names = (const char *[]){
1119                                 "csi1_clk_src",
1120                         },
1121                         .num_parents = 1,
1122                         .flags = CLK_SET_RATE_PARENT,
1123                         .ops = &clk_branch2_ops,
1124                 },
1125         },
1126 };
1127
1128 static struct clk_branch camss_csi1rdi_clk = {
1129         .halt_reg = 0x3144,
1130         .clkr = {
1131                 .enable_reg = 0x3144,
1132                 .enable_mask = BIT(0),
1133                 .hw.init = &(struct clk_init_data){
1134                         .name = "camss_csi1rdi_clk",
1135                         .parent_names = (const char *[]){
1136                                 "csi1_clk_src",
1137                         },
1138                         .num_parents = 1,
1139                         .flags = CLK_SET_RATE_PARENT,
1140                         .ops = &clk_branch2_ops,
1141                 },
1142         },
1143 };
1144
1145 static struct clk_branch camss_csi2_ahb_clk = {
1146         .halt_reg = 0x3188,
1147         .clkr = {
1148                 .enable_reg = 0x3188,
1149                 .enable_mask = BIT(0),
1150                 .hw.init = &(struct clk_init_data){
1151                         .name = "camss_csi2_ahb_clk",
1152                         .parent_names = (const char *[]){
1153                                 "mmss_ahb_clk_src",
1154                         },
1155                         .num_parents = 1,
1156                         .ops = &clk_branch2_ops,
1157                 },
1158         },
1159 };
1160
1161 static struct clk_branch camss_csi2_clk = {
1162         .halt_reg = 0x3184,
1163         .clkr = {
1164                 .enable_reg = 0x3184,
1165                 .enable_mask = BIT(0),
1166                 .hw.init = &(struct clk_init_data){
1167                         .name = "camss_csi2_clk",
1168                         .parent_names = (const char *[]){
1169                                 "csi2_clk_src",
1170                         },
1171                         .num_parents = 1,
1172                         .flags = CLK_SET_RATE_PARENT,
1173                         .ops = &clk_branch2_ops,
1174                 },
1175         },
1176 };
1177
1178 static struct clk_branch camss_csi2phy_clk = {
1179         .halt_reg = 0x3194,
1180         .clkr = {
1181                 .enable_reg = 0x3194,
1182                 .enable_mask = BIT(0),
1183                 .hw.init = &(struct clk_init_data){
1184                         .name = "camss_csi2phy_clk",
1185                         .parent_names = (const char *[]){
1186                                 "csi2_clk_src",
1187                         },
1188                         .num_parents = 1,
1189                         .flags = CLK_SET_RATE_PARENT,
1190                         .ops = &clk_branch2_ops,
1191                 },
1192         },
1193 };
1194
1195 static struct clk_branch camss_csi2pix_clk = {
1196         .halt_reg = 0x31b4,
1197         .clkr = {
1198                 .enable_reg = 0x31b4,
1199                 .enable_mask = BIT(0),
1200                 .hw.init = &(struct clk_init_data){
1201                         .name = "camss_csi2pix_clk",
1202                         .parent_names = (const char *[]){
1203                                 "csi2_clk_src",
1204                         },
1205                         .num_parents = 1,
1206                         .flags = CLK_SET_RATE_PARENT,
1207                         .ops = &clk_branch2_ops,
1208                 },
1209         },
1210 };
1211
1212 static struct clk_branch camss_csi2rdi_clk = {
1213         .halt_reg = 0x31a4,
1214         .clkr = {
1215                 .enable_reg = 0x31a4,
1216                 .enable_mask = BIT(0),
1217                 .hw.init = &(struct clk_init_data){
1218                         .name = "camss_csi2rdi_clk",
1219                         .parent_names = (const char *[]){
1220                                 "csi2_clk_src",
1221                         },
1222                         .num_parents = 1,
1223                         .flags = CLK_SET_RATE_PARENT,
1224                         .ops = &clk_branch2_ops,
1225                 },
1226         },
1227 };
1228
1229 static struct clk_branch camss_csi3_ahb_clk = {
1230         .halt_reg = 0x31e8,
1231         .clkr = {
1232                 .enable_reg = 0x31e8,
1233                 .enable_mask = BIT(0),
1234                 .hw.init = &(struct clk_init_data){
1235                         .name = "camss_csi3_ahb_clk",
1236                         .parent_names = (const char *[]){
1237                                 "mmss_ahb_clk_src",
1238                         },
1239                         .num_parents = 1,
1240                         .ops = &clk_branch2_ops,
1241                 },
1242         },
1243 };
1244
1245 static struct clk_branch camss_csi3_clk = {
1246         .halt_reg = 0x31e4,
1247         .clkr = {
1248                 .enable_reg = 0x31e4,
1249                 .enable_mask = BIT(0),
1250                 .hw.init = &(struct clk_init_data){
1251                         .name = "camss_csi3_clk",
1252                         .parent_names = (const char *[]){
1253                                 "csi3_clk_src",
1254                         },
1255                         .num_parents = 1,
1256                         .flags = CLK_SET_RATE_PARENT,
1257                         .ops = &clk_branch2_ops,
1258                 },
1259         },
1260 };
1261
1262 static struct clk_branch camss_csi3phy_clk = {
1263         .halt_reg = 0x31f4,
1264         .clkr = {
1265                 .enable_reg = 0x31f4,
1266                 .enable_mask = BIT(0),
1267                 .hw.init = &(struct clk_init_data){
1268                         .name = "camss_csi3phy_clk",
1269                         .parent_names = (const char *[]){
1270                                 "csi3_clk_src",
1271                         },
1272                         .num_parents = 1,
1273                         .flags = CLK_SET_RATE_PARENT,
1274                         .ops = &clk_branch2_ops,
1275                 },
1276         },
1277 };
1278
1279 static struct clk_branch camss_csi3pix_clk = {
1280         .halt_reg = 0x3214,
1281         .clkr = {
1282                 .enable_reg = 0x3214,
1283                 .enable_mask = BIT(0),
1284                 .hw.init = &(struct clk_init_data){
1285                         .name = "camss_csi3pix_clk",
1286                         .parent_names = (const char *[]){
1287                                 "csi3_clk_src",
1288                         },
1289                         .num_parents = 1,
1290                         .flags = CLK_SET_RATE_PARENT,
1291                         .ops = &clk_branch2_ops,
1292                 },
1293         },
1294 };
1295
1296 static struct clk_branch camss_csi3rdi_clk = {
1297         .halt_reg = 0x3204,
1298         .clkr = {
1299                 .enable_reg = 0x3204,
1300                 .enable_mask = BIT(0),
1301                 .hw.init = &(struct clk_init_data){
1302                         .name = "camss_csi3rdi_clk",
1303                         .parent_names = (const char *[]){
1304                                 "csi3_clk_src",
1305                         },
1306                         .num_parents = 1,
1307                         .flags = CLK_SET_RATE_PARENT,
1308                         .ops = &clk_branch2_ops,
1309                 },
1310         },
1311 };
1312
1313 static struct clk_branch camss_csi_vfe0_clk = {
1314         .halt_reg = 0x3704,
1315         .clkr = {
1316                 .enable_reg = 0x3704,
1317                 .enable_mask = BIT(0),
1318                 .hw.init = &(struct clk_init_data){
1319                         .name = "camss_csi_vfe0_clk",
1320                         .parent_names = (const char *[]){
1321                                 "vfe0_clk_src",
1322                         },
1323                         .num_parents = 1,
1324                         .flags = CLK_SET_RATE_PARENT,
1325                         .ops = &clk_branch2_ops,
1326                 },
1327         },
1328 };
1329
1330 static struct clk_branch camss_csi_vfe1_clk = {
1331         .halt_reg = 0x3714,
1332         .clkr = {
1333                 .enable_reg = 0x3714,
1334                 .enable_mask = BIT(0),
1335                 .hw.init = &(struct clk_init_data){
1336                         .name = "camss_csi_vfe1_clk",
1337                         .parent_names = (const char *[]){
1338                                 "vfe1_clk_src",
1339                         },
1340                         .num_parents = 1,
1341                         .flags = CLK_SET_RATE_PARENT,
1342                         .ops = &clk_branch2_ops,
1343                 },
1344         },
1345 };
1346
1347 static struct clk_branch camss_gp0_clk = {
1348         .halt_reg = 0x3444,
1349         .clkr = {
1350                 .enable_reg = 0x3444,
1351                 .enable_mask = BIT(0),
1352                 .hw.init = &(struct clk_init_data){
1353                         .name = "camss_gp0_clk",
1354                         .parent_names = (const char *[]){
1355                                 "camss_gp0_clk_src",
1356                         },
1357                         .num_parents = 1,
1358                         .flags = CLK_SET_RATE_PARENT,
1359                         .ops = &clk_branch2_ops,
1360                 },
1361         },
1362 };
1363
1364 static struct clk_branch camss_gp1_clk = {
1365         .halt_reg = 0x3474,
1366         .clkr = {
1367                 .enable_reg = 0x3474,
1368                 .enable_mask = BIT(0),
1369                 .hw.init = &(struct clk_init_data){
1370                         .name = "camss_gp1_clk",
1371                         .parent_names = (const char *[]){
1372                                 "camss_gp1_clk_src",
1373                         },
1374                         .num_parents = 1,
1375                         .flags = CLK_SET_RATE_PARENT,
1376                         .ops = &clk_branch2_ops,
1377                 },
1378         },
1379 };
1380
1381 static struct clk_branch camss_ispif_ahb_clk = {
1382         .halt_reg = 0x3224,
1383         .clkr = {
1384                 .enable_reg = 0x3224,
1385                 .enable_mask = BIT(0),
1386                 .hw.init = &(struct clk_init_data){
1387                         .name = "camss_ispif_ahb_clk",
1388                         .parent_names = (const char *[]){
1389                                 "mmss_ahb_clk_src",
1390                         },
1391                         .num_parents = 1,
1392                         .ops = &clk_branch2_ops,
1393                 },
1394         },
1395 };
1396
1397 static struct clk_branch camss_jpeg_jpeg0_clk = {
1398         .halt_reg = 0x35a8,
1399         .clkr = {
1400                 .enable_reg = 0x35a8,
1401                 .enable_mask = BIT(0),
1402                 .hw.init = &(struct clk_init_data){
1403                         .name = "camss_jpeg_jpeg0_clk",
1404                         .parent_names = (const char *[]){
1405                                 "jpeg0_clk_src",
1406                         },
1407                         .num_parents = 1,
1408                         .flags = CLK_SET_RATE_PARENT,
1409                         .ops = &clk_branch2_ops,
1410                 },
1411         },
1412 };
1413
1414 static struct clk_branch camss_jpeg_jpeg1_clk = {
1415         .halt_reg = 0x35ac,
1416         .clkr = {
1417                 .enable_reg = 0x35ac,
1418                 .enable_mask = BIT(0),
1419                 .hw.init = &(struct clk_init_data){
1420                         .name = "camss_jpeg_jpeg1_clk",
1421                         .parent_names = (const char *[]){
1422                                 "jpeg1_clk_src",
1423                         },
1424                         .num_parents = 1,
1425                         .flags = CLK_SET_RATE_PARENT,
1426                         .ops = &clk_branch2_ops,
1427                 },
1428         },
1429 };
1430
1431 static struct clk_branch camss_jpeg_jpeg2_clk = {
1432         .halt_reg = 0x35b0,
1433         .clkr = {
1434                 .enable_reg = 0x35b0,
1435                 .enable_mask = BIT(0),
1436                 .hw.init = &(struct clk_init_data){
1437                         .name = "camss_jpeg_jpeg2_clk",
1438                         .parent_names = (const char *[]){
1439                                 "jpeg2_clk_src",
1440                         },
1441                         .num_parents = 1,
1442                         .flags = CLK_SET_RATE_PARENT,
1443                         .ops = &clk_branch2_ops,
1444                 },
1445         },
1446 };
1447
1448 static struct clk_branch camss_jpeg_jpeg_ahb_clk = {
1449         .halt_reg = 0x35b4,
1450         .clkr = {
1451                 .enable_reg = 0x35b4,
1452                 .enable_mask = BIT(0),
1453                 .hw.init = &(struct clk_init_data){
1454                         .name = "camss_jpeg_jpeg_ahb_clk",
1455                         .parent_names = (const char *[]){
1456                                 "mmss_ahb_clk_src",
1457                         },
1458                         .num_parents = 1,
1459                         .ops = &clk_branch2_ops,
1460                 },
1461         },
1462 };
1463
1464 static struct clk_branch camss_jpeg_jpeg_axi_clk = {
1465         .halt_reg = 0x35b8,
1466         .clkr = {
1467                 .enable_reg = 0x35b8,
1468                 .enable_mask = BIT(0),
1469                 .hw.init = &(struct clk_init_data){
1470                         .name = "camss_jpeg_jpeg_axi_clk",
1471                         .parent_names = (const char *[]){
1472                                 "mmss_axi_clk_src",
1473                         },
1474                         .num_parents = 1,
1475                         .ops = &clk_branch2_ops,
1476                 },
1477         },
1478 };
1479
1480 static struct clk_branch camss_jpeg_jpeg_ocmemnoc_clk = {
1481         .halt_reg = 0x35bc,
1482         .clkr = {
1483                 .enable_reg = 0x35bc,
1484                 .enable_mask = BIT(0),
1485                 .hw.init = &(struct clk_init_data){
1486                         .name = "camss_jpeg_jpeg_ocmemnoc_clk",
1487                         .parent_names = (const char *[]){
1488                                 "ocmemnoc_clk_src",
1489                         },
1490                         .num_parents = 1,
1491                         .flags = CLK_SET_RATE_PARENT,
1492                         .ops = &clk_branch2_ops,
1493                 },
1494         },
1495 };
1496
1497 static struct clk_branch camss_mclk0_clk = {
1498         .halt_reg = 0x3384,
1499         .clkr = {
1500                 .enable_reg = 0x3384,
1501                 .enable_mask = BIT(0),
1502                 .hw.init = &(struct clk_init_data){
1503                         .name = "camss_mclk0_clk",
1504                         .parent_names = (const char *[]){
1505                                 "mclk0_clk_src",
1506                         },
1507                         .num_parents = 1,
1508                         .flags = CLK_SET_RATE_PARENT,
1509                         .ops = &clk_branch2_ops,
1510                 },
1511         },
1512 };
1513
1514 static struct clk_branch camss_mclk1_clk = {
1515         .halt_reg = 0x33b4,
1516         .clkr = {
1517                 .enable_reg = 0x33b4,
1518                 .enable_mask = BIT(0),
1519                 .hw.init = &(struct clk_init_data){
1520                         .name = "camss_mclk1_clk",
1521                         .parent_names = (const char *[]){
1522                                 "mclk1_clk_src",
1523                         },
1524                         .num_parents = 1,
1525                         .flags = CLK_SET_RATE_PARENT,
1526                         .ops = &clk_branch2_ops,
1527                 },
1528         },
1529 };
1530
1531 static struct clk_branch camss_mclk2_clk = {
1532         .halt_reg = 0x33e4,
1533         .clkr = {
1534                 .enable_reg = 0x33e4,
1535                 .enable_mask = BIT(0),
1536                 .hw.init = &(struct clk_init_data){
1537                         .name = "camss_mclk2_clk",
1538                         .parent_names = (const char *[]){
1539                                 "mclk2_clk_src",
1540                         },
1541                         .num_parents = 1,
1542                         .flags = CLK_SET_RATE_PARENT,
1543                         .ops = &clk_branch2_ops,
1544                 },
1545         },
1546 };
1547
1548 static struct clk_branch camss_mclk3_clk = {
1549         .halt_reg = 0x3414,
1550         .clkr = {
1551                 .enable_reg = 0x3414,
1552                 .enable_mask = BIT(0),
1553                 .hw.init = &(struct clk_init_data){
1554                         .name = "camss_mclk3_clk",
1555                         .parent_names = (const char *[]){
1556                                 "mclk3_clk_src",
1557                         },
1558                         .num_parents = 1,
1559                         .flags = CLK_SET_RATE_PARENT,
1560                         .ops = &clk_branch2_ops,
1561                 },
1562         },
1563 };
1564
1565 static struct clk_branch camss_micro_ahb_clk = {
1566         .halt_reg = 0x3494,
1567         .clkr = {
1568                 .enable_reg = 0x3494,
1569                 .enable_mask = BIT(0),
1570                 .hw.init = &(struct clk_init_data){
1571                         .name = "camss_micro_ahb_clk",
1572                         .parent_names = (const char *[]){
1573                                 "mmss_ahb_clk_src",
1574                         },
1575                         .num_parents = 1,
1576                         .ops = &clk_branch2_ops,
1577                 },
1578         },
1579 };
1580
1581 static struct clk_branch camss_phy0_csi0phytimer_clk = {
1582         .halt_reg = 0x3024,
1583         .clkr = {
1584                 .enable_reg = 0x3024,
1585                 .enable_mask = BIT(0),
1586                 .hw.init = &(struct clk_init_data){
1587                         .name = "camss_phy0_csi0phytimer_clk",
1588                         .parent_names = (const char *[]){
1589                                 "csi0phytimer_clk_src",
1590                         },
1591                         .num_parents = 1,
1592                         .flags = CLK_SET_RATE_PARENT,
1593                         .ops = &clk_branch2_ops,
1594                 },
1595         },
1596 };
1597
1598 static struct clk_branch camss_phy1_csi1phytimer_clk = {
1599         .halt_reg = 0x3054,
1600         .clkr = {
1601                 .enable_reg = 0x3054,
1602                 .enable_mask = BIT(0),
1603                 .hw.init = &(struct clk_init_data){
1604                         .name = "camss_phy1_csi1phytimer_clk",
1605                         .parent_names = (const char *[]){
1606                                 "csi1phytimer_clk_src",
1607                         },
1608                         .num_parents = 1,
1609                         .flags = CLK_SET_RATE_PARENT,
1610                         .ops = &clk_branch2_ops,
1611                 },
1612         },
1613 };
1614
1615 static struct clk_branch camss_phy2_csi2phytimer_clk = {
1616         .halt_reg = 0x3084,
1617         .clkr = {
1618                 .enable_reg = 0x3084,
1619                 .enable_mask = BIT(0),
1620                 .hw.init = &(struct clk_init_data){
1621                         .name = "camss_phy2_csi2phytimer_clk",
1622                         .parent_names = (const char *[]){
1623                                 "csi2phytimer_clk_src",
1624                         },
1625                         .num_parents = 1,
1626                         .flags = CLK_SET_RATE_PARENT,
1627                         .ops = &clk_branch2_ops,
1628                 },
1629         },
1630 };
1631
1632 static struct clk_branch camss_top_ahb_clk = {
1633         .halt_reg = 0x3484,
1634         .clkr = {
1635                 .enable_reg = 0x3484,
1636                 .enable_mask = BIT(0),
1637                 .hw.init = &(struct clk_init_data){
1638                         .name = "camss_top_ahb_clk",
1639                         .parent_names = (const char *[]){
1640                                 "mmss_ahb_clk_src",
1641                         },
1642                         .num_parents = 1,
1643                         .ops = &clk_branch2_ops,
1644                 },
1645         },
1646 };
1647
1648 static struct clk_branch camss_vfe_cpp_ahb_clk = {
1649         .halt_reg = 0x36b4,
1650         .clkr = {
1651                 .enable_reg = 0x36b4,
1652                 .enable_mask = BIT(0),
1653                 .hw.init = &(struct clk_init_data){
1654                         .name = "camss_vfe_cpp_ahb_clk",
1655                         .parent_names = (const char *[]){
1656                                 "mmss_ahb_clk_src",
1657                         },
1658                         .num_parents = 1,
1659                         .ops = &clk_branch2_ops,
1660                 },
1661         },
1662 };
1663
1664 static struct clk_branch camss_vfe_cpp_clk = {
1665         .halt_reg = 0x36b0,
1666         .clkr = {
1667                 .enable_reg = 0x36b0,
1668                 .enable_mask = BIT(0),
1669                 .hw.init = &(struct clk_init_data){
1670                         .name = "camss_vfe_cpp_clk",
1671                         .parent_names = (const char *[]){
1672                                 "cpp_clk_src",
1673                         },
1674                         .num_parents = 1,
1675                         .flags = CLK_SET_RATE_PARENT,
1676                         .ops = &clk_branch2_ops,
1677                 },
1678         },
1679 };
1680
1681 static struct clk_branch camss_vfe_vfe0_clk = {
1682         .halt_reg = 0x36a8,
1683         .clkr = {
1684                 .enable_reg = 0x36a8,
1685                 .enable_mask = BIT(0),
1686                 .hw.init = &(struct clk_init_data){
1687                         .name = "camss_vfe_vfe0_clk",
1688                         .parent_names = (const char *[]){
1689                                 "vfe0_clk_src",
1690                         },
1691                         .num_parents = 1,
1692                         .flags = CLK_SET_RATE_PARENT,
1693                         .ops = &clk_branch2_ops,
1694                 },
1695         },
1696 };
1697
1698 static struct clk_branch camss_vfe_vfe1_clk = {
1699         .halt_reg = 0x36ac,
1700         .clkr = {
1701                 .enable_reg = 0x36ac,
1702                 .enable_mask = BIT(0),
1703                 .hw.init = &(struct clk_init_data){
1704                         .name = "camss_vfe_vfe1_clk",
1705                         .parent_names = (const char *[]){
1706                                 "vfe1_clk_src",
1707                         },
1708                         .num_parents = 1,
1709                         .flags = CLK_SET_RATE_PARENT,
1710                         .ops = &clk_branch2_ops,
1711                 },
1712         },
1713 };
1714
1715 static struct clk_branch camss_vfe_vfe_ahb_clk = {
1716         .halt_reg = 0x36b8,
1717         .clkr = {
1718                 .enable_reg = 0x36b8,
1719                 .enable_mask = BIT(0),
1720                 .hw.init = &(struct clk_init_data){
1721                         .name = "camss_vfe_vfe_ahb_clk",
1722                         .parent_names = (const char *[]){
1723                                 "mmss_ahb_clk_src",
1724                         },
1725                         .num_parents = 1,
1726                         .ops = &clk_branch2_ops,
1727                 },
1728         },
1729 };
1730
1731 static struct clk_branch camss_vfe_vfe_axi_clk = {
1732         .halt_reg = 0x36bc,
1733         .clkr = {
1734                 .enable_reg = 0x36bc,
1735                 .enable_mask = BIT(0),
1736                 .hw.init = &(struct clk_init_data){
1737                         .name = "camss_vfe_vfe_axi_clk",
1738                         .parent_names = (const char *[]){
1739                                 "mmss_axi_clk_src",
1740                         },
1741                         .num_parents = 1,
1742                         .ops = &clk_branch2_ops,
1743                 },
1744         },
1745 };
1746
1747 static struct clk_branch camss_vfe_vfe_ocmemnoc_clk = {
1748         .halt_reg = 0x36c0,
1749         .clkr = {
1750                 .enable_reg = 0x36c0,
1751                 .enable_mask = BIT(0),
1752                 .hw.init = &(struct clk_init_data){
1753                         .name = "camss_vfe_vfe_ocmemnoc_clk",
1754                         .parent_names = (const char *[]){
1755                                 "ocmemnoc_clk_src",
1756                         },
1757                         .num_parents = 1,
1758                         .flags = CLK_SET_RATE_PARENT,
1759                         .ops = &clk_branch2_ops,
1760                 },
1761         },
1762 };
1763
1764 static struct clk_branch mdss_ahb_clk = {
1765         .halt_reg = 0x2308,
1766         .clkr = {
1767                 .enable_reg = 0x2308,
1768                 .enable_mask = BIT(0),
1769                 .hw.init = &(struct clk_init_data){
1770                         .name = "mdss_ahb_clk",
1771                         .parent_names = (const char *[]){
1772                                 "mmss_ahb_clk_src",
1773                         },
1774                         .num_parents = 1,
1775                         .ops = &clk_branch2_ops,
1776                 },
1777         },
1778 };
1779
1780 static struct clk_branch mdss_axi_clk = {
1781         .halt_reg = 0x2310,
1782         .clkr = {
1783                 .enable_reg = 0x2310,
1784                 .enable_mask = BIT(0),
1785                 .hw.init = &(struct clk_init_data){
1786                         .name = "mdss_axi_clk",
1787                         .parent_names = (const char *[]){
1788                                 "mmss_axi_clk_src",
1789                         },
1790                         .num_parents = 1,
1791                         .flags = CLK_SET_RATE_PARENT,
1792                         .ops = &clk_branch2_ops,
1793                 },
1794         },
1795 };
1796
1797 static struct clk_branch mdss_byte0_clk = {
1798         .halt_reg = 0x233c,
1799         .clkr = {
1800                 .enable_reg = 0x233c,
1801                 .enable_mask = BIT(0),
1802                 .hw.init = &(struct clk_init_data){
1803                         .name = "mdss_byte0_clk",
1804                         .parent_names = (const char *[]){
1805                                 "byte0_clk_src",
1806                         },
1807                         .num_parents = 1,
1808                         .flags = CLK_SET_RATE_PARENT,
1809                         .ops = &clk_branch2_ops,
1810                 },
1811         },
1812 };
1813
1814 static struct clk_branch mdss_byte1_clk = {
1815         .halt_reg = 0x2340,
1816         .clkr = {
1817                 .enable_reg = 0x2340,
1818                 .enable_mask = BIT(0),
1819                 .hw.init = &(struct clk_init_data){
1820                         .name = "mdss_byte1_clk",
1821                         .parent_names = (const char *[]){
1822                                 "byte1_clk_src",
1823                         },
1824                         .num_parents = 1,
1825                         .flags = CLK_SET_RATE_PARENT,
1826                         .ops = &clk_branch2_ops,
1827                 },
1828         },
1829 };
1830
1831 static struct clk_branch mdss_edpaux_clk = {
1832         .halt_reg = 0x2334,
1833         .clkr = {
1834                 .enable_reg = 0x2334,
1835                 .enable_mask = BIT(0),
1836                 .hw.init = &(struct clk_init_data){
1837                         .name = "mdss_edpaux_clk",
1838                         .parent_names = (const char *[]){
1839                                 "edpaux_clk_src",
1840                         },
1841                         .num_parents = 1,
1842                         .flags = CLK_SET_RATE_PARENT,
1843                         .ops = &clk_branch2_ops,
1844                 },
1845         },
1846 };
1847
1848 static struct clk_branch mdss_edplink_clk = {
1849         .halt_reg = 0x2330,
1850         .clkr = {
1851                 .enable_reg = 0x2330,
1852                 .enable_mask = BIT(0),
1853                 .hw.init = &(struct clk_init_data){
1854                         .name = "mdss_edplink_clk",
1855                         .parent_names = (const char *[]){
1856                                 "edplink_clk_src",
1857                         },
1858                         .num_parents = 1,
1859                         .flags = CLK_SET_RATE_PARENT,
1860                         .ops = &clk_branch2_ops,
1861                 },
1862         },
1863 };
1864
1865 static struct clk_branch mdss_edppixel_clk = {
1866         .halt_reg = 0x232c,
1867         .clkr = {
1868                 .enable_reg = 0x232c,
1869                 .enable_mask = BIT(0),
1870                 .hw.init = &(struct clk_init_data){
1871                         .name = "mdss_edppixel_clk",
1872                         .parent_names = (const char *[]){
1873                                 "edppixel_clk_src",
1874                         },
1875                         .num_parents = 1,
1876                         .flags = CLK_SET_RATE_PARENT,
1877                         .ops = &clk_branch2_ops,
1878                 },
1879         },
1880 };
1881
1882 static struct clk_branch mdss_esc0_clk = {
1883         .halt_reg = 0x2344,
1884         .clkr = {
1885                 .enable_reg = 0x2344,
1886                 .enable_mask = BIT(0),
1887                 .hw.init = &(struct clk_init_data){
1888                         .name = "mdss_esc0_clk",
1889                         .parent_names = (const char *[]){
1890                                 "esc0_clk_src",
1891                         },
1892                         .num_parents = 1,
1893                         .flags = CLK_SET_RATE_PARENT,
1894                         .ops = &clk_branch2_ops,
1895                 },
1896         },
1897 };
1898
1899 static struct clk_branch mdss_esc1_clk = {
1900         .halt_reg = 0x2348,
1901         .clkr = {
1902                 .enable_reg = 0x2348,
1903                 .enable_mask = BIT(0),
1904                 .hw.init = &(struct clk_init_data){
1905                         .name = "mdss_esc1_clk",
1906                         .parent_names = (const char *[]){
1907                                 "esc1_clk_src",
1908                         },
1909                         .num_parents = 1,
1910                         .flags = CLK_SET_RATE_PARENT,
1911                         .ops = &clk_branch2_ops,
1912                 },
1913         },
1914 };
1915
1916 static struct clk_branch mdss_extpclk_clk = {
1917         .halt_reg = 0x2324,
1918         .clkr = {
1919                 .enable_reg = 0x2324,
1920                 .enable_mask = BIT(0),
1921                 .hw.init = &(struct clk_init_data){
1922                         .name = "mdss_extpclk_clk",
1923                         .parent_names = (const char *[]){
1924                                 "extpclk_clk_src",
1925                         },
1926                         .num_parents = 1,
1927                         .flags = CLK_SET_RATE_PARENT,
1928                         .ops = &clk_branch2_ops,
1929                 },
1930         },
1931 };
1932
1933 static struct clk_branch mdss_hdmi_ahb_clk = {
1934         .halt_reg = 0x230c,
1935         .clkr = {
1936                 .enable_reg = 0x230c,
1937                 .enable_mask = BIT(0),
1938                 .hw.init = &(struct clk_init_data){
1939                         .name = "mdss_hdmi_ahb_clk",
1940                         .parent_names = (const char *[]){
1941                                 "mmss_ahb_clk_src",
1942                         },
1943                         .num_parents = 1,
1944                         .ops = &clk_branch2_ops,
1945                 },
1946         },
1947 };
1948
1949 static struct clk_branch mdss_hdmi_clk = {
1950         .halt_reg = 0x2338,
1951         .clkr = {
1952                 .enable_reg = 0x2338,
1953                 .enable_mask = BIT(0),
1954                 .hw.init = &(struct clk_init_data){
1955                         .name = "mdss_hdmi_clk",
1956                         .parent_names = (const char *[]){
1957                                 "hdmi_clk_src",
1958                         },
1959                         .num_parents = 1,
1960                         .flags = CLK_SET_RATE_PARENT,
1961                         .ops = &clk_branch2_ops,
1962                 },
1963         },
1964 };
1965
1966 static struct clk_branch mdss_mdp_clk = {
1967         .halt_reg = 0x231c,
1968         .clkr = {
1969                 .enable_reg = 0x231c,
1970                 .enable_mask = BIT(0),
1971                 .hw.init = &(struct clk_init_data){
1972                         .name = "mdss_mdp_clk",
1973                         .parent_names = (const char *[]){
1974                                 "mdp_clk_src",
1975                         },
1976                         .num_parents = 1,
1977                         .flags = CLK_SET_RATE_PARENT,
1978                         .ops = &clk_branch2_ops,
1979                 },
1980         },
1981 };
1982
1983 static struct clk_branch mdss_mdp_lut_clk = {
1984         .halt_reg = 0x2320,
1985         .clkr = {
1986                 .enable_reg = 0x2320,
1987                 .enable_mask = BIT(0),
1988                 .hw.init = &(struct clk_init_data){
1989                         .name = "mdss_mdp_lut_clk",
1990                         .parent_names = (const char *[]){
1991                                 "mdp_clk_src",
1992                         },
1993                         .num_parents = 1,
1994                         .flags = CLK_SET_RATE_PARENT,
1995                         .ops = &clk_branch2_ops,
1996                 },
1997         },
1998 };
1999
2000 static struct clk_branch mdss_pclk0_clk = {
2001         .halt_reg = 0x2314,
2002         .clkr = {
2003                 .enable_reg = 0x2314,
2004                 .enable_mask = BIT(0),
2005                 .hw.init = &(struct clk_init_data){
2006                         .name = "mdss_pclk0_clk",
2007                         .parent_names = (const char *[]){
2008                                 "pclk0_clk_src",
2009                         },
2010                         .num_parents = 1,
2011                         .flags = CLK_SET_RATE_PARENT,
2012                         .ops = &clk_branch2_ops,
2013                 },
2014         },
2015 };
2016
2017 static struct clk_branch mdss_pclk1_clk = {
2018         .halt_reg = 0x2318,
2019         .clkr = {
2020                 .enable_reg = 0x2318,
2021                 .enable_mask = BIT(0),
2022                 .hw.init = &(struct clk_init_data){
2023                         .name = "mdss_pclk1_clk",
2024                         .parent_names = (const char *[]){
2025                                 "pclk1_clk_src",
2026                         },
2027                         .num_parents = 1,
2028                         .flags = CLK_SET_RATE_PARENT,
2029                         .ops = &clk_branch2_ops,
2030                 },
2031         },
2032 };
2033
2034 static struct clk_branch mdss_vsync_clk = {
2035         .halt_reg = 0x2328,
2036         .clkr = {
2037                 .enable_reg = 0x2328,
2038                 .enable_mask = BIT(0),
2039                 .hw.init = &(struct clk_init_data){
2040                         .name = "mdss_vsync_clk",
2041                         .parent_names = (const char *[]){
2042                                 "vsync_clk_src",
2043                         },
2044                         .num_parents = 1,
2045                         .flags = CLK_SET_RATE_PARENT,
2046                         .ops = &clk_branch2_ops,
2047                 },
2048         },
2049 };
2050
2051 static struct clk_branch mmss_misc_ahb_clk = {
2052         .halt_reg = 0x502c,
2053         .clkr = {
2054                 .enable_reg = 0x502c,
2055                 .enable_mask = BIT(0),
2056                 .hw.init = &(struct clk_init_data){
2057                         .name = "mmss_misc_ahb_clk",
2058                         .parent_names = (const char *[]){
2059                                 "mmss_ahb_clk_src",
2060                         },
2061                         .num_parents = 1,
2062                         .ops = &clk_branch2_ops,
2063                 },
2064         },
2065 };
2066
2067 static struct clk_branch mmss_mmssnoc_ahb_clk = {
2068         .halt_reg = 0x5024,
2069         .clkr = {
2070                 .enable_reg = 0x5024,
2071                 .enable_mask = BIT(0),
2072                 .hw.init = &(struct clk_init_data){
2073                         .name = "mmss_mmssnoc_ahb_clk",
2074                         .parent_names = (const char *[]){
2075                                 "mmss_ahb_clk_src",
2076                         },
2077                         .num_parents = 1,
2078                         .ops = &clk_branch2_ops,
2079                         .flags = CLK_IGNORE_UNUSED,
2080                 },
2081         },
2082 };
2083
2084 static struct clk_branch mmss_mmssnoc_bto_ahb_clk = {
2085         .halt_reg = 0x5028,
2086         .clkr = {
2087                 .enable_reg = 0x5028,
2088                 .enable_mask = BIT(0),
2089                 .hw.init = &(struct clk_init_data){
2090                         .name = "mmss_mmssnoc_bto_ahb_clk",
2091                         .parent_names = (const char *[]){
2092                                 "mmss_ahb_clk_src",
2093                         },
2094                         .num_parents = 1,
2095                         .ops = &clk_branch2_ops,
2096                         .flags = CLK_IGNORE_UNUSED,
2097                 },
2098         },
2099 };
2100
2101 static struct clk_branch mmss_mmssnoc_axi_clk = {
2102         .halt_reg = 0x506c,
2103         .clkr = {
2104                 .enable_reg = 0x506c,
2105                 .enable_mask = BIT(0),
2106                 .hw.init = &(struct clk_init_data){
2107                         .name = "mmss_mmssnoc_axi_clk",
2108                         .parent_names = (const char *[]){
2109                                 "mmss_axi_clk_src",
2110                         },
2111                         .num_parents = 1,
2112                         .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2113                         .ops = &clk_branch2_ops,
2114                 },
2115         },
2116 };
2117
2118 static struct clk_branch mmss_s0_axi_clk = {
2119         .halt_reg = 0x5064,
2120         .clkr = {
2121                 .enable_reg = 0x5064,
2122                 .enable_mask = BIT(0),
2123                 .hw.init = &(struct clk_init_data){
2124                         .name = "mmss_s0_axi_clk",
2125                         .parent_names = (const char *[]){
2126                                 "mmss_axi_clk_src",
2127                         },
2128                         .num_parents = 1,
2129                         .ops = &clk_branch2_ops,
2130                         .flags = CLK_IGNORE_UNUSED,
2131                 },
2132         },
2133 };
2134
2135 static struct clk_branch ocmemcx_ahb_clk = {
2136         .halt_reg = 0x405c,
2137         .clkr = {
2138                 .enable_reg = 0x405c,
2139                 .enable_mask = BIT(0),
2140                 .hw.init = &(struct clk_init_data){
2141                         .name = "ocmemcx_ahb_clk",
2142                         .parent_names = (const char *[]){
2143                                 "mmss_ahb_clk_src",
2144                         },
2145                         .num_parents = 1,
2146                         .ops = &clk_branch2_ops,
2147                 },
2148         },
2149 };
2150
2151 static struct clk_branch ocmemcx_ocmemnoc_clk = {
2152         .halt_reg = 0x4058,
2153         .clkr = {
2154                 .enable_reg = 0x4058,
2155                 .enable_mask = BIT(0),
2156                 .hw.init = &(struct clk_init_data){
2157                         .name = "ocmemcx_ocmemnoc_clk",
2158                         .parent_names = (const char *[]){
2159                                 "ocmemnoc_clk_src",
2160                         },
2161                         .num_parents = 1,
2162                         .flags = CLK_SET_RATE_PARENT,
2163                         .ops = &clk_branch2_ops,
2164                 },
2165         },
2166 };
2167
2168 static struct clk_branch oxili_ocmemgx_clk = {
2169         .halt_reg = 0x402c,
2170         .clkr = {
2171                 .enable_reg = 0x402c,
2172                 .enable_mask = BIT(0),
2173                 .hw.init = &(struct clk_init_data){
2174                         .name = "oxili_ocmemgx_clk",
2175                         .parent_names = (const char *[]){
2176                                 "gfx3d_clk_src",
2177                         },
2178                         .num_parents = 1,
2179                         .flags = CLK_SET_RATE_PARENT,
2180                         .ops = &clk_branch2_ops,
2181                 },
2182         },
2183 };
2184
2185 static struct clk_branch ocmemnoc_clk = {
2186         .halt_reg = 0x50b4,
2187         .clkr = {
2188                 .enable_reg = 0x50b4,
2189                 .enable_mask = BIT(0),
2190                 .hw.init = &(struct clk_init_data){
2191                         .name = "ocmemnoc_clk",
2192                         .parent_names = (const char *[]){
2193                                 "ocmemnoc_clk_src",
2194                         },
2195                         .num_parents = 1,
2196                         .flags = CLK_SET_RATE_PARENT,
2197                         .ops = &clk_branch2_ops,
2198                 },
2199         },
2200 };
2201
2202 static struct clk_branch oxili_gfx3d_clk = {
2203         .halt_reg = 0x4028,
2204         .clkr = {
2205                 .enable_reg = 0x4028,
2206                 .enable_mask = BIT(0),
2207                 .hw.init = &(struct clk_init_data){
2208                         .name = "oxili_gfx3d_clk",
2209                         .parent_names = (const char *[]){
2210                                 "gfx3d_clk_src",
2211                         },
2212                         .num_parents = 1,
2213                         .flags = CLK_SET_RATE_PARENT,
2214                         .ops = &clk_branch2_ops,
2215                 },
2216         },
2217 };
2218
2219 static struct clk_branch oxilicx_ahb_clk = {
2220         .halt_reg = 0x403c,
2221         .clkr = {
2222                 .enable_reg = 0x403c,
2223                 .enable_mask = BIT(0),
2224                 .hw.init = &(struct clk_init_data){
2225                         .name = "oxilicx_ahb_clk",
2226                         .parent_names = (const char *[]){
2227                                 "mmss_ahb_clk_src",
2228                         },
2229                         .num_parents = 1,
2230                         .ops = &clk_branch2_ops,
2231                 },
2232         },
2233 };
2234
2235 static struct clk_branch oxilicx_axi_clk = {
2236         .halt_reg = 0x4038,
2237         .clkr = {
2238                 .enable_reg = 0x4038,
2239                 .enable_mask = BIT(0),
2240                 .hw.init = &(struct clk_init_data){
2241                         .name = "oxilicx_axi_clk",
2242                         .parent_names = (const char *[]){
2243                                 "mmss_axi_clk_src",
2244                         },
2245                         .num_parents = 1,
2246                         .ops = &clk_branch2_ops,
2247                 },
2248         },
2249 };
2250
2251 static struct clk_branch venus0_ahb_clk = {
2252         .halt_reg = 0x1030,
2253         .clkr = {
2254                 .enable_reg = 0x1030,
2255                 .enable_mask = BIT(0),
2256                 .hw.init = &(struct clk_init_data){
2257                         .name = "venus0_ahb_clk",
2258                         .parent_names = (const char *[]){
2259                                 "mmss_ahb_clk_src",
2260                         },
2261                         .num_parents = 1,
2262                         .ops = &clk_branch2_ops,
2263                 },
2264         },
2265 };
2266
2267 static struct clk_branch venus0_axi_clk = {
2268         .halt_reg = 0x1034,
2269         .clkr = {
2270                 .enable_reg = 0x1034,
2271                 .enable_mask = BIT(0),
2272                 .hw.init = &(struct clk_init_data){
2273                         .name = "venus0_axi_clk",
2274                         .parent_names = (const char *[]){
2275                                 "mmss_axi_clk_src",
2276                         },
2277                         .num_parents = 1,
2278                         .ops = &clk_branch2_ops,
2279                 },
2280         },
2281 };
2282
2283 static struct clk_branch venus0_ocmemnoc_clk = {
2284         .halt_reg = 0x1038,
2285         .clkr = {
2286                 .enable_reg = 0x1038,
2287                 .enable_mask = BIT(0),
2288                 .hw.init = &(struct clk_init_data){
2289                         .name = "venus0_ocmemnoc_clk",
2290                         .parent_names = (const char *[]){
2291                                 "ocmemnoc_clk_src",
2292                         },
2293                         .num_parents = 1,
2294                         .flags = CLK_SET_RATE_PARENT,
2295                         .ops = &clk_branch2_ops,
2296                 },
2297         },
2298 };
2299
2300 static struct clk_branch venus0_vcodec0_clk = {
2301         .halt_reg = 0x1028,
2302         .clkr = {
2303                 .enable_reg = 0x1028,
2304                 .enable_mask = BIT(0),
2305                 .hw.init = &(struct clk_init_data){
2306                         .name = "venus0_vcodec0_clk",
2307                         .parent_names = (const char *[]){
2308                                 "vcodec0_clk_src",
2309                         },
2310                         .num_parents = 1,
2311                         .flags = CLK_SET_RATE_PARENT,
2312                         .ops = &clk_branch2_ops,
2313                 },
2314         },
2315 };
2316
2317 static const struct pll_config mmpll1_config = {
2318         .l = 60,
2319         .m = 25,
2320         .n = 32,
2321         .vco_val = 0x0,
2322         .vco_mask = 0x3 << 20,
2323         .pre_div_val = 0x0,
2324         .pre_div_mask = 0x7 << 12,
2325         .post_div_val = 0x0,
2326         .post_div_mask = 0x3 << 8,
2327         .mn_ena_mask = BIT(24),
2328         .main_output_mask = BIT(0),
2329 };
2330
2331 static struct pll_config mmpll3_config = {
2332         .l = 48,
2333         .m = 7,
2334         .n = 16,
2335         .vco_val = 0x0,
2336         .vco_mask = 0x3 << 20,
2337         .pre_div_val = 0x0,
2338         .pre_div_mask = 0x7 << 12,
2339         .post_div_val = 0x0,
2340         .post_div_mask = 0x3 << 8,
2341         .mn_ena_mask = BIT(24),
2342         .main_output_mask = BIT(0),
2343         .aux_output_mask = BIT(1),
2344 };
2345
2346 static struct clk_regmap *mmcc_msm8974_clocks[] = {
2347         [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
2348         [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
2349         [OCMEMNOC_CLK_SRC] = &ocmemnoc_clk_src.clkr,
2350         [MMPLL0] = &mmpll0.clkr,
2351         [MMPLL0_VOTE] = &mmpll0_vote,
2352         [MMPLL1] = &mmpll1.clkr,
2353         [MMPLL1_VOTE] = &mmpll1_vote,
2354         [MMPLL2] = &mmpll2.clkr,
2355         [MMPLL3] = &mmpll3.clkr,
2356         [CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2357         [CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2358         [CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2359         [CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2360         [VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2361         [VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2362         [MDP_CLK_SRC] = &mdp_clk_src.clkr,
2363         [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2364         [JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2365         [JPEG1_CLK_SRC] = &jpeg1_clk_src.clkr,
2366         [JPEG2_CLK_SRC] = &jpeg2_clk_src.clkr,
2367         [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2368         [PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2369         [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr,
2370         [CCI_CLK_SRC] = &cci_clk_src.clkr,
2371         [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr,
2372         [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr,
2373         [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2374         [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2375         [MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2376         [MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2377         [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2378         [CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2379         [CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2380         [CPP_CLK_SRC] = &cpp_clk_src.clkr,
2381         [BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2382         [BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2383         [EDPAUX_CLK_SRC] = &edpaux_clk_src.clkr,
2384         [EDPLINK_CLK_SRC] = &edplink_clk_src.clkr,
2385         [EDPPIXEL_CLK_SRC] = &edppixel_clk_src.clkr,
2386         [ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2387         [ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2388         [EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2389         [HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2390         [VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2391         [CAMSS_CCI_CCI_AHB_CLK] = &camss_cci_cci_ahb_clk.clkr,
2392         [CAMSS_CCI_CCI_CLK] = &camss_cci_cci_clk.clkr,
2393         [CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2394         [CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2395         [CAMSS_CSI0PHY_CLK] = &camss_csi0phy_clk.clkr,
2396         [CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2397         [CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2398         [CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2399         [CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2400         [CAMSS_CSI1PHY_CLK] = &camss_csi1phy_clk.clkr,
2401         [CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2402         [CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2403         [CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2404         [CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2405         [CAMSS_CSI2PHY_CLK] = &camss_csi2phy_clk.clkr,
2406         [CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2407         [CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2408         [CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2409         [CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2410         [CAMSS_CSI3PHY_CLK] = &camss_csi3phy_clk.clkr,
2411         [CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2412         [CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2413         [CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2414         [CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2415         [CAMSS_GP0_CLK] = &camss_gp0_clk.clkr,
2416         [CAMSS_GP1_CLK] = &camss_gp1_clk.clkr,
2417         [CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2418         [CAMSS_JPEG_JPEG0_CLK] = &camss_jpeg_jpeg0_clk.clkr,
2419         [CAMSS_JPEG_JPEG1_CLK] = &camss_jpeg_jpeg1_clk.clkr,
2420         [CAMSS_JPEG_JPEG2_CLK] = &camss_jpeg_jpeg2_clk.clkr,
2421         [CAMSS_JPEG_JPEG_AHB_CLK] = &camss_jpeg_jpeg_ahb_clk.clkr,
2422         [CAMSS_JPEG_JPEG_AXI_CLK] = &camss_jpeg_jpeg_axi_clk.clkr,
2423         [CAMSS_JPEG_JPEG_OCMEMNOC_CLK] = &camss_jpeg_jpeg_ocmemnoc_clk.clkr,
2424         [CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2425         [CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2426         [CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2427         [CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2428         [CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2429         [CAMSS_PHY0_CSI0PHYTIMER_CLK] = &camss_phy0_csi0phytimer_clk.clkr,
2430         [CAMSS_PHY1_CSI1PHYTIMER_CLK] = &camss_phy1_csi1phytimer_clk.clkr,
2431         [CAMSS_PHY2_CSI2PHYTIMER_CLK] = &camss_phy2_csi2phytimer_clk.clkr,
2432         [CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2433         [CAMSS_VFE_CPP_AHB_CLK] = &camss_vfe_cpp_ahb_clk.clkr,
2434         [CAMSS_VFE_CPP_CLK] = &camss_vfe_cpp_clk.clkr,
2435         [CAMSS_VFE_VFE0_CLK] = &camss_vfe_vfe0_clk.clkr,
2436         [CAMSS_VFE_VFE1_CLK] = &camss_vfe_vfe1_clk.clkr,
2437         [CAMSS_VFE_VFE_AHB_CLK] = &camss_vfe_vfe_ahb_clk.clkr,
2438         [CAMSS_VFE_VFE_AXI_CLK] = &camss_vfe_vfe_axi_clk.clkr,
2439         [CAMSS_VFE_VFE_OCMEMNOC_CLK] = &camss_vfe_vfe_ocmemnoc_clk.clkr,
2440         [MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2441         [MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2442         [MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2443         [MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2444         [MDSS_EDPAUX_CLK] = &mdss_edpaux_clk.clkr,
2445         [MDSS_EDPLINK_CLK] = &mdss_edplink_clk.clkr,
2446         [MDSS_EDPPIXEL_CLK] = &mdss_edppixel_clk.clkr,
2447         [MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2448         [MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2449         [MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2450         [MDSS_HDMI_AHB_CLK] = &mdss_hdmi_ahb_clk.clkr,
2451         [MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2452         [MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2453         [MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2454         [MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2455         [MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2456         [MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2457         [MMSS_MISC_AHB_CLK] = &mmss_misc_ahb_clk.clkr,
2458         [MMSS_MMSSNOC_AHB_CLK] = &mmss_mmssnoc_ahb_clk.clkr,
2459         [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
2460         [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
2461         [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
2462         [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
2463         [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
2464         [OXILI_OCMEMGX_CLK] = &oxili_ocmemgx_clk.clkr,
2465         [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
2466         [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
2467         [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
2468         [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
2469         [VENUS0_AHB_CLK] = &venus0_ahb_clk.clkr,
2470         [VENUS0_AXI_CLK] = &venus0_axi_clk.clkr,
2471         [VENUS0_OCMEMNOC_CLK] = &venus0_ocmemnoc_clk.clkr,
2472         [VENUS0_VCODEC0_CLK] = &venus0_vcodec0_clk.clkr,
2473 };
2474
2475 static const struct qcom_reset_map mmcc_msm8974_resets[] = {
2476         [SPDM_RESET] = { 0x0200 },
2477         [SPDM_RM_RESET] = { 0x0300 },
2478         [VENUS0_RESET] = { 0x1020 },
2479         [MDSS_RESET] = { 0x2300 },
2480         [CAMSS_PHY0_RESET] = { 0x3020 },
2481         [CAMSS_PHY1_RESET] = { 0x3050 },
2482         [CAMSS_PHY2_RESET] = { 0x3080 },
2483         [CAMSS_CSI0_RESET] = { 0x30b0 },
2484         [CAMSS_CSI0PHY_RESET] = { 0x30c0 },
2485         [CAMSS_CSI0RDI_RESET] = { 0x30d0 },
2486         [CAMSS_CSI0PIX_RESET] = { 0x30e0 },
2487         [CAMSS_CSI1_RESET] = { 0x3120 },
2488         [CAMSS_CSI1PHY_RESET] = { 0x3130 },
2489         [CAMSS_CSI1RDI_RESET] = { 0x3140 },
2490         [CAMSS_CSI1PIX_RESET] = { 0x3150 },
2491         [CAMSS_CSI2_RESET] = { 0x3180 },
2492         [CAMSS_CSI2PHY_RESET] = { 0x3190 },
2493         [CAMSS_CSI2RDI_RESET] = { 0x31a0 },
2494         [CAMSS_CSI2PIX_RESET] = { 0x31b0 },
2495         [CAMSS_CSI3_RESET] = { 0x31e0 },
2496         [CAMSS_CSI3PHY_RESET] = { 0x31f0 },
2497         [CAMSS_CSI3RDI_RESET] = { 0x3200 },
2498         [CAMSS_CSI3PIX_RESET] = { 0x3210 },
2499         [CAMSS_ISPIF_RESET] = { 0x3220 },
2500         [CAMSS_CCI_RESET] = { 0x3340 },
2501         [CAMSS_MCLK0_RESET] = { 0x3380 },
2502         [CAMSS_MCLK1_RESET] = { 0x33b0 },
2503         [CAMSS_MCLK2_RESET] = { 0x33e0 },
2504         [CAMSS_MCLK3_RESET] = { 0x3410 },
2505         [CAMSS_GP0_RESET] = { 0x3440 },
2506         [CAMSS_GP1_RESET] = { 0x3470 },
2507         [CAMSS_TOP_RESET] = { 0x3480 },
2508         [CAMSS_MICRO_RESET] = { 0x3490 },
2509         [CAMSS_JPEG_RESET] = { 0x35a0 },
2510         [CAMSS_VFE_RESET] = { 0x36a0 },
2511         [CAMSS_CSI_VFE0_RESET] = { 0x3700 },
2512         [CAMSS_CSI_VFE1_RESET] = { 0x3710 },
2513         [OXILI_RESET] = { 0x4020 },
2514         [OXILICX_RESET] = { 0x4030 },
2515         [OCMEMCX_RESET] = { 0x4050 },
2516         [MMSS_RBCRP_RESET] = { 0x4080 },
2517         [MMSSNOCAHB_RESET] = { 0x5020 },
2518         [MMSSNOCAXI_RESET] = { 0x5060 },
2519         [OCMEMNOC_RESET] = { 0x50b0 },
2520 };
2521
2522 static const struct regmap_config mmcc_msm8974_regmap_config = {
2523         .reg_bits       = 32,
2524         .reg_stride     = 4,
2525         .val_bits       = 32,
2526         .max_register   = 0x5104,
2527         .fast_io        = true,
2528 };
2529
2530 static const struct of_device_id mmcc_msm8974_match_table[] = {
2531         { .compatible = "qcom,mmcc-msm8974" },
2532         { }
2533 };
2534 MODULE_DEVICE_TABLE(of, mmcc_msm8974_match_table);
2535
2536 struct qcom_cc {
2537         struct qcom_reset_controller reset;
2538         struct clk_onecell_data data;
2539         struct clk *clks[];
2540 };
2541
2542 static int mmcc_msm8974_probe(struct platform_device *pdev)
2543 {
2544         void __iomem *base;
2545         struct resource *res;
2546         int i, ret;
2547         struct device *dev = &pdev->dev;
2548         struct clk *clk;
2549         struct clk_onecell_data *data;
2550         struct clk **clks;
2551         struct regmap *regmap;
2552         size_t num_clks;
2553         struct qcom_reset_controller *reset;
2554         struct qcom_cc *cc;
2555
2556         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2557         base = devm_ioremap_resource(dev, res);
2558         if (IS_ERR(base))
2559                 return PTR_ERR(base);
2560
2561         regmap = devm_regmap_init_mmio(dev, base, &mmcc_msm8974_regmap_config);
2562         if (IS_ERR(regmap))
2563                 return PTR_ERR(regmap);
2564
2565         num_clks = ARRAY_SIZE(mmcc_msm8974_clocks);
2566         cc = devm_kzalloc(dev, sizeof(*cc) + sizeof(*clks) * num_clks,
2567                           GFP_KERNEL);
2568         if (!cc)
2569                 return -ENOMEM;
2570
2571         clks = cc->clks;
2572         data = &cc->data;
2573         data->clks = clks;
2574         data->clk_num = num_clks;
2575
2576         clk_pll_configure_sr_hpm_lp(&mmpll1, regmap, &mmpll1_config, true);
2577         clk_pll_configure_sr_hpm_lp(&mmpll3, regmap, &mmpll3_config, false);
2578
2579         for (i = 0; i < num_clks; i++) {
2580                 if (!mmcc_msm8974_clocks[i])
2581                         continue;
2582                 clk = devm_clk_register_regmap(dev, mmcc_msm8974_clocks[i]);
2583                 if (IS_ERR(clk))
2584                         return PTR_ERR(clk);
2585                 clks[i] = clk;
2586         }
2587
2588         ret = of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, data);
2589         if (ret)
2590                 return ret;
2591
2592         reset = &cc->reset;
2593         reset->rcdev.of_node = dev->of_node;
2594         reset->rcdev.ops = &qcom_reset_ops,
2595         reset->rcdev.owner = THIS_MODULE,
2596         reset->rcdev.nr_resets = ARRAY_SIZE(mmcc_msm8974_resets),
2597         reset->regmap = regmap;
2598         reset->reset_map = mmcc_msm8974_resets,
2599         platform_set_drvdata(pdev, &reset->rcdev);
2600
2601         ret = reset_controller_register(&reset->rcdev);
2602         if (ret)
2603                 of_clk_del_provider(dev->of_node);
2604
2605         return ret;
2606 }
2607
2608 static int mmcc_msm8974_remove(struct platform_device *pdev)
2609 {
2610         of_clk_del_provider(pdev->dev.of_node);
2611         reset_controller_unregister(platform_get_drvdata(pdev));
2612         return 0;
2613 }
2614
2615 static struct platform_driver mmcc_msm8974_driver = {
2616         .probe          = mmcc_msm8974_probe,
2617         .remove         = mmcc_msm8974_remove,
2618         .driver         = {
2619                 .name   = "mmcc-msm8974",
2620                 .owner  = THIS_MODULE,
2621                 .of_match_table = mmcc_msm8974_match_table,
2622         },
2623 };
2624 module_platform_driver(mmcc_msm8974_driver);
2625
2626 MODULE_DESCRIPTION("QCOM MMCC MSM8974 Driver");
2627 MODULE_LICENSE("GPL v2");
2628 MODULE_ALIAS("platform:mmcc-msm8974");