drivers/clk/qcom/mmcc-msm8960.c

   1 /*
   2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/delay.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/clk-provider.h>
  23 #include <linux/regmap.h>
  24 #include <linux/reset-controller.h>
  25
  26 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
  27 #include <dt-bindings/reset/qcom,mmcc-msm8960.h>
  28
  29 #include "common.h"
  30 #include "clk-regmap.h"
  31 #include "clk-pll.h"
  32 #include "clk-rcg.h"
  33 #include "clk-branch.h"
  34 #include "reset.h"
  35
  36 #define P_PXO   0
  37 #define P_PLL8  1
  38 #define P_PLL2  2
  39 #define P_PLL3  3
  40
  41 #define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
  42
  43 static u8 mmcc_pxo_pll8_pll2_map[] = {
  44         [P_PXO]         = 0,
  45         [P_PLL8]        = 2,
  46         [P_PLL2]        = 1,
  47 };
  48
  49 static const char *mmcc_pxo_pll8_pll2[] = {
  50         "pxo",
  51         "pll8_vote",
  52         "pll2",
  53 };
  54
  55 static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
  56         [P_PXO]         = 0,
  57         [P_PLL8]        = 2,
  58         [P_PLL2]        = 1,
  59         [P_PLL3]        = 3,
  60 };
  61
  62 static const char *mmcc_pxo_pll8_pll2_pll3[] = {
  63         "pxo",
  64         "pll8_vote",
  65         "pll2",
  66         "pll3",
  67 };
  68
  69 static struct clk_pll pll2 = {
  70         .l_reg = 0x320,
  71         .m_reg = 0x324,
  72         .n_reg = 0x328,
  73         .config_reg = 0x32c,
  74         .mode_reg = 0x31c,
  75         .status_reg = 0x334,
  76         .status_bit = 16,
  77         .clkr.hw.init = &(struct clk_init_data){
  78                 .name = "pll2",
  79                 .parent_names = (const char *[]){ "pxo" },
  80                 .num_parents = 1,
  81                 .ops = &clk_pll_ops,
  82         },
  83 };
  84
  85 static struct freq_tbl clk_tbl_cam[] = {
  86         {   6000000, P_PLL8, 4, 1, 16 },
  87         {   8000000, P_PLL8, 4, 1, 12 },
  88         {  12000000, P_PLL8, 4, 1,  8 },
  89         {  16000000, P_PLL8, 4, 1,  6 },
  90         {  19200000, P_PLL8, 4, 1,  5 },
  91         {  24000000, P_PLL8, 4, 1,  4 },
  92         {  32000000, P_PLL8, 4, 1,  3 },
  93         {  48000000, P_PLL8, 4, 1,  2 },
  94         {  64000000, P_PLL8, 3, 1,  2 },
  95         {  96000000, P_PLL8, 4, 0,  0 },
  96         { 128000000, P_PLL8, 3, 0,  0 },
  97         { }
  98 };
  99
 100 static struct clk_rcg camclk0_src = {
 101         .ns_reg = 0x0148,
 102         .md_reg = 0x0144,
 103         .mn = {
 104                 .mnctr_en_bit = 5,
 105                 .mnctr_reset_bit = 8,
 106                 .reset_in_cc = true,
 107                 .mnctr_mode_shift = 6,
 108                 .n_val_shift = 24,
 109                 .m_val_shift = 8,
 110                 .width = 8,
 111         },
 112         .p = {
 113                 .pre_div_shift = 14,
 114                 .pre_div_width = 2,
 115         },
 116         .s = {
 117                 .src_sel_shift = 0,
 118                 .parent_map = mmcc_pxo_pll8_pll2_map,
 119         },
 120         .freq_tbl = clk_tbl_cam,
 121         .clkr = {
 122                 .enable_reg = 0x0140,
 123                 .enable_mask = BIT(2),
 124                 .hw.init = &(struct clk_init_data){
 125                         .name = "camclk0_src",
 126                         .parent_names = mmcc_pxo_pll8_pll2,
 127                         .num_parents = 3,
 128                         .ops = &clk_rcg_ops,
 129                 },
 130         },
 131 };
 132
 133 static struct clk_branch camclk0_clk = {
 134         .halt_reg = 0x01e8,
 135         .halt_bit = 15,
 136         .clkr = {
 137                 .enable_reg = 0x0140,
 138                 .enable_mask = BIT(0),
 139                 .hw.init = &(struct clk_init_data){
 140                         .name = "camclk0_clk",
 141                         .parent_names = (const char *[]){ "camclk0_src" },
 142                         .num_parents = 1,
 143                         .ops = &clk_branch_ops,
 144                 },
 145         },
 146
 147 };
 148
 149 static struct clk_rcg camclk1_src = {
 150         .ns_reg = 0x015c,
 151         .md_reg = 0x0158,
 152         .mn = {
 153                 .mnctr_en_bit = 5,
 154                 .mnctr_reset_bit = 8,
 155                 .reset_in_cc = true,
 156                 .mnctr_mode_shift = 6,
 157                 .n_val_shift = 24,
 158                 .m_val_shift = 8,
 159                 .width = 8,
 160         },
 161         .p = {
 162                 .pre_div_shift = 14,
 163                 .pre_div_width = 2,
 164         },
 165         .s = {
 166                 .src_sel_shift = 0,
 167                 .parent_map = mmcc_pxo_pll8_pll2_map,
 168         },
 169         .freq_tbl = clk_tbl_cam,
 170         .clkr = {
 171                 .enable_reg = 0x0154,
 172                 .enable_mask = BIT(2),
 173                 .hw.init = &(struct clk_init_data){
 174                         .name = "camclk1_src",
 175                         .parent_names = mmcc_pxo_pll8_pll2,
 176                         .num_parents = 3,
 177                         .ops = &clk_rcg_ops,
 178                 },
 179         },
 180 };
 181
 182 static struct clk_branch camclk1_clk = {
 183         .halt_reg = 0x01e8,
 184         .halt_bit = 16,
 185         .clkr = {
 186                 .enable_reg = 0x0154,
 187                 .enable_mask = BIT(0),
 188                 .hw.init = &(struct clk_init_data){
 189                         .name = "camclk1_clk",
 190                         .parent_names = (const char *[]){ "camclk1_src" },
 191                         .num_parents = 1,
 192                         .ops = &clk_branch_ops,
 193                 },
 194         },
 195
 196 };
 197
 198 static struct clk_rcg camclk2_src = {
 199         .ns_reg = 0x0228,
 200         .md_reg = 0x0224,
 201         .mn = {
 202                 .mnctr_en_bit = 5,
 203                 .mnctr_reset_bit = 8,
 204                 .reset_in_cc = true,
 205                 .mnctr_mode_shift = 6,
 206                 .n_val_shift = 24,
 207                 .m_val_shift = 8,
 208                 .width = 8,
 209         },
 210         .p = {
 211                 .pre_div_shift = 14,
 212                 .pre_div_width = 2,
 213         },
 214         .s = {
 215                 .src_sel_shift = 0,
 216                 .parent_map = mmcc_pxo_pll8_pll2_map,
 217         },
 218         .freq_tbl = clk_tbl_cam,
 219         .clkr = {
 220                 .enable_reg = 0x0220,
 221                 .enable_mask = BIT(2),
 222                 .hw.init = &(struct clk_init_data){
 223                         .name = "camclk2_src",
 224                         .parent_names = mmcc_pxo_pll8_pll2,
 225                         .num_parents = 3,
 226                         .ops = &clk_rcg_ops,
 227                 },
 228         },
 229 };
 230
 231 static struct clk_branch camclk2_clk = {
 232         .halt_reg = 0x01e8,
 233         .halt_bit = 16,
 234         .clkr = {
 235                 .enable_reg = 0x0220,
 236                 .enable_mask = BIT(0),
 237                 .hw.init = &(struct clk_init_data){
 238                         .name = "camclk2_clk",
 239                         .parent_names = (const char *[]){ "camclk2_src" },
 240                         .num_parents = 1,
 241                         .ops = &clk_branch_ops,
 242                 },
 243         },
 244
 245 };
 246
 247 static struct freq_tbl clk_tbl_csi[] = {
 248         {  27000000, P_PXO,  1, 0, 0 },
 249         {  85330000, P_PLL8, 1, 2, 9 },
 250         { 177780000, P_PLL2, 1, 2, 9 },
 251         { }
 252 };
 253
 254 static struct clk_rcg csi0_src = {
 255         .ns_reg = 0x0048,
 256         .md_reg = 0x0044,
 257         .mn = {
 258                 .mnctr_en_bit = 5,
 259                 .mnctr_reset_bit = 7,
 260                 .mnctr_mode_shift = 6,
 261                 .n_val_shift = 24,
 262                 .m_val_shift = 8,
 263                 .width = 8,
 264         },
 265         .p = {
 266                 .pre_div_shift = 14,
 267                 .pre_div_width = 2,
 268         },
 269         .s = {
 270                 .src_sel_shift = 0,
 271                 .parent_map = mmcc_pxo_pll8_pll2_map,
 272         },
 273         .freq_tbl = clk_tbl_csi,
 274         .clkr = {
 275                 .enable_reg = 0x0040,
 276                 .enable_mask = BIT(2),
 277                 .hw.init = &(struct clk_init_data){
 278                         .name = "csi0_src",
 279                         .parent_names = mmcc_pxo_pll8_pll2,
 280                         .num_parents = 3,
 281                         .ops = &clk_rcg_ops,
 282                 },
 283         },
 284 };
 285
 286 static struct clk_branch csi0_clk = {
 287         .halt_reg = 0x01cc,
 288         .halt_bit = 13,
 289         .clkr = {
 290                 .enable_reg = 0x0040,
 291                 .enable_mask = BIT(0),
 292                 .hw.init = &(struct clk_init_data){
 293                         .parent_names = (const char *[]){ "csi0_src" },
 294                         .num_parents = 1,
 295                         .name = "csi0_clk",
 296                         .ops = &clk_branch_ops,
 297                         .flags = CLK_SET_RATE_PARENT,
 298                 },
 299         },
 300 };
 301
 302 static struct clk_branch csi0_phy_clk = {
 303         .halt_reg = 0x01e8,
 304         .halt_bit = 9,
 305         .clkr = {
 306                 .enable_reg = 0x0040,
 307                 .enable_mask = BIT(8),
 308                 .hw.init = &(struct clk_init_data){
 309                         .parent_names = (const char *[]){ "csi0_src" },
 310                         .num_parents = 1,
 311                         .name = "csi0_phy_clk",
 312                         .ops = &clk_branch_ops,
 313                         .flags = CLK_SET_RATE_PARENT,
 314                 },
 315         },
 316 };
 317
 318 static struct clk_rcg csi1_src = {
 319         .ns_reg = 0x0010,
 320         .md_reg = 0x0028,
 321         .mn = {
 322                 .mnctr_en_bit = 5,
 323                 .mnctr_reset_bit = 7,
 324                 .mnctr_mode_shift = 6,
 325                 .n_val_shift = 24,
 326                 .m_val_shift = 8,
 327                 .width = 8,
 328         },
 329         .p = {
 330                 .pre_div_shift = 14,
 331                 .pre_div_width = 2,
 332         },
 333         .s = {
 334                 .src_sel_shift = 0,
 335                 .parent_map = mmcc_pxo_pll8_pll2_map,
 336         },
 337         .freq_tbl = clk_tbl_csi,
 338         .clkr = {
 339                 .enable_reg = 0x0024,
 340                 .enable_mask = BIT(2),
 341                 .hw.init = &(struct clk_init_data){
 342                         .name = "csi1_src",
 343                         .parent_names = mmcc_pxo_pll8_pll2,
 344                         .num_parents = 3,
 345                         .ops = &clk_rcg_ops,
 346                 },
 347         },
 348 };
 349
 350 static struct clk_branch csi1_clk = {
 351         .halt_reg = 0x01cc,
 352         .halt_bit = 14,
 353         .clkr = {
 354                 .enable_reg = 0x0024,
 355                 .enable_mask = BIT(0),
 356                 .hw.init = &(struct clk_init_data){
 357                         .parent_names = (const char *[]){ "csi1_src" },
 358                         .num_parents = 1,
 359                         .name = "csi1_clk",
 360                         .ops = &clk_branch_ops,
 361                         .flags = CLK_SET_RATE_PARENT,
 362                 },
 363         },
 364 };
 365
 366 static struct clk_branch csi1_phy_clk = {
 367         .halt_reg = 0x01e8,
 368         .halt_bit = 10,
 369         .clkr = {
 370                 .enable_reg = 0x0024,
 371                 .enable_mask = BIT(8),
 372                 .hw.init = &(struct clk_init_data){
 373                         .parent_names = (const char *[]){ "csi1_src" },
 374                         .num_parents = 1,
 375                         .name = "csi1_phy_clk",
 376                         .ops = &clk_branch_ops,
 377                         .flags = CLK_SET_RATE_PARENT,
 378                 },
 379         },
 380 };
 381
 382 static struct clk_rcg csi2_src = {
 383         .ns_reg = 0x0234,
 384         .md_reg = 0x022c,
 385         .mn = {
 386                 .mnctr_en_bit = 5,
 387                 .mnctr_reset_bit = 7,
 388                 .mnctr_mode_shift = 6,
 389                 .n_val_shift = 24,
 390                 .m_val_shift = 8,
 391                 .width = 8,
 392         },
 393         .p = {
 394                 .pre_div_shift = 14,
 395                 .pre_div_width = 2,
 396         },
 397         .s = {
 398                 .src_sel_shift = 0,
 399                 .parent_map = mmcc_pxo_pll8_pll2_map,
 400         },
 401         .freq_tbl = clk_tbl_csi,
 402         .clkr = {
 403                 .enable_reg = 0x022c,
 404                 .enable_mask = BIT(2),
 405                 .hw.init = &(struct clk_init_data){
 406                         .name = "csi2_src",
 407                         .parent_names = mmcc_pxo_pll8_pll2,
 408                         .num_parents = 3,
 409                         .ops = &clk_rcg_ops,
 410                 },
 411         },
 412 };
 413
 414 static struct clk_branch csi2_clk = {
 415         .halt_reg = 0x01cc,
 416         .halt_bit = 29,
 417         .clkr = {
 418                 .enable_reg = 0x022c,
 419                 .enable_mask = BIT(0),
 420                 .hw.init = &(struct clk_init_data){
 421                         .parent_names = (const char *[]){ "csi2_src" },
 422                         .num_parents = 1,
 423                         .name = "csi2_clk",
 424                         .ops = &clk_branch_ops,
 425                         .flags = CLK_SET_RATE_PARENT,
 426                 },
 427         },
 428 };
 429
 430 static struct clk_branch csi2_phy_clk = {
 431         .halt_reg = 0x01e8,
 432         .halt_bit = 29,
 433         .clkr = {
 434                 .enable_reg = 0x022c,
 435                 .enable_mask = BIT(8),
 436                 .hw.init = &(struct clk_init_data){
 437                         .parent_names = (const char *[]){ "csi2_src" },
 438                         .num_parents = 1,
 439                         .name = "csi2_phy_clk",
 440                         .ops = &clk_branch_ops,
 441                         .flags = CLK_SET_RATE_PARENT,
 442                 },
 443         },
 444 };
 445
 446 struct clk_pix_rdi {
 447         u32 s_reg;
 448         u32 s_mask;
 449         u32 s2_reg;
 450         u32 s2_mask;
 451         struct clk_regmap clkr;
 452 };
 453
 454 #define to_clk_pix_rdi(_hw) \
 455         container_of(to_clk_regmap(_hw), struct clk_pix_rdi, clkr)
 456
 457 static int pix_rdi_set_parent(struct clk_hw *hw, u8 index)
 458 {
 459         int i;
 460         int ret = 0;
 461         u32 val;
 462         struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
 463         struct clk *clk = hw->clk;
 464         int num_parents = __clk_get_num_parents(hw->clk);
 465
 466         /*
 467          * These clocks select three inputs via two muxes. One mux selects
 468          * between csi0 and csi1 and the second mux selects between that mux's
 469          * output and csi2. The source and destination selections for each
 470          * mux must be clocking for the switch to succeed so just turn on
 471          * all three sources because it's easier than figuring out what source
 472          * needs to be on at what time.
 473          */
 474         for (i = 0; i < num_parents; i++) {
 475                 ret = clk_prepare_enable(clk_get_parent_by_index(clk, i));
 476                 if (ret)
 477                         goto err;
 478         }
 479
 480         if (index == 2)
 481                 val = rdi->s2_mask;
 482         else
 483                 val = 0;
 484         regmap_update_bits(rdi->clkr.regmap, rdi->s2_reg, rdi->s2_mask, val);
 485         /*
 486          * Wait at least 6 cycles of slowest clock
 487          * for the glitch-free MUX to fully switch sources.
 488          */
 489         udelay(1);
 490
 491         if (index == 1)
 492                 val = rdi->s_mask;
 493         else
 494                 val = 0;
 495         regmap_update_bits(rdi->clkr.regmap, rdi->s_reg, rdi->s_mask, val);
 496         /*
 497          * Wait at least 6 cycles of slowest clock
 498          * for the glitch-free MUX to fully switch sources.
 499          */
 500         udelay(1);
 501
 502 err:
 503         for (i--; i >= 0; i--)
 504                 clk_disable_unprepare(clk_get_parent_by_index(clk, i));
 505
 506         return ret;
 507 }
 508
 509 static u8 pix_rdi_get_parent(struct clk_hw *hw)
 510 {
 511         u32 val;
 512         struct clk_pix_rdi *rdi = to_clk_pix_rdi(hw);
 513
 514
 515         regmap_read(rdi->clkr.regmap, rdi->s2_reg, &val);
 516         if (val & rdi->s2_mask)
 517                 return 2;
 518
 519         regmap_read(rdi->clkr.regmap, rdi->s_reg, &val);
 520         if (val & rdi->s_mask)
 521                 return 1;
 522
 523         return 0;
 524 }
 525
 526 static const struct clk_ops clk_ops_pix_rdi = {
 527         .enable = clk_enable_regmap,
 528         .disable = clk_disable_regmap,
 529         .set_parent = pix_rdi_set_parent,
 530         .get_parent = pix_rdi_get_parent,
 531         .determine_rate = __clk_mux_determine_rate,
 532 };
 533
 534 static const char *pix_rdi_parents[] = {
 535         "csi0_clk",
 536         "csi1_clk",
 537         "csi2_clk",
 538 };
 539
 540 static struct clk_pix_rdi csi_pix_clk = {
 541         .s_reg = 0x0058,
 542         .s_mask = BIT(25),
 543         .s2_reg = 0x0238,
 544         .s2_mask = BIT(13),
 545         .clkr = {
 546                 .enable_reg = 0x0058,
 547                 .enable_mask = BIT(26),
 548                 .hw.init = &(struct clk_init_data){
 549                         .name = "csi_pix_clk",
 550                         .parent_names = pix_rdi_parents,
 551                         .num_parents = 3,
 552                         .ops = &clk_ops_pix_rdi,
 553                 },
 554         },
 555 };
 556
 557 static struct clk_pix_rdi csi_pix1_clk = {
 558         .s_reg = 0x0238,
 559         .s_mask = BIT(8),
 560         .s2_reg = 0x0238,
 561         .s2_mask = BIT(9),
 562         .clkr = {
 563                 .enable_reg = 0x0238,
 564                 .enable_mask = BIT(10),
 565                 .hw.init = &(struct clk_init_data){
 566                         .name = "csi_pix1_clk",
 567                         .parent_names = pix_rdi_parents,
 568                         .num_parents = 3,
 569                         .ops = &clk_ops_pix_rdi,
 570                 },
 571         },
 572 };
 573
 574 static struct clk_pix_rdi csi_rdi_clk = {
 575         .s_reg = 0x0058,
 576         .s_mask = BIT(12),
 577         .s2_reg = 0x0238,
 578         .s2_mask = BIT(12),
 579         .clkr = {
 580                 .enable_reg = 0x0058,
 581                 .enable_mask = BIT(13),
 582                 .hw.init = &(struct clk_init_data){
 583                         .name = "csi_rdi_clk",
 584                         .parent_names = pix_rdi_parents,
 585                         .num_parents = 3,
 586                         .ops = &clk_ops_pix_rdi,
 587                 },
 588         },
 589 };
 590
 591 static struct clk_pix_rdi csi_rdi1_clk = {
 592         .s_reg = 0x0238,
 593         .s_mask = BIT(0),
 594         .s2_reg = 0x0238,
 595         .s2_mask = BIT(1),
 596         .clkr = {
 597                 .enable_reg = 0x0238,
 598                 .enable_mask = BIT(2),
 599                 .hw.init = &(struct clk_init_data){
 600                         .name = "csi_rdi1_clk",
 601                         .parent_names = pix_rdi_parents,
 602                         .num_parents = 3,
 603                         .ops = &clk_ops_pix_rdi,
 604                 },
 605         },
 606 };
 607
 608 static struct clk_pix_rdi csi_rdi2_clk = {
 609         .s_reg = 0x0238,
 610         .s_mask = BIT(4),
 611         .s2_reg = 0x0238,
 612         .s2_mask = BIT(5),
 613         .clkr = {
 614                 .enable_reg = 0x0238,
 615                 .enable_mask = BIT(6),
 616                 .hw.init = &(struct clk_init_data){
 617                         .name = "csi_rdi2_clk",
 618                         .parent_names = pix_rdi_parents,
 619                         .num_parents = 3,
 620                         .ops = &clk_ops_pix_rdi,
 621                 },
 622         },
 623 };
 624
 625 static struct freq_tbl clk_tbl_csiphytimer[] = {
 626         {  85330000, P_PLL8, 1, 2, 9 },
 627         { 177780000, P_PLL2, 1, 2, 9 },
 628         { }
 629 };
 630
 631 static struct clk_rcg csiphytimer_src = {
 632         .ns_reg = 0x0168,
 633         .md_reg = 0x0164,
 634         .mn = {
 635                 .mnctr_en_bit = 5,
 636                 .mnctr_reset_bit = 8,
 637                 .reset_in_cc = true,
 638                 .mnctr_mode_shift = 6,
 639                 .n_val_shift = 24,
 640                 .m_val_shift = 8,
 641                 .width = 8,
 642         },
 643         .p = {
 644                 .pre_div_shift = 14,
 645                 .pre_div_width = 2,
 646         },
 647         .s = {
 648                 .src_sel_shift = 0,
 649                 .parent_map = mmcc_pxo_pll8_pll2_map,
 650         },
 651         .freq_tbl = clk_tbl_csiphytimer,
 652         .clkr = {
 653                 .enable_reg = 0x0160,
 654                 .enable_mask = BIT(2),
 655                 .hw.init = &(struct clk_init_data){
 656                         .name = "csiphytimer_src",
 657                         .parent_names = mmcc_pxo_pll8_pll2,
 658                         .num_parents = 3,
 659                         .ops = &clk_rcg_ops,
 660                 },
 661         },
 662 };
 663
 664 static const char *csixphy_timer_src[] = { "csiphytimer_src" };
 665
 666 static struct clk_branch csiphy0_timer_clk = {
 667         .halt_reg = 0x01e8,
 668         .halt_bit = 17,
 669         .clkr = {
 670                 .enable_reg = 0x0160,
 671                 .enable_mask = BIT(0),
 672                 .hw.init = &(struct clk_init_data){
 673                         .parent_names = csixphy_timer_src,
 674                         .num_parents = 1,
 675                         .name = "csiphy0_timer_clk",
 676                         .ops = &clk_branch_ops,
 677                         .flags = CLK_SET_RATE_PARENT,
 678                 },
 679         },
 680 };
 681
 682 static struct clk_branch csiphy1_timer_clk = {
 683         .halt_reg = 0x01e8,
 684         .halt_bit = 18,
 685         .clkr = {
 686                 .enable_reg = 0x0160,
 687                 .enable_mask = BIT(9),
 688                 .hw.init = &(struct clk_init_data){
 689                         .parent_names = csixphy_timer_src,
 690                         .num_parents = 1,
 691                         .name = "csiphy1_timer_clk",
 692                         .ops = &clk_branch_ops,
 693                         .flags = CLK_SET_RATE_PARENT,
 694                 },
 695         },
 696 };
 697
 698 static struct clk_branch csiphy2_timer_clk = {
 699         .halt_reg = 0x01e8,
 700         .halt_bit = 30,
 701         .clkr = {
 702                 .enable_reg = 0x0160,
 703                 .enable_mask = BIT(11),
 704                 .hw.init = &(struct clk_init_data){
 705                         .parent_names = csixphy_timer_src,
 706                         .num_parents = 1,
 707                         .name = "csiphy2_timer_clk",
 708                         .ops = &clk_branch_ops,
 709                         .flags = CLK_SET_RATE_PARENT,
 710                 },
 711         },
 712 };
 713
 714 static struct freq_tbl clk_tbl_gfx2d[] = {
 715         F_MN( 27000000, P_PXO,  1,  0),
 716         F_MN( 48000000, P_PLL8, 1,  8),
 717         F_MN( 54857000, P_PLL8, 1,  7),
 718         F_MN( 64000000, P_PLL8, 1,  6),
 719         F_MN( 76800000, P_PLL8, 1,  5),
 720         F_MN( 96000000, P_PLL8, 1,  4),
 721         F_MN(128000000, P_PLL8, 1,  3),
 722         F_MN(145455000, P_PLL2, 2, 11),
 723         F_MN(160000000, P_PLL2, 1,  5),
 724         F_MN(177778000, P_PLL2, 2,  9),
 725         F_MN(200000000, P_PLL2, 1,  4),
 726         F_MN(228571000, P_PLL2, 2,  7),
 727         { }
 728 };
 729
 730 static struct clk_dyn_rcg gfx2d0_src = {
 731         .ns_reg = 0x0070,
 732         .md_reg[0] = 0x0064,
 733         .md_reg[1] = 0x0068,
 734         .mn[0] = {
 735                 .mnctr_en_bit = 8,
 736                 .mnctr_reset_bit = 25,
 737                 .mnctr_mode_shift = 9,
 738                 .n_val_shift = 20,
 739                 .m_val_shift = 4,
 740                 .width = 4,
 741         },
 742         .mn[1] = {
 743                 .mnctr_en_bit = 5,
 744                 .mnctr_reset_bit = 24,
 745                 .mnctr_mode_shift = 6,
 746                 .n_val_shift = 16,
 747                 .m_val_shift = 4,
 748                 .width = 4,
 749         },
 750         .s[0] = {
 751                 .src_sel_shift = 3,
 752                 .parent_map = mmcc_pxo_pll8_pll2_map,
 753         },
 754         .s[1] = {
 755                 .src_sel_shift = 0,
 756                 .parent_map = mmcc_pxo_pll8_pll2_map,
 757         },
 758         .mux_sel_bit = 11,
 759         .freq_tbl = clk_tbl_gfx2d,
 760         .clkr = {
 761                 .enable_reg = 0x0060,
 762                 .enable_mask = BIT(2),
 763                 .hw.init = &(struct clk_init_data){
 764                         .name = "gfx2d0_src",
 765                         .parent_names = mmcc_pxo_pll8_pll2,
 766                         .num_parents = 3,
 767                         .ops = &clk_dyn_rcg_ops,
 768                 },
 769         },
 770 };
 771
 772 static struct clk_branch gfx2d0_clk = {
 773         .halt_reg = 0x01c8,
 774         .halt_bit = 9,
 775         .clkr = {
 776                 .enable_reg = 0x0060,
 777                 .enable_mask = BIT(0),
 778                 .hw.init = &(struct clk_init_data){
 779                         .name = "gfx2d0_clk",
 780                         .parent_names = (const char *[]){ "gfx2d0_src" },
 781                         .num_parents = 1,
 782                         .ops = &clk_branch_ops,
 783                         .flags = CLK_SET_RATE_PARENT,
 784                 },
 785         },
 786 };
 787
 788 static struct clk_dyn_rcg gfx2d1_src = {
 789         .ns_reg = 0x007c,
 790         .md_reg[0] = 0x0078,
 791         .md_reg[1] = 0x006c,
 792         .mn[0] = {
 793                 .mnctr_en_bit = 8,
 794                 .mnctr_reset_bit = 25,
 795                 .mnctr_mode_shift = 9,
 796                 .n_val_shift = 20,
 797                 .m_val_shift = 4,
 798                 .width = 4,
 799         },
 800         .mn[1] = {
 801                 .mnctr_en_bit = 5,
 802                 .mnctr_reset_bit = 24,
 803                 .mnctr_mode_shift = 6,
 804                 .n_val_shift = 16,
 805                 .m_val_shift = 4,
 806                 .width = 4,
 807         },
 808         .s[0] = {
 809                 .src_sel_shift = 3,
 810                 .parent_map = mmcc_pxo_pll8_pll2_map,
 811         },
 812         .s[1] = {
 813                 .src_sel_shift = 0,
 814                 .parent_map = mmcc_pxo_pll8_pll2_map,
 815         },
 816         .mux_sel_bit = 11,
 817         .freq_tbl = clk_tbl_gfx2d,
 818         .clkr = {
 819                 .enable_reg = 0x0074,
 820                 .enable_mask = BIT(2),
 821                 .hw.init = &(struct clk_init_data){
 822                         .name = "gfx2d1_src",
 823                         .parent_names = mmcc_pxo_pll8_pll2,
 824                         .num_parents = 3,
 825                         .ops = &clk_dyn_rcg_ops,
 826                 },
 827         },
 828 };
 829
 830 static struct clk_branch gfx2d1_clk = {
 831         .halt_reg = 0x01c8,
 832         .halt_bit = 14,
 833         .clkr = {
 834                 .enable_reg = 0x0074,
 835                 .enable_mask = BIT(0),
 836                 .hw.init = &(struct clk_init_data){
 837                         .name = "gfx2d1_clk",
 838                         .parent_names = (const char *[]){ "gfx2d1_src" },
 839                         .num_parents = 1,
 840                         .ops = &clk_branch_ops,
 841                         .flags = CLK_SET_RATE_PARENT,
 842                 },
 843         },
 844 };
 845
 846 static struct freq_tbl clk_tbl_gfx3d[] = {
 847         F_MN( 27000000, P_PXO,  1,  0),
 848         F_MN( 48000000, P_PLL8, 1,  8),
 849         F_MN( 54857000, P_PLL8, 1,  7),
 850         F_MN( 64000000, P_PLL8, 1,  6),
 851         F_MN( 76800000, P_PLL8, 1,  5),
 852         F_MN( 96000000, P_PLL8, 1,  4),
 853         F_MN(128000000, P_PLL8, 1,  3),
 854         F_MN(145455000, P_PLL2, 2, 11),
 855         F_MN(160000000, P_PLL2, 1,  5),
 856         F_MN(177778000, P_PLL2, 2,  9),
 857         F_MN(200000000, P_PLL2, 1,  4),
 858         F_MN(228571000, P_PLL2, 2,  7),
 859         F_MN(266667000, P_PLL2, 1,  3),
 860         F_MN(300000000, P_PLL3, 1,  4),
 861         F_MN(320000000, P_PLL2, 2,  5),
 862         F_MN(400000000, P_PLL2, 1,  2),
 863         { }
 864 };
 865
 866 static struct clk_dyn_rcg gfx3d_src = {
 867         .ns_reg = 0x008c,
 868         .md_reg[0] = 0x0084,
 869         .md_reg[1] = 0x0088,
 870         .mn[0] = {
 871                 .mnctr_en_bit = 8,
 872                 .mnctr_reset_bit = 25,
 873                 .mnctr_mode_shift = 9,
 874                 .n_val_shift = 18,
 875                 .m_val_shift = 4,
 876                 .width = 4,
 877         },
 878         .mn[1] = {
 879                 .mnctr_en_bit = 5,
 880                 .mnctr_reset_bit = 24,
 881                 .mnctr_mode_shift = 6,
 882                 .n_val_shift = 14,
 883                 .m_val_shift = 4,
 884                 .width = 4,
 885         },
 886         .s[0] = {
 887                 .src_sel_shift = 3,
 888                 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
 889         },
 890         .s[1] = {
 891                 .src_sel_shift = 0,
 892                 .parent_map = mmcc_pxo_pll8_pll2_pll3_map,
 893         },
 894         .mux_sel_bit = 11,
 895         .freq_tbl = clk_tbl_gfx3d,
 896         .clkr = {
 897                 .enable_reg = 0x0080,
 898                 .enable_mask = BIT(2),
 899                 .hw.init = &(struct clk_init_data){
 900                         .name = "gfx3d_src",
 901                         .parent_names = mmcc_pxo_pll8_pll2_pll3,
 902                         .num_parents = 4,
 903                         .ops = &clk_dyn_rcg_ops,
 904                 },
 905         },
 906 };
 907
 908 static struct clk_branch gfx3d_clk = {
 909         .halt_reg = 0x01c8,
 910         .halt_bit = 4,
 911         .clkr = {
 912                 .enable_reg = 0x0080,
 913                 .enable_mask = BIT(0),
 914                 .hw.init = &(struct clk_init_data){
 915                         .name = "gfx3d_clk",
 916                         .parent_names = (const char *[]){ "gfx3d_src" },
 917                         .num_parents = 1,
 918                         .ops = &clk_branch_ops,
 919                         .flags = CLK_SET_RATE_PARENT,
 920                 },
 921         },
 922 };
 923
 924 static struct freq_tbl clk_tbl_ijpeg[] = {
 925         {  27000000, P_PXO,  1, 0,  0 },
 926         {  36570000, P_PLL8, 1, 2, 21 },
 927         {  54860000, P_PLL8, 7, 0,  0 },
 928         {  96000000, P_PLL8, 4, 0,  0 },
 929         { 109710000, P_PLL8, 1, 2,  7 },
 930         { 128000000, P_PLL8, 3, 0,  0 },
 931         { 153600000, P_PLL8, 1, 2,  5 },
 932         { 200000000, P_PLL2, 4, 0,  0 },
 933         { 228571000, P_PLL2, 1, 2,  7 },
 934         { 266667000, P_PLL2, 1, 1,  3 },
 935         { 320000000, P_PLL2, 1, 2,  5 },
 936         { }
 937 };
 938
 939 static struct clk_rcg ijpeg_src = {
 940         .ns_reg = 0x00a0,
 941         .md_reg = 0x009c,
 942         .mn = {
 943                 .mnctr_en_bit = 5,
 944                 .mnctr_reset_bit = 7,
 945                 .mnctr_mode_shift = 6,
 946                 .n_val_shift = 16,
 947                 .m_val_shift = 8,
 948                 .width = 8,
 949         },
 950         .p = {
 951                 .pre_div_shift = 12,
 952                 .pre_div_width = 2,
 953         },
 954         .s = {
 955                 .src_sel_shift = 0,
 956                 .parent_map = mmcc_pxo_pll8_pll2_map,
 957         },
 958         .freq_tbl = clk_tbl_ijpeg,
 959         .clkr = {
 960                 .enable_reg = 0x0098,
 961                 .enable_mask = BIT(2),
 962                 .hw.init = &(struct clk_init_data){
 963                         .name = "ijpeg_src",
 964                         .parent_names = mmcc_pxo_pll8_pll2,
 965                         .num_parents = 3,
 966                         .ops = &clk_rcg_ops,
 967                 },
 968         },
 969 };
 970
 971 static struct clk_branch ijpeg_clk = {
 972         .halt_reg = 0x01c8,
 973         .halt_bit = 24,
 974         .clkr = {
 975                 .enable_reg = 0x0098,
 976                 .enable_mask = BIT(0),
 977                 .hw.init = &(struct clk_init_data){
 978                         .name = "ijpeg_clk",
 979                         .parent_names = (const char *[]){ "ijpeg_src" },
 980                         .num_parents = 1,
 981                         .ops = &clk_branch_ops,
 982                         .flags = CLK_SET_RATE_PARENT,
 983                 },
 984         },
 985 };
 986
 987 static struct freq_tbl clk_tbl_jpegd[] = {
 988         {  64000000, P_PLL8, 6 },
 989         {  76800000, P_PLL8, 5 },
 990         {  96000000, P_PLL8, 4 },
 991         { 160000000, P_PLL2, 5 },
 992         { 200000000, P_PLL2, 4 },
 993         { }
 994 };
 995
 996 static struct clk_rcg jpegd_src = {
 997         .ns_reg = 0x00ac,
 998         .p = {
 999                 .pre_div_shift = 12,
1000                 .pre_div_width = 4,
1001         },
1002         .s = {
1003                 .src_sel_shift = 0,
1004                 .parent_map = mmcc_pxo_pll8_pll2_map,
1005         },
1006         .freq_tbl = clk_tbl_jpegd,
1007         .clkr = {
1008                 .enable_reg = 0x00a4,
1009                 .enable_mask = BIT(2),
1010                 .hw.init = &(struct clk_init_data){
1011                         .name = "jpegd_src",
1012                         .parent_names = mmcc_pxo_pll8_pll2,
1013                         .num_parents = 3,
1014                         .ops = &clk_rcg_ops,
1015                 },
1016         },
1017 };
1018
1019 static struct clk_branch jpegd_clk = {
1020         .halt_reg = 0x01c8,
1021         .halt_bit = 19,
1022         .clkr = {
1023                 .enable_reg = 0x00a4,
1024                 .enable_mask = BIT(0),
1025                 .hw.init = &(struct clk_init_data){
1026                         .name = "jpegd_clk",
1027                         .parent_names = (const char *[]){ "jpegd_src" },
1028                         .num_parents = 1,
1029                         .ops = &clk_branch_ops,
1030                         .flags = CLK_SET_RATE_PARENT,
1031                 },
1032         },
1033 };
1034
1035 static struct freq_tbl clk_tbl_mdp[] = {
1036         {   9600000, P_PLL8, 1, 1, 40 },
1037         {  13710000, P_PLL8, 1, 1, 28 },
1038         {  27000000, P_PXO,  1, 0,  0 },
1039         {  29540000, P_PLL8, 1, 1, 13 },
1040         {  34910000, P_PLL8, 1, 1, 11 },
1041         {  38400000, P_PLL8, 1, 1, 10 },
1042         {  59080000, P_PLL8, 1, 2, 13 },
1043         {  76800000, P_PLL8, 1, 1,  5 },
1044         {  85330000, P_PLL8, 1, 2,  9 },
1045         {  96000000, P_PLL8, 1, 1,  4 },
1046         { 128000000, P_PLL8, 1, 1,  3 },
1047         { 160000000, P_PLL2, 1, 1,  5 },
1048         { 177780000, P_PLL2, 1, 2,  9 },
1049         { 200000000, P_PLL2, 1, 1,  4 },
1050         { 228571000, P_PLL2, 1, 2,  7 },
1051         { 266667000, P_PLL2, 1, 1,  3 },
1052         { }
1053 };
1054
1055 static struct clk_dyn_rcg mdp_src = {
1056         .ns_reg = 0x00d0,
1057         .md_reg[0] = 0x00c4,
1058         .md_reg[1] = 0x00c8,
1059         .mn[0] = {
1060                 .mnctr_en_bit = 8,
1061                 .mnctr_reset_bit = 31,
1062                 .mnctr_mode_shift = 9,
1063                 .n_val_shift = 22,
1064                 .m_val_shift = 8,
1065                 .width = 8,
1066         },
1067         .mn[1] = {
1068                 .mnctr_en_bit = 5,
1069                 .mnctr_reset_bit = 30,
1070                 .mnctr_mode_shift = 6,
1071                 .n_val_shift = 14,
1072                 .m_val_shift = 8,
1073                 .width = 8,
1074         },
1075         .s[0] = {
1076                 .src_sel_shift = 3,
1077                 .parent_map = mmcc_pxo_pll8_pll2_map,
1078         },
1079         .s[1] = {
1080                 .src_sel_shift = 0,
1081                 .parent_map = mmcc_pxo_pll8_pll2_map,
1082         },
1083         .mux_sel_bit = 11,
1084         .freq_tbl = clk_tbl_mdp,
1085         .clkr = {
1086                 .enable_reg = 0x00c0,
1087                 .enable_mask = BIT(2),
1088                 .hw.init = &(struct clk_init_data){
1089                         .name = "mdp_src",
1090                         .parent_names = mmcc_pxo_pll8_pll2,
1091                         .num_parents = 3,
1092                         .ops = &clk_dyn_rcg_ops,
1093                 },
1094         },
1095 };
1096
1097 static struct clk_branch mdp_clk = {
1098         .halt_reg = 0x01d0,
1099         .halt_bit = 10,
1100         .clkr = {
1101                 .enable_reg = 0x00c0,
1102                 .enable_mask = BIT(0),
1103                 .hw.init = &(struct clk_init_data){
1104                         .name = "mdp_clk",
1105                         .parent_names = (const char *[]){ "mdp_src" },
1106                         .num_parents = 1,
1107                         .ops = &clk_branch_ops,
1108                         .flags = CLK_SET_RATE_PARENT,
1109                 },
1110         },
1111 };
1112
1113 static struct clk_branch mdp_lut_clk = {
1114         .halt_reg = 0x01e8,
1115         .halt_bit = 13,
1116         .clkr = {
1117                 .enable_reg = 0x016c,
1118                 .enable_mask = BIT(0),
1119                 .hw.init = &(struct clk_init_data){
1120                         .parent_names = (const char *[]){ "mdp_src" },
1121                         .num_parents = 1,
1122                         .name = "mdp_lut_clk",
1123                         .ops = &clk_branch_ops,
1124                         .flags = CLK_SET_RATE_PARENT,
1125                 },
1126         },
1127 };
1128
1129 static struct clk_branch mdp_vsync_clk = {
1130         .halt_reg = 0x01cc,
1131         .halt_bit = 22,
1132         .clkr = {
1133                 .enable_reg = 0x0058,
1134                 .enable_mask = BIT(6),
1135                 .hw.init = &(struct clk_init_data){
1136                         .name = "mdp_vsync_clk",
1137                         .parent_names = (const char *[]){ "pxo" },
1138                         .num_parents = 1,
1139                         .ops = &clk_branch_ops
1140                 },
1141         },
1142 };
1143
1144 static struct freq_tbl clk_tbl_rot[] = {
1145         {  27000000, P_PXO,   1 },
1146         {  29540000, P_PLL8, 13 },
1147         {  32000000, P_PLL8, 12 },
1148         {  38400000, P_PLL8, 10 },
1149         {  48000000, P_PLL8,  8 },
1150         {  54860000, P_PLL8,  7 },
1151         {  64000000, P_PLL8,  6 },
1152         {  76800000, P_PLL8,  5 },
1153         {  96000000, P_PLL8,  4 },
1154         { 100000000, P_PLL2,  8 },
1155         { 114290000, P_PLL2,  7 },
1156         { 133330000, P_PLL2,  6 },
1157         { 160000000, P_PLL2,  5 },
1158         { 200000000, P_PLL2,  4 },
1159         { }
1160 };
1161
1162 static struct clk_dyn_rcg rot_src = {
1163         .ns_reg = 0x00e8,
1164         .p[0] = {
1165                 .pre_div_shift = 22,
1166                 .pre_div_width = 4,
1167         },
1168         .p[1] = {
1169                 .pre_div_shift = 26,
1170                 .pre_div_width = 4,
1171         },
1172         .s[0] = {
1173                 .src_sel_shift = 16,
1174                 .parent_map = mmcc_pxo_pll8_pll2_map,
1175         },
1176         .s[1] = {
1177                 .src_sel_shift = 19,
1178                 .parent_map = mmcc_pxo_pll8_pll2_map,
1179         },
1180         .mux_sel_bit = 30,
1181         .freq_tbl = clk_tbl_rot,
1182         .clkr = {
1183                 .enable_reg = 0x00e0,
1184                 .enable_mask = BIT(2),
1185                 .hw.init = &(struct clk_init_data){
1186                         .name = "rot_src",
1187                         .parent_names = mmcc_pxo_pll8_pll2,
1188                         .num_parents = 3,
1189                         .ops = &clk_dyn_rcg_ops,
1190                 },
1191         },
1192 };
1193
1194 static struct clk_branch rot_clk = {
1195         .halt_reg = 0x01d0,
1196         .halt_bit = 15,
1197         .clkr = {
1198                 .enable_reg = 0x00e0,
1199                 .enable_mask = BIT(0),
1200                 .hw.init = &(struct clk_init_data){
1201                         .name = "rot_clk",
1202                         .parent_names = (const char *[]){ "rot_src" },
1203                         .num_parents = 1,
1204                         .ops = &clk_branch_ops,
1205                         .flags = CLK_SET_RATE_PARENT,
1206                 },
1207         },
1208 };
1209
1210 #define P_HDMI_PLL 1
1211
1212 static u8 mmcc_pxo_hdmi_map[] = {
1213         [P_PXO]         = 0,
1214         [P_HDMI_PLL]    = 3,
1215 };
1216
1217 static const char *mmcc_pxo_hdmi[] = {
1218         "pxo",
1219         "hdmi_pll",
1220 };
1221
1222 static struct freq_tbl clk_tbl_tv[] = {
1223         {  25200000, P_HDMI_PLL, 1, 0, 0 },
1224         {  27000000, P_HDMI_PLL, 1, 0, 0 },
1225         {  27030000, P_HDMI_PLL, 1, 0, 0 },
1226         {  74250000, P_HDMI_PLL, 1, 0, 0 },
1227         { 108000000, P_HDMI_PLL, 1, 0, 0 },
1228         { 148500000, P_HDMI_PLL, 1, 0, 0 },
1229         { }
1230 };
1231
1232 static struct clk_rcg tv_src = {
1233         .ns_reg = 0x00f4,
1234         .md_reg = 0x00f0,
1235         .mn = {
1236                 .mnctr_en_bit = 5,
1237                 .mnctr_reset_bit = 7,
1238                 .mnctr_mode_shift = 6,
1239                 .n_val_shift = 16,
1240                 .m_val_shift = 8,
1241                 .width = 8,
1242         },
1243         .p = {
1244                 .pre_div_shift = 14,
1245                 .pre_div_width = 2,
1246         },
1247         .s = {
1248                 .src_sel_shift = 0,
1249                 .parent_map = mmcc_pxo_hdmi_map,
1250         },
1251         .freq_tbl = clk_tbl_tv,
1252         .clkr = {
1253                 .enable_reg = 0x00ec,
1254                 .enable_mask = BIT(2),
1255                 .hw.init = &(struct clk_init_data){
1256                         .name = "tv_src",
1257                         .parent_names = mmcc_pxo_hdmi,
1258                         .num_parents = 2,
1259                         .ops = &clk_rcg_ops,
1260                         .flags = CLK_SET_RATE_PARENT,
1261                 },
1262         },
1263 };
1264
1265 static const char *tv_src_name[] = { "tv_src" };
1266
1267 static struct clk_branch tv_enc_clk = {
1268         .halt_reg = 0x01d4,
1269         .halt_bit = 9,
1270         .clkr = {
1271                 .enable_reg = 0x00ec,
1272                 .enable_mask = BIT(8),
1273                 .hw.init = &(struct clk_init_data){
1274                         .parent_names = tv_src_name,
1275                         .num_parents = 1,
1276                         .name = "tv_enc_clk",
1277                         .ops = &clk_branch_ops,
1278                         .flags = CLK_SET_RATE_PARENT,
1279                 },
1280         },
1281 };
1282
1283 static struct clk_branch tv_dac_clk = {
1284         .halt_reg = 0x01d4,
1285         .halt_bit = 10,
1286         .clkr = {
1287                 .enable_reg = 0x00ec,
1288                 .enable_mask = BIT(10),
1289                 .hw.init = &(struct clk_init_data){
1290                         .parent_names = tv_src_name,
1291                         .num_parents = 1,
1292                         .name = "tv_dac_clk",
1293                         .ops = &clk_branch_ops,
1294                         .flags = CLK_SET_RATE_PARENT,
1295                 },
1296         },
1297 };
1298
1299 static struct clk_branch mdp_tv_clk = {
1300         .halt_reg = 0x01d4,
1301         .halt_bit = 12,
1302         .clkr = {
1303                 .enable_reg = 0x00ec,
1304                 .enable_mask = BIT(0),
1305                 .hw.init = &(struct clk_init_data){
1306                         .parent_names = tv_src_name,
1307                         .num_parents = 1,
1308                         .name = "mdp_tv_clk",
1309                         .ops = &clk_branch_ops,
1310                         .flags = CLK_SET_RATE_PARENT,
1311                 },
1312         },
1313 };
1314
1315 static struct clk_branch hdmi_tv_clk = {
1316         .halt_reg = 0x01d4,
1317         .halt_bit = 11,
1318         .clkr = {
1319                 .enable_reg = 0x00ec,
1320                 .enable_mask = BIT(12),
1321                 .hw.init = &(struct clk_init_data){
1322                         .parent_names = tv_src_name,
1323                         .num_parents = 1,
1324                         .name = "hdmi_tv_clk",
1325                         .ops = &clk_branch_ops,
1326                         .flags = CLK_SET_RATE_PARENT,
1327                 },
1328         },
1329 };
1330
1331 static struct clk_branch hdmi_app_clk = {
1332         .halt_reg = 0x01cc,
1333         .halt_bit = 25,
1334         .clkr = {
1335                 .enable_reg = 0x005c,
1336                 .enable_mask = BIT(11),
1337                 .hw.init = &(struct clk_init_data){
1338                         .parent_names = (const char *[]){ "pxo" },
1339                         .num_parents = 1,
1340                         .name = "hdmi_app_clk",
1341                         .ops = &clk_branch_ops,
1342                 },
1343         },
1344 };
1345
1346 static struct freq_tbl clk_tbl_vcodec[] = {
1347         F_MN( 27000000, P_PXO,  1,  0),
1348         F_MN( 32000000, P_PLL8, 1, 12),
1349         F_MN( 48000000, P_PLL8, 1,  8),
1350         F_MN( 54860000, P_PLL8, 1,  7),
1351         F_MN( 96000000, P_PLL8, 1,  4),
1352         F_MN(133330000, P_PLL2, 1,  6),
1353         F_MN(200000000, P_PLL2, 1,  4),
1354         F_MN(228570000, P_PLL2, 2,  7),
1355         F_MN(266670000, P_PLL2, 1,  3),
1356         { }
1357 };
1358
1359 static struct clk_dyn_rcg vcodec_src = {
1360         .ns_reg = 0x0100,
1361         .md_reg[0] = 0x00fc,
1362         .md_reg[1] = 0x0128,
1363         .mn[0] = {
1364                 .mnctr_en_bit = 5,
1365                 .mnctr_reset_bit = 31,
1366                 .mnctr_mode_shift = 6,
1367                 .n_val_shift = 11,
1368                 .m_val_shift = 8,
1369                 .width = 8,
1370         },
1371         .mn[1] = {
1372                 .mnctr_en_bit = 10,
1373                 .mnctr_reset_bit = 30,
1374                 .mnctr_mode_shift = 11,
1375                 .n_val_shift = 19,
1376                 .m_val_shift = 8,
1377                 .width = 8,
1378         },
1379         .s[0] = {
1380                 .src_sel_shift = 27,
1381                 .parent_map = mmcc_pxo_pll8_pll2_map,
1382         },
1383         .s[1] = {
1384                 .src_sel_shift = 0,
1385                 .parent_map = mmcc_pxo_pll8_pll2_map,
1386         },
1387         .mux_sel_bit = 13,
1388         .freq_tbl = clk_tbl_vcodec,
1389         .clkr = {
1390                 .enable_reg = 0x00f8,
1391                 .enable_mask = BIT(2),
1392                 .hw.init = &(struct clk_init_data){
1393                         .name = "vcodec_src",
1394                         .parent_names = mmcc_pxo_pll8_pll2,
1395                         .num_parents = 3,
1396                         .ops = &clk_dyn_rcg_ops,
1397                 },
1398         },
1399 };
1400
1401 static struct clk_branch vcodec_clk = {
1402         .halt_reg = 0x01d0,
1403         .halt_bit = 29,
1404         .clkr = {
1405                 .enable_reg = 0x00f8,
1406                 .enable_mask = BIT(0),
1407                 .hw.init = &(struct clk_init_data){
1408                         .name = "vcodec_clk",
1409                         .parent_names = (const char *[]){ "vcodec_src" },
1410                         .num_parents = 1,
1411                         .ops = &clk_branch_ops,
1412                         .flags = CLK_SET_RATE_PARENT,
1413                 },
1414         },
1415 };
1416
1417 static struct freq_tbl clk_tbl_vpe[] = {
1418         {  27000000, P_PXO,   1 },
1419         {  34909000, P_PLL8, 11 },
1420         {  38400000, P_PLL8, 10 },
1421         {  64000000, P_PLL8,  6 },
1422         {  76800000, P_PLL8,  5 },
1423         {  96000000, P_PLL8,  4 },
1424         { 100000000, P_PLL2,  8 },
1425         { 160000000, P_PLL2,  5 },
1426         { }
1427 };
1428
1429 static struct clk_rcg vpe_src = {
1430         .ns_reg = 0x0118,
1431         .p = {
1432                 .pre_div_shift = 12,
1433                 .pre_div_width = 4,
1434         },
1435         .s = {
1436                 .src_sel_shift = 0,
1437                 .parent_map = mmcc_pxo_pll8_pll2_map,
1438         },
1439         .freq_tbl = clk_tbl_vpe,
1440         .clkr = {
1441                 .enable_reg = 0x0110,
1442                 .enable_mask = BIT(2),
1443                 .hw.init = &(struct clk_init_data){
1444                         .name = "vpe_src",
1445                         .parent_names = mmcc_pxo_pll8_pll2,
1446                         .num_parents = 3,
1447                         .ops = &clk_rcg_ops,
1448                 },
1449         },
1450 };
1451
1452 static struct clk_branch vpe_clk = {
1453         .halt_reg = 0x01c8,
1454         .halt_bit = 28,
1455         .clkr = {
1456                 .enable_reg = 0x0110,
1457                 .enable_mask = BIT(0),
1458                 .hw.init = &(struct clk_init_data){
1459                         .name = "vpe_clk",
1460                         .parent_names = (const char *[]){ "vpe_src" },
1461                         .num_parents = 1,
1462                         .ops = &clk_branch_ops,
1463                         .flags = CLK_SET_RATE_PARENT,
1464                 },
1465         },
1466 };
1467
1468 static struct freq_tbl clk_tbl_vfe[] = {
1469         {  13960000, P_PLL8,  1, 2, 55 },
1470         {  27000000, P_PXO,   1, 0,  0 },
1471         {  36570000, P_PLL8,  1, 2, 21 },
1472         {  38400000, P_PLL8,  2, 1,  5 },
1473         {  45180000, P_PLL8,  1, 2, 17 },
1474         {  48000000, P_PLL8,  2, 1,  4 },
1475         {  54860000, P_PLL8,  1, 1,  7 },
1476         {  64000000, P_PLL8,  2, 1,  3 },
1477         {  76800000, P_PLL8,  1, 1,  5 },
1478         {  96000000, P_PLL8,  2, 1,  2 },
1479         { 109710000, P_PLL8,  1, 2,  7 },
1480         { 128000000, P_PLL8,  1, 1,  3 },
1481         { 153600000, P_PLL8,  1, 2,  5 },
1482         { 200000000, P_PLL2,  2, 1,  2 },
1483         { 228570000, P_PLL2,  1, 2,  7 },
1484         { 266667000, P_PLL2,  1, 1,  3 },
1485         { 320000000, P_PLL2,  1, 2,  5 },
1486         { }
1487 };
1488
1489 static struct clk_rcg vfe_src = {
1490         .ns_reg = 0x0108,
1491         .mn = {
1492                 .mnctr_en_bit = 5,
1493                 .mnctr_reset_bit = 7,
1494                 .mnctr_mode_shift = 6,
1495                 .n_val_shift = 16,
1496                 .m_val_shift = 8,
1497                 .width = 8,
1498         },
1499         .p = {
1500                 .pre_div_shift = 10,
1501                 .pre_div_width = 1,
1502         },
1503         .s = {
1504                 .src_sel_shift = 0,
1505                 .parent_map = mmcc_pxo_pll8_pll2_map,
1506         },
1507         .freq_tbl = clk_tbl_vfe,
1508         .clkr = {
1509                 .enable_reg = 0x0104,
1510                 .enable_mask = BIT(2),
1511                 .hw.init = &(struct clk_init_data){
1512                         .name = "vfe_src",
1513                         .parent_names = mmcc_pxo_pll8_pll2,
1514                         .num_parents = 3,
1515                         .ops = &clk_rcg_ops,
1516                 },
1517         },
1518 };
1519
1520 static struct clk_branch vfe_clk = {
1521         .halt_reg = 0x01cc,
1522         .halt_bit = 6,
1523         .clkr = {
1524                 .enable_reg = 0x0104,
1525                 .enable_mask = BIT(0),
1526                 .hw.init = &(struct clk_init_data){
1527                         .name = "vfe_clk",
1528                         .parent_names = (const char *[]){ "vfe_src" },
1529                         .num_parents = 1,
1530                         .ops = &clk_branch_ops,
1531                         .flags = CLK_SET_RATE_PARENT,
1532                 },
1533         },
1534 };
1535
1536 static struct clk_branch vfe_csi_clk = {
1537         .halt_reg = 0x01cc,
1538         .halt_bit = 8,
1539         .clkr = {
1540                 .enable_reg = 0x0104,
1541                 .enable_mask = BIT(12),
1542                 .hw.init = &(struct clk_init_data){
1543                         .parent_names = (const char *[]){ "vfe_src" },
1544                         .num_parents = 1,
1545                         .name = "vfe_csi_clk",
1546                         .ops = &clk_branch_ops,
1547                         .flags = CLK_SET_RATE_PARENT,
1548                 },
1549         },
1550 };
1551
1552 static struct clk_branch gmem_axi_clk = {
1553         .halt_reg = 0x01d8,
1554         .halt_bit = 6,
1555         .clkr = {
1556                 .enable_reg = 0x0018,
1557                 .enable_mask = BIT(24),
1558                 .hw.init = &(struct clk_init_data){
1559                         .name = "gmem_axi_clk",
1560                         .ops = &clk_branch_ops,
1561                         .flags = CLK_IS_ROOT,
1562                 },
1563         },
1564 };
1565
1566 static struct clk_branch ijpeg_axi_clk = {
1567         .hwcg_reg = 0x0018,
1568         .hwcg_bit = 11,
1569         .halt_reg = 0x01d8,
1570         .halt_bit = 4,
1571         .clkr = {
1572                 .enable_reg = 0x0018,
1573                 .enable_mask = BIT(21),
1574                 .hw.init = &(struct clk_init_data){
1575                         .name = "ijpeg_axi_clk",
1576                         .ops = &clk_branch_ops,
1577                         .flags = CLK_IS_ROOT,
1578                 },
1579         },
1580 };
1581
1582 static struct clk_branch mmss_imem_axi_clk = {
1583         .hwcg_reg = 0x0018,
1584         .hwcg_bit = 15,
1585         .halt_reg = 0x01d8,
1586         .halt_bit = 7,
1587         .clkr = {
1588                 .enable_reg = 0x0018,
1589                 .enable_mask = BIT(22),
1590                 .hw.init = &(struct clk_init_data){
1591                         .name = "mmss_imem_axi_clk",
1592                         .ops = &clk_branch_ops,
1593                         .flags = CLK_IS_ROOT,
1594                 },
1595         },
1596 };
1597
1598 static struct clk_branch jpegd_axi_clk = {
1599         .halt_reg = 0x01d8,
1600         .halt_bit = 5,
1601         .clkr = {
1602                 .enable_reg = 0x0018,
1603                 .enable_mask = BIT(25),
1604                 .hw.init = &(struct clk_init_data){
1605                         .name = "jpegd_axi_clk",
1606                         .ops = &clk_branch_ops,
1607                         .flags = CLK_IS_ROOT,
1608                 },
1609         },
1610 };
1611
1612 static struct clk_branch vcodec_axi_b_clk = {
1613         .hwcg_reg = 0x0114,
1614         .hwcg_bit = 22,
1615         .halt_reg = 0x01e8,
1616         .halt_bit = 25,
1617         .clkr = {
1618                 .enable_reg = 0x0114,
1619                 .enable_mask = BIT(23),
1620                 .hw.init = &(struct clk_init_data){
1621                         .name = "vcodec_axi_b_clk",
1622                         .ops = &clk_branch_ops,
1623                         .flags = CLK_IS_ROOT,
1624                 },
1625         },
1626 };
1627
1628 static struct clk_branch vcodec_axi_a_clk = {
1629         .hwcg_reg = 0x0114,
1630         .hwcg_bit = 24,
1631         .halt_reg = 0x01e8,
1632         .halt_bit = 26,
1633         .clkr = {
1634                 .enable_reg = 0x0114,
1635                 .enable_mask = BIT(25),
1636                 .hw.init = &(struct clk_init_data){
1637                         .name = "vcodec_axi_a_clk",
1638                         .ops = &clk_branch_ops,
1639                         .flags = CLK_IS_ROOT,
1640                 },
1641         },
1642 };
1643
1644 static struct clk_branch vcodec_axi_clk = {
1645         .hwcg_reg = 0x0018,
1646         .hwcg_bit = 13,
1647         .halt_reg = 0x01d8,
1648         .halt_bit = 3,
1649         .clkr = {
1650                 .enable_reg = 0x0018,
1651                 .enable_mask = BIT(19),
1652                 .hw.init = &(struct clk_init_data){
1653                         .name = "vcodec_axi_clk",
1654                         .ops = &clk_branch_ops,
1655                         .flags = CLK_IS_ROOT,
1656                 },
1657         },
1658 };
1659
1660 static struct clk_branch vfe_axi_clk = {
1661         .halt_reg = 0x01d8,
1662         .halt_bit = 0,
1663         .clkr = {
1664                 .enable_reg = 0x0018,
1665                 .enable_mask = BIT(18),
1666                 .hw.init = &(struct clk_init_data){
1667                         .name = "vfe_axi_clk",
1668                         .ops = &clk_branch_ops,
1669                         .flags = CLK_IS_ROOT,
1670                 },
1671         },
1672 };
1673
1674 static struct clk_branch mdp_axi_clk = {
1675         .hwcg_reg = 0x0018,
1676         .hwcg_bit = 16,
1677         .halt_reg = 0x01d8,
1678         .halt_bit = 8,
1679         .clkr = {
1680                 .enable_reg = 0x0018,
1681                 .enable_mask = BIT(23),
1682                 .hw.init = &(struct clk_init_data){
1683                         .name = "mdp_axi_clk",
1684                         .ops = &clk_branch_ops,
1685                         .flags = CLK_IS_ROOT,
1686                 },
1687         },
1688 };
1689
1690 static struct clk_branch rot_axi_clk = {
1691         .hwcg_reg = 0x0020,
1692         .hwcg_bit = 25,
1693         .halt_reg = 0x01d8,
1694         .halt_bit = 2,
1695         .clkr = {
1696                 .enable_reg = 0x0020,
1697                 .enable_mask = BIT(24),
1698                 .hw.init = &(struct clk_init_data){
1699                         .name = "rot_axi_clk",
1700                         .ops = &clk_branch_ops,
1701                         .flags = CLK_IS_ROOT,
1702                 },
1703         },
1704 };
1705
1706 static struct clk_branch vpe_axi_clk = {
1707         .hwcg_reg = 0x0020,
1708         .hwcg_bit = 27,
1709         .halt_reg = 0x01d8,
1710         .halt_bit = 1,
1711         .clkr = {
1712                 .enable_reg = 0x0020,
1713                 .enable_mask = BIT(26),
1714                 .hw.init = &(struct clk_init_data){
1715                         .name = "vpe_axi_clk",
1716                         .ops = &clk_branch_ops,
1717                         .flags = CLK_IS_ROOT,
1718                 },
1719         },
1720 };
1721
1722 static struct clk_branch gfx3d_axi_clk = {
1723         .hwcg_reg = 0x0244,
1724         .hwcg_bit = 24,
1725         .halt_reg = 0x0240,
1726         .halt_bit = 30,
1727         .clkr = {
1728                 .enable_reg = 0x0244,
1729                 .enable_mask = BIT(25),
1730                 .hw.init = &(struct clk_init_data){
1731                         .name = "gfx3d_axi_clk",
1732                         .ops = &clk_branch_ops,
1733                         .flags = CLK_IS_ROOT,
1734                 },
1735         },
1736 };
1737
1738 static struct clk_branch amp_ahb_clk = {
1739         .halt_reg = 0x01dc,
1740         .halt_bit = 18,
1741         .clkr = {
1742                 .enable_reg = 0x0008,
1743                 .enable_mask = BIT(24),
1744                 .hw.init = &(struct clk_init_data){
1745                         .name = "amp_ahb_clk",
1746                         .ops = &clk_branch_ops,
1747                         .flags = CLK_IS_ROOT,
1748                 },
1749         },
1750 };
1751
1752 static struct clk_branch csi_ahb_clk = {
1753         .halt_reg = 0x01dc,
1754         .halt_bit = 16,
1755         .clkr = {
1756                 .enable_reg = 0x0008,
1757                 .enable_mask = BIT(7),
1758                 .hw.init = &(struct clk_init_data){
1759                         .name = "csi_ahb_clk",
1760                         .ops = &clk_branch_ops,
1761                         .flags = CLK_IS_ROOT
1762                 },
1763         },
1764 };
1765
1766 static struct clk_branch dsi_m_ahb_clk = {
1767         .halt_reg = 0x01dc,
1768         .halt_bit = 19,
1769         .clkr = {
1770                 .enable_reg = 0x0008,
1771                 .enable_mask = BIT(9),
1772                 .hw.init = &(struct clk_init_data){
1773                         .name = "dsi_m_ahb_clk",
1774                         .ops = &clk_branch_ops,
1775                         .flags = CLK_IS_ROOT,
1776                 },
1777         },
1778 };
1779
1780 static struct clk_branch dsi_s_ahb_clk = {
1781         .hwcg_reg = 0x0038,
1782         .hwcg_bit = 20,
1783         .halt_reg = 0x01dc,
1784         .halt_bit = 21,
1785         .clkr = {
1786                 .enable_reg = 0x0008,
1787                 .enable_mask = BIT(18),
1788                 .hw.init = &(struct clk_init_data){
1789                         .name = "dsi_s_ahb_clk",
1790                         .ops = &clk_branch_ops,
1791                         .flags = CLK_IS_ROOT,
1792                 },
1793         },
1794 };
1795
1796 static struct clk_branch dsi2_m_ahb_clk = {
1797         .halt_reg = 0x01d8,
1798         .halt_bit = 18,
1799         .clkr = {
1800                 .enable_reg = 0x0008,
1801                 .enable_mask = BIT(17),
1802                 .hw.init = &(struct clk_init_data){
1803                         .name = "dsi2_m_ahb_clk",
1804                         .ops = &clk_branch_ops,
1805                         .flags = CLK_IS_ROOT
1806                 },
1807         },
1808 };
1809
1810 static struct clk_branch dsi2_s_ahb_clk = {
1811         .hwcg_reg = 0x0038,
1812         .hwcg_bit = 15,
1813         .halt_reg = 0x01dc,
1814         .halt_bit = 20,
1815         .clkr = {
1816                 .enable_reg = 0x0008,
1817                 .enable_mask = BIT(22),
1818                 .hw.init = &(struct clk_init_data){
1819                         .name = "dsi2_s_ahb_clk",
1820                         .ops = &clk_branch_ops,
1821                         .flags = CLK_IS_ROOT,
1822                 },
1823         },
1824 };
1825
1826 static struct clk_branch gfx2d0_ahb_clk = {
1827         .hwcg_reg = 0x0038,
1828         .hwcg_bit = 28,
1829         .halt_reg = 0x01dc,
1830         .halt_bit = 2,
1831         .clkr = {
1832                 .enable_reg = 0x0008,
1833                 .enable_mask = BIT(19),
1834                 .hw.init = &(struct clk_init_data){
1835                         .name = "gfx2d0_ahb_clk",
1836                         .ops = &clk_branch_ops,
1837                         .flags = CLK_IS_ROOT,
1838                 },
1839         },
1840 };
1841
1842 static struct clk_branch gfx2d1_ahb_clk = {
1843         .hwcg_reg = 0x0038,
1844         .hwcg_bit = 29,
1845         .halt_reg = 0x01dc,
1846         .halt_bit = 3,
1847         .clkr = {
1848                 .enable_reg = 0x0008,
1849                 .enable_mask = BIT(2),
1850                 .hw.init = &(struct clk_init_data){
1851                         .name = "gfx2d1_ahb_clk",
1852                         .ops = &clk_branch_ops,
1853                         .flags = CLK_IS_ROOT,
1854                 },
1855         },
1856 };
1857
1858 static struct clk_branch gfx3d_ahb_clk = {
1859         .hwcg_reg = 0x0038,
1860         .hwcg_bit = 27,
1861         .halt_reg = 0x01dc,
1862         .halt_bit = 4,
1863         .clkr = {
1864                 .enable_reg = 0x0008,
1865                 .enable_mask = BIT(3),
1866                 .hw.init = &(struct clk_init_data){
1867                         .name = "gfx3d_ahb_clk",
1868                         .ops = &clk_branch_ops,
1869                         .flags = CLK_IS_ROOT,
1870                 },
1871         },
1872 };
1873
1874 static struct clk_branch hdmi_m_ahb_clk = {
1875         .hwcg_reg = 0x0038,
1876         .hwcg_bit = 21,
1877         .halt_reg = 0x01dc,
1878         .halt_bit = 5,
1879         .clkr = {
1880                 .enable_reg = 0x0008,
1881                 .enable_mask = BIT(14),
1882                 .hw.init = &(struct clk_init_data){
1883                         .name = "hdmi_m_ahb_clk",
1884                         .ops = &clk_branch_ops,
1885                         .flags = CLK_IS_ROOT,
1886                 },
1887         },
1888 };
1889
1890 static struct clk_branch hdmi_s_ahb_clk = {
1891         .hwcg_reg = 0x0038,
1892         .hwcg_bit = 22,
1893         .halt_reg = 0x01dc,
1894         .halt_bit = 6,
1895         .clkr = {
1896                 .enable_reg = 0x0008,
1897                 .enable_mask = BIT(4),
1898                 .hw.init = &(struct clk_init_data){
1899                         .name = "hdmi_s_ahb_clk",
1900                         .ops = &clk_branch_ops,
1901                         .flags = CLK_IS_ROOT,
1902                 },
1903         },
1904 };
1905
1906 static struct clk_branch ijpeg_ahb_clk = {
1907         .halt_reg = 0x01dc,
1908         .halt_bit = 9,
1909         .clkr = {
1910                 .enable_reg = 0x0008,
1911                 .enable_mask = BIT(5),
1912                 .hw.init = &(struct clk_init_data){
1913                         .name = "ijpeg_ahb_clk",
1914                         .ops = &clk_branch_ops,
1915                         .flags = CLK_IS_ROOT
1916                 },
1917         },
1918 };
1919
1920 static struct clk_branch mmss_imem_ahb_clk = {
1921         .hwcg_reg = 0x0038,
1922         .hwcg_bit = 12,
1923         .halt_reg = 0x01dc,
1924         .halt_bit = 10,
1925         .clkr = {
1926                 .enable_reg = 0x0008,
1927                 .enable_mask = BIT(6),
1928                 .hw.init = &(struct clk_init_data){
1929                         .name = "mmss_imem_ahb_clk",
1930                         .ops = &clk_branch_ops,
1931                         .flags = CLK_IS_ROOT
1932                 },
1933         },
1934 };
1935
1936 static struct clk_branch jpegd_ahb_clk = {
1937         .halt_reg = 0x01dc,
1938         .halt_bit = 7,
1939         .clkr = {
1940                 .enable_reg = 0x0008,
1941                 .enable_mask = BIT(21),
1942                 .hw.init = &(struct clk_init_data){
1943                         .name = "jpegd_ahb_clk",
1944                         .ops = &clk_branch_ops,
1945                         .flags = CLK_IS_ROOT,
1946                 },
1947         },
1948 };
1949
1950 static struct clk_branch mdp_ahb_clk = {
1951         .halt_reg = 0x01dc,
1952         .halt_bit = 11,
1953         .clkr = {
1954                 .enable_reg = 0x0008,
1955                 .enable_mask = BIT(10),
1956                 .hw.init = &(struct clk_init_data){
1957                         .name = "mdp_ahb_clk",
1958                         .ops = &clk_branch_ops,
1959                         .flags = CLK_IS_ROOT,
1960                 },
1961         },
1962 };
1963
1964 static struct clk_branch rot_ahb_clk = {
1965         .halt_reg = 0x01dc,
1966         .halt_bit = 13,
1967         .clkr = {
1968                 .enable_reg = 0x0008,
1969                 .enable_mask = BIT(12),
1970                 .hw.init = &(struct clk_init_data){
1971                         .name = "rot_ahb_clk",
1972                         .ops = &clk_branch_ops,
1973                         .flags = CLK_IS_ROOT
1974                 },
1975         },
1976 };
1977
1978 static struct clk_branch smmu_ahb_clk = {
1979         .hwcg_reg = 0x0008,
1980         .hwcg_bit = 26,
1981         .halt_reg = 0x01dc,
1982         .halt_bit = 22,
1983         .clkr = {
1984                 .enable_reg = 0x0008,
1985                 .enable_mask = BIT(15),
1986                 .hw.init = &(struct clk_init_data){
1987                         .name = "smmu_ahb_clk",
1988                         .ops = &clk_branch_ops,
1989                         .flags = CLK_IS_ROOT,
1990                 },
1991         },
1992 };
1993
1994 static struct clk_branch tv_enc_ahb_clk = {
1995         .halt_reg = 0x01dc,
1996         .halt_bit = 23,
1997         .clkr = {
1998                 .enable_reg = 0x0008,
1999                 .enable_mask = BIT(25),
2000                 .hw.init = &(struct clk_init_data){
2001                         .name = "tv_enc_ahb_clk",
2002                         .ops = &clk_branch_ops,
2003                         .flags = CLK_IS_ROOT,
2004                 },
2005         },
2006 };
2007
2008 static struct clk_branch vcodec_ahb_clk = {
2009         .hwcg_reg = 0x0038,
2010         .hwcg_bit = 26,
2011         .halt_reg = 0x01dc,
2012         .halt_bit = 12,
2013         .clkr = {
2014                 .enable_reg = 0x0008,
2015                 .enable_mask = BIT(11),
2016                 .hw.init = &(struct clk_init_data){
2017                         .name = "vcodec_ahb_clk",
2018                         .ops = &clk_branch_ops,
2019                         .flags = CLK_IS_ROOT,
2020                 },
2021         },
2022 };
2023
2024 static struct clk_branch vfe_ahb_clk = {
2025         .halt_reg = 0x01dc,
2026         .halt_bit = 14,
2027         .clkr = {
2028                 .enable_reg = 0x0008,
2029                 .enable_mask = BIT(13),
2030                 .hw.init = &(struct clk_init_data){
2031                         .name = "vfe_ahb_clk",
2032                         .ops = &clk_branch_ops,
2033                         .flags = CLK_IS_ROOT,
2034                 },
2035         },
2036 };
2037
2038 static struct clk_branch vpe_ahb_clk = {
2039         .halt_reg = 0x01dc,
2040         .halt_bit = 15,
2041         .clkr = {
2042                 .enable_reg = 0x0008,
2043                 .enable_mask = BIT(16),
2044                 .hw.init = &(struct clk_init_data){
2045                         .name = "vpe_ahb_clk",
2046                         .ops = &clk_branch_ops,
2047                         .flags = CLK_IS_ROOT,
2048                 },
2049         },
2050 };
2051
2052 static struct clk_regmap *mmcc_msm8960_clks[] = {
2053         [TV_ENC_AHB_CLK] = &tv_enc_ahb_clk.clkr,
2054         [AMP_AHB_CLK] = &amp_ahb_clk.clkr,
2055         [DSI2_S_AHB_CLK] = &dsi2_s_ahb_clk.clkr,
2056         [JPEGD_AHB_CLK] = &jpegd_ahb_clk.clkr,
2057         [GFX2D0_AHB_CLK] = &gfx2d0_ahb_clk.clkr,
2058         [DSI_S_AHB_CLK] = &dsi_s_ahb_clk.clkr,
2059         [DSI2_M_AHB_CLK] = &dsi2_m_ahb_clk.clkr,
2060         [VPE_AHB_CLK] = &vpe_ahb_clk.clkr,
2061         [SMMU_AHB_CLK] = &smmu_ahb_clk.clkr,
2062         [HDMI_M_AHB_CLK] = &hdmi_m_ahb_clk.clkr,
2063         [VFE_AHB_CLK] = &vfe_ahb_clk.clkr,
2064         [ROT_AHB_CLK] = &rot_ahb_clk.clkr,
2065         [VCODEC_AHB_CLK] = &vcodec_ahb_clk.clkr,
2066         [MDP_AHB_CLK] = &mdp_ahb_clk.clkr,
2067         [DSI_M_AHB_CLK] = &dsi_m_ahb_clk.clkr,
2068         [CSI_AHB_CLK] = &csi_ahb_clk.clkr,
2069         [MMSS_IMEM_AHB_CLK] = &mmss_imem_ahb_clk.clkr,
2070         [IJPEG_AHB_CLK] = &ijpeg_ahb_clk.clkr,
2071         [HDMI_S_AHB_CLK] = &hdmi_s_ahb_clk.clkr,
2072         [GFX3D_AHB_CLK] = &gfx3d_ahb_clk.clkr,
2073         [GFX2D1_AHB_CLK] = &gfx2d1_ahb_clk.clkr,
2074         [JPEGD_AXI_CLK] = &jpegd_axi_clk.clkr,
2075         [GMEM_AXI_CLK] = &gmem_axi_clk.clkr,
2076         [MDP_AXI_CLK] = &mdp_axi_clk.clkr,
2077         [MMSS_IMEM_AXI_CLK] = &mmss_imem_axi_clk.clkr,
2078         [IJPEG_AXI_CLK] = &ijpeg_axi_clk.clkr,
2079         [GFX3D_AXI_CLK] = &gfx3d_axi_clk.clkr,
2080         [VCODEC_AXI_CLK] = &vcodec_axi_clk.clkr,
2081         [VFE_AXI_CLK] = &vfe_axi_clk.clkr,
2082         [VPE_AXI_CLK] = &vpe_axi_clk.clkr,
2083         [ROT_AXI_CLK] = &rot_axi_clk.clkr,
2084         [VCODEC_AXI_A_CLK] = &vcodec_axi_a_clk.clkr,
2085         [VCODEC_AXI_B_CLK] = &vcodec_axi_b_clk.clkr,
2086         [CSI0_SRC] = &csi0_src.clkr,
2087         [CSI0_CLK] = &csi0_clk.clkr,
2088         [CSI0_PHY_CLK] = &csi0_phy_clk.clkr,
2089         [CSI1_SRC] = &csi1_src.clkr,
2090         [CSI1_CLK] = &csi1_clk.clkr,
2091         [CSI1_PHY_CLK] = &csi1_phy_clk.clkr,
2092         [CSI2_SRC] = &csi2_src.clkr,
2093         [CSI2_CLK] = &csi2_clk.clkr,
2094         [CSI2_PHY_CLK] = &csi2_phy_clk.clkr,
2095         [CSI_PIX_CLK] = &csi_pix_clk.clkr,
2096         [CSI_RDI_CLK] = &csi_rdi_clk.clkr,
2097         [MDP_VSYNC_CLK] = &mdp_vsync_clk.clkr,
2098         [HDMI_APP_CLK] = &hdmi_app_clk.clkr,
2099         [CSI_PIX1_CLK] = &csi_pix1_clk.clkr,
2100         [CSI_RDI2_CLK] = &csi_rdi2_clk.clkr,
2101         [CSI_RDI1_CLK] = &csi_rdi1_clk.clkr,
2102         [GFX2D0_SRC] = &gfx2d0_src.clkr,
2103         [GFX2D0_CLK] = &gfx2d0_clk.clkr,
2104         [GFX2D1_SRC] = &gfx2d1_src.clkr,
2105         [GFX2D1_CLK] = &gfx2d1_clk.clkr,
2106         [GFX3D_SRC] = &gfx3d_src.clkr,
2107         [GFX3D_CLK] = &gfx3d_clk.clkr,
2108         [IJPEG_SRC] = &ijpeg_src.clkr,
2109         [IJPEG_CLK] = &ijpeg_clk.clkr,
2110         [JPEGD_SRC] = &jpegd_src.clkr,
2111         [JPEGD_CLK] = &jpegd_clk.clkr,
2112         [MDP_SRC] = &mdp_src.clkr,
2113         [MDP_CLK] = &mdp_clk.clkr,
2114         [MDP_LUT_CLK] = &mdp_lut_clk.clkr,
2115         [ROT_SRC] = &rot_src.clkr,
2116         [ROT_CLK] = &rot_clk.clkr,
2117         [TV_ENC_CLK] = &tv_enc_clk.clkr,
2118         [TV_DAC_CLK] = &tv_dac_clk.clkr,
2119         [HDMI_TV_CLK] = &hdmi_tv_clk.clkr,
2120         [MDP_TV_CLK] = &mdp_tv_clk.clkr,
2121         [TV_SRC] = &tv_src.clkr,
2122         [VCODEC_SRC] = &vcodec_src.clkr,
2123         [VCODEC_CLK] = &vcodec_clk.clkr,
2124         [VFE_SRC] = &vfe_src.clkr,
2125         [VFE_CLK] = &vfe_clk.clkr,
2126         [VFE_CSI_CLK] = &vfe_csi_clk.clkr,
2127         [VPE_SRC] = &vpe_src.clkr,
2128         [VPE_CLK] = &vpe_clk.clkr,
2129         [CAMCLK0_SRC] = &camclk0_src.clkr,
2130         [CAMCLK0_CLK] = &camclk0_clk.clkr,
2131         [CAMCLK1_SRC] = &camclk1_src.clkr,
2132         [CAMCLK1_CLK] = &camclk1_clk.clkr,
2133         [CAMCLK2_SRC] = &camclk2_src.clkr,
2134         [CAMCLK2_CLK] = &camclk2_clk.clkr,
2135         [CSIPHYTIMER_SRC] = &csiphytimer_src.clkr,
2136         [CSIPHY2_TIMER_CLK] = &csiphy2_timer_clk.clkr,
2137         [CSIPHY1_TIMER_CLK] = &csiphy1_timer_clk.clkr,
2138         [CSIPHY0_TIMER_CLK] = &csiphy0_timer_clk.clkr,
2139         [PLL2] = &pll2.clkr,
2140 };
2141
2142 static const struct qcom_reset_map mmcc_msm8960_resets[] = {
2143         [VPE_AXI_RESET] = { 0x0208, 15 },
2144         [IJPEG_AXI_RESET] = { 0x0208, 14 },
2145         [MPD_AXI_RESET] = { 0x0208, 13 },
2146         [VFE_AXI_RESET] = { 0x0208, 9 },
2147         [SP_AXI_RESET] = { 0x0208, 8 },
2148         [VCODEC_AXI_RESET] = { 0x0208, 7 },
2149         [ROT_AXI_RESET] = { 0x0208, 6 },
2150         [VCODEC_AXI_A_RESET] = { 0x0208, 5 },
2151         [VCODEC_AXI_B_RESET] = { 0x0208, 4 },
2152         [FAB_S3_AXI_RESET] = { 0x0208, 3 },
2153         [FAB_S2_AXI_RESET] = { 0x0208, 2 },
2154         [FAB_S1_AXI_RESET] = { 0x0208, 1 },
2155         [FAB_S0_AXI_RESET] = { 0x0208 },
2156         [SMMU_GFX3D_ABH_RESET] = { 0x020c, 31 },
2157         [SMMU_VPE_AHB_RESET] = { 0x020c, 30 },
2158         [SMMU_VFE_AHB_RESET] = { 0x020c, 29 },
2159         [SMMU_ROT_AHB_RESET] = { 0x020c, 28 },
2160         [SMMU_VCODEC_B_AHB_RESET] = { 0x020c, 27 },
2161         [SMMU_VCODEC_A_AHB_RESET] = { 0x020c, 26 },
2162         [SMMU_MDP1_AHB_RESET] = { 0x020c, 25 },
2163         [SMMU_MDP0_AHB_RESET] = { 0x020c, 24 },
2164         [SMMU_JPEGD_AHB_RESET] = { 0x020c, 23 },
2165         [SMMU_IJPEG_AHB_RESET] = { 0x020c, 22 },
2166         [SMMU_GFX2D0_AHB_RESET] = { 0x020c, 21 },
2167         [SMMU_GFX2D1_AHB_RESET] = { 0x020c, 20 },
2168         [APU_AHB_RESET] = { 0x020c, 18 },
2169         [CSI_AHB_RESET] = { 0x020c, 17 },
2170         [TV_ENC_AHB_RESET] = { 0x020c, 15 },
2171         [VPE_AHB_RESET] = { 0x020c, 14 },
2172         [FABRIC_AHB_RESET] = { 0x020c, 13 },
2173         [GFX2D0_AHB_RESET] = { 0x020c, 12 },
2174         [GFX2D1_AHB_RESET] = { 0x020c, 11 },
2175         [GFX3D_AHB_RESET] = { 0x020c, 10 },
2176         [HDMI_AHB_RESET] = { 0x020c, 9 },
2177         [MSSS_IMEM_AHB_RESET] = { 0x020c, 8 },
2178         [IJPEG_AHB_RESET] = { 0x020c, 7 },
2179         [DSI_M_AHB_RESET] = { 0x020c, 6 },
2180         [DSI_S_AHB_RESET] = { 0x020c, 5 },
2181         [JPEGD_AHB_RESET] = { 0x020c, 4 },
2182         [MDP_AHB_RESET] = { 0x020c, 3 },
2183         [ROT_AHB_RESET] = { 0x020c, 2 },
2184         [VCODEC_AHB_RESET] = { 0x020c, 1 },
2185         [VFE_AHB_RESET] = { 0x020c, 0 },
2186         [DSI2_M_AHB_RESET] = { 0x0210, 31 },
2187         [DSI2_S_AHB_RESET] = { 0x0210, 30 },
2188         [CSIPHY2_RESET] = { 0x0210, 29 },
2189         [CSI_PIX1_RESET] = { 0x0210, 28 },
2190         [CSIPHY0_RESET] = { 0x0210, 27 },
2191         [CSIPHY1_RESET] = { 0x0210, 26 },
2192         [DSI2_RESET] = { 0x0210, 25 },
2193         [VFE_CSI_RESET] = { 0x0210, 24 },
2194         [MDP_RESET] = { 0x0210, 21 },
2195         [AMP_RESET] = { 0x0210, 20 },
2196         [JPEGD_RESET] = { 0x0210, 19 },
2197         [CSI1_RESET] = { 0x0210, 18 },
2198         [VPE_RESET] = { 0x0210, 17 },
2199         [MMSS_FABRIC_RESET] = { 0x0210, 16 },
2200         [VFE_RESET] = { 0x0210, 15 },
2201         [GFX2D0_RESET] = { 0x0210, 14 },
2202         [GFX2D1_RESET] = { 0x0210, 13 },
2203         [GFX3D_RESET] = { 0x0210, 12 },
2204         [HDMI_RESET] = { 0x0210, 11 },
2205         [MMSS_IMEM_RESET] = { 0x0210, 10 },
2206         [IJPEG_RESET] = { 0x0210, 9 },
2207         [CSI0_RESET] = { 0x0210, 8 },
2208         [DSI_RESET] = { 0x0210, 7 },
2209         [VCODEC_RESET] = { 0x0210, 6 },
2210         [MDP_TV_RESET] = { 0x0210, 4 },
2211         [MDP_VSYNC_RESET] = { 0x0210, 3 },
2212         [ROT_RESET] = { 0x0210, 2 },
2213         [TV_HDMI_RESET] = { 0x0210, 1 },
2214         [TV_ENC_RESET] = { 0x0210 },
2215         [CSI2_RESET] = { 0x0214, 2 },
2216         [CSI_RDI1_RESET] = { 0x0214, 1 },
2217         [CSI_RDI2_RESET] = { 0x0214 },
2218 };
2219
2220 static const struct regmap_config mmcc_msm8960_regmap_config = {
2221         .reg_bits       = 32,
2222         .reg_stride     = 4,
2223         .val_bits       = 32,
2224         .max_register   = 0x334,
2225         .fast_io        = true,
2226 };
2227
2228 static const struct qcom_cc_desc mmcc_msm8960_desc = {
2229         .config = &mmcc_msm8960_regmap_config,
2230         .clks = mmcc_msm8960_clks,
2231         .num_clks = ARRAY_SIZE(mmcc_msm8960_clks),
2232         .resets = mmcc_msm8960_resets,
2233         .num_resets = ARRAY_SIZE(mmcc_msm8960_resets),
2234 };
2235
2236 static const struct of_device_id mmcc_msm8960_match_table[] = {
2237         { .compatible = "qcom,mmcc-msm8960" },
2238         { }
2239 };
2240 MODULE_DEVICE_TABLE(of, mmcc_msm8960_match_table);
2241
2242 static int mmcc_msm8960_probe(struct platform_device *pdev)
2243 {
2244         return qcom_cc_probe(pdev, &mmcc_msm8960_desc);
2245 }
2246
2247 static int mmcc_msm8960_remove(struct platform_device *pdev)
2248 {
2249         qcom_cc_remove(pdev);
2250         return 0;
2251 }
2252
2253 static struct platform_driver mmcc_msm8960_driver = {
2254         .probe          = mmcc_msm8960_probe,
2255         .remove         = mmcc_msm8960_remove,
2256         .driver         = {
2257                 .name   = "mmcc-msm8960",
2258                 .owner  = THIS_MODULE,
2259                 .of_match_table = mmcc_msm8960_match_table,
2260         },
2261 };
2262
2263 module_platform_driver(mmcc_msm8960_driver);
2264
2265 MODULE_DESCRIPTION("QCOM MMCC MSM8960 Driver");
2266 MODULE_LICENSE("GPL v2");
2267 MODULE_ALIAS("platform:mmcc-msm8960");