drivers/clk/qcom/gcc-qcs404.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/regmap.h>
  12 #include <linux/reset-controller.h>
  13
  14 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
  15
  16 #include "clk-alpha-pll.h"
  17 #include "clk-branch.h"
  18 #include "clk-pll.h"
  19 #include "clk-rcg.h"
  20 #include "clk-regmap.h"
  21 #include "common.h"
  22 #include "reset.h"
  23
  24 enum {
  25         P_CORE_BI_PLL_TEST_SE,
  26         P_DSI0_PHY_PLL_OUT_BYTECLK,
  27         P_DSI0_PHY_PLL_OUT_DSICLK,
  28         P_GPLL0_OUT_AUX,
  29         P_GPLL0_OUT_MAIN,
  30         P_GPLL1_OUT_MAIN,
  31         P_GPLL3_OUT_MAIN,
  32         P_GPLL4_OUT_AUX,
  33         P_GPLL4_OUT_MAIN,
  34         P_GPLL6_OUT_AUX,
  35         P_HDMI_PHY_PLL_CLK,
  36         P_PCIE_0_PIPE_CLK,
  37         P_SLEEP_CLK,
  38         P_XO,
  39 };
  40
  41 static const struct parent_map gcc_parent_map_0[] = {
  42         { P_XO, 0 },
  43         { P_GPLL0_OUT_MAIN, 1 },
  44         { P_CORE_BI_PLL_TEST_SE, 7 },
  45 };
  46
  47 static const char * const gcc_parent_names_0[] = {
  48         "cxo",
  49         "gpll0_out_main",
  50         "core_bi_pll_test_se",
  51 };
  52
  53 static const char * const gcc_parent_names_ao_0[] = {
  54         "cxo",
  55         "gpll0_ao_out_main",
  56         "core_bi_pll_test_se",
  57 };
  58
  59 static const struct parent_map gcc_parent_map_1[] = {
  60         { P_XO, 0 },
  61         { P_CORE_BI_PLL_TEST_SE, 7 },
  62 };
  63
  64 static const char * const gcc_parent_names_1[] = {
  65         "cxo",
  66         "core_bi_pll_test_se",
  67 };
  68
  69 static const struct parent_map gcc_parent_map_2[] = {
  70         { P_XO, 0 },
  71         { P_GPLL0_OUT_MAIN, 1 },
  72         { P_GPLL6_OUT_AUX, 2 },
  73         { P_SLEEP_CLK, 6 },
  74 };
  75
  76 static const char * const gcc_parent_names_2[] = {
  77         "cxo",
  78         "gpll0_out_main",
  79         "gpll6_out_aux",
  80         "sleep_clk",
  81 };
  82
  83 static const struct parent_map gcc_parent_map_3[] = {
  84         { P_XO, 0 },
  85         { P_GPLL0_OUT_MAIN, 1 },
  86         { P_GPLL6_OUT_AUX, 2 },
  87         { P_CORE_BI_PLL_TEST_SE, 7 },
  88 };
  89
  90 static const char * const gcc_parent_names_3[] = {
  91         "cxo",
  92         "gpll0_out_main",
  93         "gpll6_out_aux",
  94         "core_bi_pll_test_se",
  95 };
  96
  97 static const struct parent_map gcc_parent_map_4[] = {
  98         { P_XO, 0 },
  99         { P_GPLL1_OUT_MAIN, 1 },
 100         { P_CORE_BI_PLL_TEST_SE, 7 },
 101 };
 102
 103 static const char * const gcc_parent_names_4[] = {
 104         "cxo",
 105         "gpll1_out_main",
 106         "core_bi_pll_test_se",
 107 };
 108
 109 static const struct parent_map gcc_parent_map_5[] = {
 110         { P_XO, 0 },
 111         { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
 112         { P_GPLL0_OUT_AUX, 2 },
 113         { P_CORE_BI_PLL_TEST_SE, 7 },
 114 };
 115
 116 static const char * const gcc_parent_names_5[] = {
 117         "cxo",
 118         "dsi0pll_byteclk_src",
 119         "gpll0_out_aux",
 120         "core_bi_pll_test_se",
 121 };
 122
 123 static const struct parent_map gcc_parent_map_6[] = {
 124         { P_XO, 0 },
 125         { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
 126         { P_GPLL0_OUT_AUX, 3 },
 127         { P_CORE_BI_PLL_TEST_SE, 7 },
 128 };
 129
 130 static const char * const gcc_parent_names_6[] = {
 131         "cxo",
 132         "dsi0_phy_pll_out_byteclk",
 133         "gpll0_out_aux",
 134         "core_bi_pll_test_se",
 135 };
 136
 137 static const struct parent_map gcc_parent_map_7[] = {
 138         { P_XO, 0 },
 139         { P_GPLL0_OUT_MAIN, 1 },
 140         { P_GPLL3_OUT_MAIN, 2 },
 141         { P_GPLL6_OUT_AUX, 3 },
 142         { P_GPLL4_OUT_AUX, 4 },
 143         { P_CORE_BI_PLL_TEST_SE, 7 },
 144 };
 145
 146 static const char * const gcc_parent_names_7[] = {
 147         "cxo",
 148         "gpll0_out_main",
 149         "gpll3_out_main",
 150         "gpll6_out_aux",
 151         "gpll4_out_aux",
 152         "core_bi_pll_test_se",
 153 };
 154
 155 static const struct parent_map gcc_parent_map_8[] = {
 156         { P_XO, 0 },
 157         { P_HDMI_PHY_PLL_CLK, 1 },
 158         { P_CORE_BI_PLL_TEST_SE, 7 },
 159 };
 160
 161 static const char * const gcc_parent_names_8[] = {
 162         "cxo",
 163         "hdmi_phy_pll_clk",
 164         "core_bi_pll_test_se",
 165 };
 166
 167 static const struct parent_map gcc_parent_map_9[] = {
 168         { P_XO, 0 },
 169         { P_GPLL0_OUT_MAIN, 1 },
 170         { P_DSI0_PHY_PLL_OUT_DSICLK, 2 },
 171         { P_GPLL6_OUT_AUX, 3 },
 172         { P_CORE_BI_PLL_TEST_SE, 7 },
 173 };
 174
 175 static const char * const gcc_parent_names_9[] = {
 176         "cxo",
 177         "gpll0_out_main",
 178         "dsi0_phy_pll_out_dsiclk",
 179         "gpll6_out_aux",
 180         "core_bi_pll_test_se",
 181 };
 182
 183 static const struct parent_map gcc_parent_map_10[] = {
 184         { P_XO, 0 },
 185         { P_SLEEP_CLK, 1 },
 186         { P_CORE_BI_PLL_TEST_SE, 7 },
 187 };
 188
 189 static const char * const gcc_parent_names_10[] = {
 190         "cxo",
 191         "sleep_clk",
 192         "core_bi_pll_test_se",
 193 };
 194
 195 static const struct parent_map gcc_parent_map_11[] = {
 196         { P_XO, 0 },
 197         { P_PCIE_0_PIPE_CLK, 1 },
 198         { P_CORE_BI_PLL_TEST_SE, 7 },
 199 };
 200
 201 static const char * const gcc_parent_names_11[] = {
 202         "cxo",
 203         "pcie_0_pipe_clk",
 204         "core_bi_pll_test_se",
 205 };
 206
 207 static const struct parent_map gcc_parent_map_12[] = {
 208         { P_XO, 0 },
 209         { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
 210         { P_GPLL0_OUT_AUX, 2 },
 211         { P_CORE_BI_PLL_TEST_SE, 7 },
 212 };
 213
 214 static const char * const gcc_parent_names_12[] = {
 215         "cxo",
 216         "dsi0pll_pclk_src",
 217         "gpll0_out_aux",
 218         "core_bi_pll_test_se",
 219 };
 220
 221 static const struct parent_map gcc_parent_map_13[] = {
 222         { P_XO, 0 },
 223         { P_GPLL0_OUT_MAIN, 1 },
 224         { P_GPLL4_OUT_MAIN, 2 },
 225         { P_GPLL6_OUT_AUX, 3 },
 226         { P_CORE_BI_PLL_TEST_SE, 7 },
 227 };
 228
 229 static const char * const gcc_parent_names_13[] = {
 230         "cxo",
 231         "gpll0_out_main",
 232         "gpll4_out_main",
 233         "gpll6_out_aux",
 234         "core_bi_pll_test_se",
 235 };
 236
 237 static const struct parent_map gcc_parent_map_14[] = {
 238         { P_XO, 0 },
 239         { P_GPLL0_OUT_MAIN, 1 },
 240         { P_GPLL4_OUT_AUX, 2 },
 241         { P_CORE_BI_PLL_TEST_SE, 7 },
 242 };
 243
 244 static const char * const gcc_parent_names_14[] = {
 245         "cxo",
 246         "gpll0_out_main",
 247         "gpll4_out_aux",
 248         "core_bi_pll_test_se",
 249 };
 250
 251 static const struct parent_map gcc_parent_map_15[] = {
 252         { P_XO, 0 },
 253         { P_GPLL0_OUT_AUX, 2 },
 254         { P_CORE_BI_PLL_TEST_SE, 7 },
 255 };
 256
 257 static const char * const gcc_parent_names_15[] = {
 258         "cxo",
 259         "gpll0_out_aux",
 260         "core_bi_pll_test_se",
 261 };
 262
 263 static const struct parent_map gcc_parent_map_16[] = {
 264         { P_XO, 0 },
 265         { P_GPLL0_OUT_MAIN, 1 },
 266         { P_GPLL0_OUT_AUX, 2 },
 267         { P_CORE_BI_PLL_TEST_SE, 7 },
 268 };
 269
 270 static const char * const gcc_parent_names_16[] = {
 271         "cxo",
 272         "gpll0_out_main",
 273         "gpll0_out_aux",
 274         "core_bi_pll_test_se",
 275 };
 276
 277 static struct clk_fixed_factor cxo = {
 278         .mult = 1,
 279         .div = 1,
 280         .hw.init = &(struct clk_init_data){
 281                 .name = "cxo",
 282                 .parent_names = (const char *[]){ "xo-board" },
 283                 .num_parents = 1,
 284                 .ops = &clk_fixed_factor_ops,
 285         },
 286 };
 287
 288 static struct clk_alpha_pll gpll0_sleep_clk_src = {
 289         .offset = 0x21000,
 290         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 291         .clkr = {
 292                 .enable_reg = 0x45008,
 293                 .enable_mask = BIT(23),
 294                 .enable_is_inverted = true,
 295                 .hw.init = &(struct clk_init_data){
 296                         .name = "gpll0_sleep_clk_src",
 297                         .parent_names = (const char *[]){ "cxo" },
 298                         .num_parents = 1,
 299                         .ops = &clk_alpha_pll_ops,
 300                 },
 301         },
 302 };
 303
 304 static struct clk_alpha_pll gpll0_out_main = {
 305         .offset = 0x21000,
 306         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 307         .flags = SUPPORTS_FSM_MODE,
 308         .clkr = {
 309                 .enable_reg = 0x45000,
 310                 .enable_mask = BIT(0),
 311                 .hw.init = &(struct clk_init_data){
 312                         .name = "gpll0_out_main",
 313                         .parent_names = (const char *[])
 314                                         { "cxo" },
 315                         .num_parents = 1,
 316                         .ops = &clk_alpha_pll_ops,
 317                 },
 318         },
 319 };
 320
 321 static struct clk_alpha_pll gpll0_ao_out_main = {
 322         .offset = 0x21000,
 323         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 324         .flags = SUPPORTS_FSM_MODE,
 325         .clkr = {
 326                 .enable_reg = 0x45000,
 327                 .enable_mask = BIT(0),
 328                 .hw.init = &(struct clk_init_data){
 329                         .name = "gpll0_ao_out_main",
 330                         .parent_names = (const char *[]){ "cxo" },
 331                         .num_parents = 1,
 332                         .flags = CLK_IS_CRITICAL,
 333                         .ops = &clk_alpha_pll_ops,
 334                 },
 335         },
 336 };
 337
 338 static struct clk_alpha_pll gpll1_out_main = {
 339         .offset = 0x20000,
 340         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 341         .clkr = {
 342                 .enable_reg = 0x45000,
 343                 .enable_mask = BIT(1),
 344                 .hw.init = &(struct clk_init_data){
 345                         .name = "gpll1_out_main",
 346                         .parent_names = (const char *[]){ "cxo" },
 347                         .num_parents = 1,
 348                         .ops = &clk_alpha_pll_ops,
 349                 },
 350         },
 351 };
 352
 353 /* 930MHz configuration */
 354 static const struct alpha_pll_config gpll3_config = {
 355         .l = 48,
 356         .alpha = 0x0,
 357         .alpha_en_mask = BIT(24),
 358         .post_div_mask = 0xf << 8,
 359         .post_div_val = 0x1 << 8,
 360         .vco_mask = 0x3 << 20,
 361         .main_output_mask = 0x1,
 362         .config_ctl_val = 0x4001055b,
 363 };
 364
 365 static const struct pll_vco gpll3_vco[] = {
 366         { 700000000, 1400000000, 0 },
 367 };
 368
 369 static struct clk_alpha_pll gpll3_out_main = {
 370         .offset = 0x22000,
 371         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 372         .vco_table = gpll3_vco,
 373         .num_vco = ARRAY_SIZE(gpll3_vco),
 374         .clkr = {
 375                 .hw.init = &(struct clk_init_data){
 376                         .name = "gpll3_out_main",
 377                         .parent_names = (const char *[]){ "cxo" },
 378                         .num_parents = 1,
 379                         .ops = &clk_alpha_pll_ops,
 380                 },
 381         },
 382 };
 383
 384 static struct clk_alpha_pll gpll4_out_main = {
 385         .offset = 0x24000,
 386         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 387         .clkr = {
 388                 .enable_reg = 0x45000,
 389                 .enable_mask = BIT(5),
 390                 .hw.init = &(struct clk_init_data){
 391                         .name = "gpll4_out_main",
 392                         .parent_names = (const char *[]){ "cxo" },
 393                         .num_parents = 1,
 394                         .ops = &clk_alpha_pll_ops,
 395                 },
 396         },
 397 };
 398
 399 static struct clk_pll gpll6 = {
 400         .l_reg = 0x37004,
 401         .m_reg = 0x37008,
 402         .n_reg = 0x3700C,
 403         .config_reg = 0x37014,
 404         .mode_reg = 0x37000,
 405         .status_reg = 0x3701C,
 406         .status_bit = 17,
 407         .clkr.hw.init = &(struct clk_init_data){
 408                 .name = "gpll6",
 409                 .parent_names = (const char *[]){ "cxo" },
 410                 .num_parents = 1,
 411                 .ops = &clk_pll_ops,
 412         },
 413 };
 414
 415 static struct clk_regmap gpll6_out_aux = {
 416         .enable_reg = 0x45000,
 417         .enable_mask = BIT(7),
 418         .hw.init = &(struct clk_init_data){
 419                 .name = "gpll6_out_aux",
 420                 .parent_names = (const char *[]){ "gpll6" },
 421                 .num_parents = 1,
 422                 .ops = &clk_pll_vote_ops,
 423         },
 424 };
 425
 426 static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
 427         F(19200000, P_XO, 1, 0, 0),
 428         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 429         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 430         F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
 431         { }
 432 };
 433
 434 static struct clk_rcg2 apss_ahb_clk_src = {
 435         .cmd_rcgr = 0x46000,
 436         .mnd_width = 0,
 437         .hid_width = 5,
 438         .parent_map = gcc_parent_map_0,
 439         .freq_tbl = ftbl_apss_ahb_clk_src,
 440         .clkr.hw.init = &(struct clk_init_data){
 441                 .name = "apss_ahb_clk_src",
 442                 .parent_names = gcc_parent_names_ao_0,
 443                 .num_parents = 3,
 444                 .flags = CLK_IS_CRITICAL,
 445                 .ops = &clk_rcg2_ops,
 446         },
 447 };
 448
 449 static const struct freq_tbl ftbl_blsp1_qup0_i2c_apps_clk_src[] = {
 450         F(19200000, P_XO, 1, 0, 0),
 451         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 452         { }
 453 };
 454
 455 static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = {
 456         .cmd_rcgr = 0x602c,
 457         .mnd_width = 0,
 458         .hid_width = 5,
 459         .parent_map = gcc_parent_map_0,
 460         .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
 461         .clkr.hw.init = &(struct clk_init_data){
 462                 .name = "blsp1_qup0_i2c_apps_clk_src",
 463                 .parent_names = gcc_parent_names_0,
 464                 .num_parents = 3,
 465                 .ops = &clk_rcg2_ops,
 466         },
 467 };
 468
 469 static const struct freq_tbl ftbl_blsp1_qup0_spi_apps_clk_src[] = {
 470         F(960000, P_XO, 10, 1, 2),
 471         F(4800000, P_XO, 4, 0, 0),
 472         F(9600000, P_XO, 2, 0, 0),
 473         F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
 474         F(19200000, P_XO, 1, 0, 0),
 475         F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
 476         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 477         { }
 478 };
 479
 480 static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = {
 481         .cmd_rcgr = 0x6034,
 482         .mnd_width = 8,
 483         .hid_width = 5,
 484         .parent_map = gcc_parent_map_0,
 485         .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
 486         .clkr.hw.init = &(struct clk_init_data){
 487                 .name = "blsp1_qup0_spi_apps_clk_src",
 488                 .parent_names = gcc_parent_names_0,
 489                 .num_parents = 3,
 490                 .ops = &clk_rcg2_ops,
 491         },
 492 };
 493
 494 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 495         .cmd_rcgr = 0x200c,
 496         .mnd_width = 0,
 497         .hid_width = 5,
 498         .parent_map = gcc_parent_map_0,
 499         .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
 500         .clkr.hw.init = &(struct clk_init_data){
 501                 .name = "blsp1_qup1_i2c_apps_clk_src",
 502                 .parent_names = gcc_parent_names_0,
 503                 .num_parents = 3,
 504                 .ops = &clk_rcg2_ops,
 505         },
 506 };
 507
 508 static const struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
 509         F(960000,   P_XO, 10, 1, 2),
 510         F(4800000,  P_XO, 4, 0, 0),
 511         F(9600000,  P_XO, 2, 0, 0),
 512         F(10480000, P_GPLL0_OUT_MAIN, 1, 3, 229),
 513         F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
 514         F(19200000, P_XO, 1, 0, 0),
 515         F(20961000, P_GPLL0_OUT_MAIN, 1, 6, 229),
 516         { }
 517 };
 518
 519 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 520         .cmd_rcgr = 0x2024,
 521         .mnd_width = 8,
 522         .hid_width = 5,
 523         .parent_map = gcc_parent_map_0,
 524         .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
 525         .clkr.hw.init = &(struct clk_init_data){
 526                 .name = "blsp1_qup1_spi_apps_clk_src",
 527                 .parent_names = gcc_parent_names_0,
 528                 .num_parents = 3,
 529                 .ops = &clk_rcg2_ops,
 530         },
 531 };
 532
 533 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 534         .cmd_rcgr = 0x3000,
 535         .mnd_width = 0,
 536         .hid_width = 5,
 537         .parent_map = gcc_parent_map_0,
 538         .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
 539         .clkr.hw.init = &(struct clk_init_data){
 540                 .name = "blsp1_qup2_i2c_apps_clk_src",
 541                 .parent_names = gcc_parent_names_0,
 542                 .num_parents = 3,
 543                 .ops = &clk_rcg2_ops,
 544         },
 545 };
 546
 547 static const struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
 548         F(960000,   P_XO, 10, 1, 2),
 549         F(4800000,  P_XO, 4, 0, 0),
 550         F(9600000,  P_XO, 2, 0, 0),
 551         F(15000000, P_GPLL0_OUT_MAIN, 1,  3, 160),
 552         F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
 553         F(19200000, P_XO, 1, 0, 0),
 554         F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
 555         F(30000000, P_GPLL0_OUT_MAIN, 1,  3, 80),
 556         { }
 557 };
 558
 559 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 560         .cmd_rcgr = 0x3014,
 561         .mnd_width = 8,
 562         .hid_width = 5,
 563         .parent_map = gcc_parent_map_0,
 564         .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
 565         .clkr.hw.init = &(struct clk_init_data){
 566                 .name = "blsp1_qup2_spi_apps_clk_src",
 567                 .parent_names = gcc_parent_names_0,
 568                 .num_parents = 3,
 569                 .ops = &clk_rcg2_ops,
 570         },
 571 };
 572
 573 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 574         .cmd_rcgr = 0x4000,
 575         .mnd_width = 0,
 576         .hid_width = 5,
 577         .parent_map = gcc_parent_map_0,
 578         .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
 579         .clkr.hw.init = &(struct clk_init_data){
 580                 .name = "blsp1_qup3_i2c_apps_clk_src",
 581                 .parent_names = gcc_parent_names_0,
 582                 .num_parents = 3,
 583                 .ops = &clk_rcg2_ops,
 584         },
 585 };
 586
 587 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 588         .cmd_rcgr = 0x4024,
 589         .mnd_width = 8,
 590         .hid_width = 5,
 591         .parent_map = gcc_parent_map_0,
 592         .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
 593         .clkr.hw.init = &(struct clk_init_data){
 594                 .name = "blsp1_qup3_spi_apps_clk_src",
 595                 .parent_names = gcc_parent_names_0,
 596                 .num_parents = 3,
 597                 .ops = &clk_rcg2_ops,
 598         },
 599 };
 600
 601 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 602         .cmd_rcgr = 0x5000,
 603         .mnd_width = 0,
 604         .hid_width = 5,
 605         .parent_map = gcc_parent_map_0,
 606         .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
 607         .clkr.hw.init = &(struct clk_init_data){
 608                 .name = "blsp1_qup4_i2c_apps_clk_src",
 609                 .parent_names = gcc_parent_names_0,
 610                 .num_parents = 3,
 611                 .ops = &clk_rcg2_ops,
 612         },
 613 };
 614
 615 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 616         .cmd_rcgr = 0x5024,
 617         .mnd_width = 8,
 618         .hid_width = 5,
 619         .parent_map = gcc_parent_map_0,
 620         .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
 621         .clkr.hw.init = &(struct clk_init_data){
 622                 .name = "blsp1_qup4_spi_apps_clk_src",
 623                 .parent_names = gcc_parent_names_0,
 624                 .num_parents = 3,
 625                 .ops = &clk_rcg2_ops,
 626         },
 627 };
 628
 629 static const struct freq_tbl ftbl_blsp1_uart0_apps_clk_src[] = {
 630         F(3686400, P_GPLL0_OUT_MAIN, 1, 72, 15625),
 631         F(7372800, P_GPLL0_OUT_MAIN, 1, 144, 15625),
 632         F(14745600, P_GPLL0_OUT_MAIN, 1, 288, 15625),
 633         F(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),
 634         F(19200000, P_XO, 1, 0, 0),
 635         F(24000000, P_GPLL0_OUT_MAIN, 1, 3, 100),
 636         F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
 637         F(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),
 638         F(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),
 639         F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),
 640         F(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),
 641         F(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),
 642         F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),
 643         F(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),
 644         F(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),
 645         F(64000000, P_GPLL0_OUT_MAIN, 1, 2, 25),
 646         { }
 647 };
 648
 649 static struct clk_rcg2 blsp1_uart0_apps_clk_src = {
 650         .cmd_rcgr = 0x600c,
 651         .mnd_width = 16,
 652         .hid_width = 5,
 653         .parent_map = gcc_parent_map_0,
 654         .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
 655         .clkr.hw.init = &(struct clk_init_data){
 656                 .name = "blsp1_uart0_apps_clk_src",
 657                 .parent_names = gcc_parent_names_0,
 658                 .num_parents = 3,
 659                 .ops = &clk_rcg2_ops,
 660         },
 661 };
 662
 663 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 664         .cmd_rcgr = 0x2044,
 665         .mnd_width = 16,
 666         .hid_width = 5,
 667         .parent_map = gcc_parent_map_0,
 668         .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
 669         .clkr.hw.init = &(struct clk_init_data){
 670                 .name = "blsp1_uart1_apps_clk_src",
 671                 .parent_names = gcc_parent_names_0,
 672                 .num_parents = 3,
 673                 .ops = &clk_rcg2_ops,
 674         },
 675 };
 676
 677 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 678         .cmd_rcgr = 0x3034,
 679         .mnd_width = 16,
 680         .hid_width = 5,
 681         .parent_map = gcc_parent_map_0,
 682         .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
 683         .clkr.hw.init = &(struct clk_init_data){
 684                 .name = "blsp1_uart2_apps_clk_src",
 685                 .parent_names = gcc_parent_names_0,
 686                 .num_parents = 3,
 687                 .ops = &clk_rcg2_ops,
 688         },
 689 };
 690
 691 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 692         .cmd_rcgr = 0x4014,
 693         .mnd_width = 16,
 694         .hid_width = 5,
 695         .cfg_off = 0x20,
 696         .parent_map = gcc_parent_map_0,
 697         .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
 698         .clkr.hw.init = &(struct clk_init_data){
 699                 .name = "blsp1_uart3_apps_clk_src",
 700                 .parent_names = gcc_parent_names_0,
 701                 .num_parents = 3,
 702                 .ops = &clk_rcg2_ops,
 703         },
 704 };
 705
 706 static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = {
 707         .cmd_rcgr = 0xc00c,
 708         .mnd_width = 0,
 709         .hid_width = 5,
 710         .parent_map = gcc_parent_map_0,
 711         .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src,
 712         .clkr.hw.init = &(struct clk_init_data){
 713                 .name = "blsp2_qup0_i2c_apps_clk_src",
 714                 .parent_names = gcc_parent_names_0,
 715                 .num_parents = 3,
 716                 .ops = &clk_rcg2_ops,
 717         },
 718 };
 719
 720 static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = {
 721         .cmd_rcgr = 0xc024,
 722         .mnd_width = 8,
 723         .hid_width = 5,
 724         .parent_map = gcc_parent_map_0,
 725         .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src,
 726         .clkr.hw.init = &(struct clk_init_data){
 727                 .name = "blsp2_qup0_spi_apps_clk_src",
 728                 .parent_names = gcc_parent_names_0,
 729                 .num_parents = 3,
 730                 .ops = &clk_rcg2_ops,
 731         },
 732 };
 733
 734 static struct clk_rcg2 blsp2_uart0_apps_clk_src = {
 735         .cmd_rcgr = 0xc044,
 736         .mnd_width = 16,
 737         .hid_width = 5,
 738         .parent_map = gcc_parent_map_0,
 739         .freq_tbl = ftbl_blsp1_uart0_apps_clk_src,
 740         .clkr.hw.init = &(struct clk_init_data){
 741                 .name = "blsp2_uart0_apps_clk_src",
 742                 .parent_names = gcc_parent_names_0,
 743                 .num_parents = 3,
 744                 .ops = &clk_rcg2_ops,
 745         },
 746 };
 747
 748 static struct clk_rcg2 byte0_clk_src = {
 749         .cmd_rcgr = 0x4d044,
 750         .mnd_width = 0,
 751         .hid_width = 5,
 752         .parent_map = gcc_parent_map_5,
 753         .clkr.hw.init = &(struct clk_init_data){
 754                 .name = "byte0_clk_src",
 755                 .parent_names = gcc_parent_names_5,
 756                 .num_parents = 4,
 757                 .flags = CLK_SET_RATE_PARENT,
 758                 .ops = &clk_byte2_ops,
 759         },
 760 };
 761
 762 static const struct freq_tbl ftbl_emac_clk_src[] = {
 763         F(5000000,   P_GPLL1_OUT_MAIN, 2, 1, 50),
 764         F(50000000,  P_GPLL1_OUT_MAIN, 10, 0, 0),
 765         F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
 766         F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
 767         { }
 768 };
 769
 770 static struct clk_rcg2 emac_clk_src = {
 771         .cmd_rcgr = 0x4e01c,
 772         .mnd_width = 8,
 773         .hid_width = 5,
 774         .parent_map = gcc_parent_map_4,
 775         .freq_tbl = ftbl_emac_clk_src,
 776         .clkr.hw.init = &(struct clk_init_data){
 777                 .name = "emac_clk_src",
 778                 .parent_names = gcc_parent_names_4,
 779                 .num_parents = 3,
 780                 .ops = &clk_rcg2_ops,
 781         },
 782 };
 783
 784 static const struct freq_tbl ftbl_emac_ptp_clk_src[] = {
 785         F(50000000,  P_GPLL1_OUT_MAIN, 10, 0, 0),
 786         F(125000000, P_GPLL1_OUT_MAIN, 4, 0, 0),
 787         F(250000000, P_GPLL1_OUT_MAIN, 2, 0, 0),
 788         { }
 789 };
 790
 791 static struct clk_rcg2 emac_ptp_clk_src = {
 792         .cmd_rcgr = 0x4e014,
 793         .mnd_width = 0,
 794         .hid_width = 5,
 795         .parent_map = gcc_parent_map_4,
 796         .freq_tbl = ftbl_emac_ptp_clk_src,
 797         .clkr.hw.init = &(struct clk_init_data){
 798                 .name = "emac_ptp_clk_src",
 799                 .parent_names = gcc_parent_names_4,
 800                 .num_parents = 3,
 801                 .ops = &clk_rcg2_ops,
 802         },
 803 };
 804
 805 static const struct freq_tbl ftbl_esc0_clk_src[] = {
 806         F(19200000, P_XO, 1, 0, 0),
 807         { }
 808 };
 809
 810 static struct clk_rcg2 esc0_clk_src = {
 811         .cmd_rcgr = 0x4d05c,
 812         .mnd_width = 0,
 813         .hid_width = 5,
 814         .parent_map = gcc_parent_map_6,
 815         .freq_tbl = ftbl_esc0_clk_src,
 816         .clkr.hw.init = &(struct clk_init_data){
 817                 .name = "esc0_clk_src",
 818                 .parent_names = gcc_parent_names_6,
 819                 .num_parents = 4,
 820                 .ops = &clk_rcg2_ops,
 821         },
 822 };
 823
 824 static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
 825         F(19200000,  P_XO, 1, 0, 0),
 826         F(50000000,  P_GPLL0_OUT_MAIN, 16, 0, 0),
 827         F(80000000,  P_GPLL0_OUT_MAIN, 10, 0, 0),
 828         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 829         F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
 830         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 831         F(228571429, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
 832         F(240000000, P_GPLL6_OUT_AUX,  4.5, 0, 0),
 833         F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
 834         F(270000000, P_GPLL6_OUT_AUX,  4, 0, 0),
 835         F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 836         F(400000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
 837         F(484800000, P_GPLL3_OUT_MAIN, 1, 0, 0),
 838         F(523200000, P_GPLL3_OUT_MAIN, 1, 0, 0),
 839         F(550000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
 840         F(598000000, P_GPLL3_OUT_MAIN, 1, 0, 0),
 841         { }
 842 };
 843
 844 static struct clk_rcg2 gfx3d_clk_src = {
 845         .cmd_rcgr = 0x59000,
 846         .mnd_width = 0,
 847         .hid_width = 5,
 848         .parent_map = gcc_parent_map_7,
 849         .freq_tbl = ftbl_gfx3d_clk_src,
 850         .clkr.hw.init = &(struct clk_init_data){
 851                 .name = "gfx3d_clk_src",
 852                 .parent_names = gcc_parent_names_7,
 853                 .num_parents = 6,
 854                 .ops = &clk_rcg2_ops,
 855         },
 856 };
 857
 858 static const struct freq_tbl ftbl_gp1_clk_src[] = {
 859         F(19200000, P_XO, 1, 0, 0),
 860         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 861         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 862         { }
 863 };
 864
 865 static struct clk_rcg2 gp1_clk_src = {
 866         .cmd_rcgr = 0x8004,
 867         .mnd_width = 8,
 868         .hid_width = 5,
 869         .parent_map = gcc_parent_map_2,
 870         .freq_tbl = ftbl_gp1_clk_src,
 871         .clkr.hw.init = &(struct clk_init_data){
 872                 .name = "gp1_clk_src",
 873                 .parent_names = gcc_parent_names_2,
 874                 .num_parents = 4,
 875                 .ops = &clk_rcg2_ops,
 876         },
 877 };
 878
 879 static struct clk_rcg2 gp2_clk_src = {
 880         .cmd_rcgr = 0x9004,
 881         .mnd_width = 8,
 882         .hid_width = 5,
 883         .parent_map = gcc_parent_map_2,
 884         .freq_tbl = ftbl_gp1_clk_src,
 885         .clkr.hw.init = &(struct clk_init_data){
 886                 .name = "gp2_clk_src",
 887                 .parent_names = gcc_parent_names_2,
 888                 .num_parents = 4,
 889                 .ops = &clk_rcg2_ops,
 890         },
 891 };
 892
 893 static struct clk_rcg2 gp3_clk_src = {
 894         .cmd_rcgr = 0xa004,
 895         .mnd_width = 8,
 896         .hid_width = 5,
 897         .parent_map = gcc_parent_map_2,
 898         .freq_tbl = ftbl_gp1_clk_src,
 899         .clkr.hw.init = &(struct clk_init_data){
 900                 .name = "gp3_clk_src",
 901                 .parent_names = gcc_parent_names_2,
 902                 .num_parents = 4,
 903                 .ops = &clk_rcg2_ops,
 904         },
 905 };
 906
 907 static struct clk_rcg2 hdmi_app_clk_src = {
 908         .cmd_rcgr = 0x4d0e4,
 909         .mnd_width = 0,
 910         .hid_width = 5,
 911         .parent_map = gcc_parent_map_1,
 912         .freq_tbl = ftbl_esc0_clk_src,
 913         .clkr.hw.init = &(struct clk_init_data){
 914                 .name = "hdmi_app_clk_src",
 915                 .parent_names = gcc_parent_names_1,
 916                 .num_parents = 2,
 917                 .ops = &clk_rcg2_ops,
 918         },
 919 };
 920
 921 static struct clk_rcg2 hdmi_pclk_clk_src = {
 922         .cmd_rcgr = 0x4d0dc,
 923         .mnd_width = 0,
 924         .hid_width = 5,
 925         .parent_map = gcc_parent_map_8,
 926         .freq_tbl = ftbl_esc0_clk_src,
 927         .clkr.hw.init = &(struct clk_init_data){
 928                 .name = "hdmi_pclk_clk_src",
 929                 .parent_names = gcc_parent_names_8,
 930                 .num_parents = 3,
 931                 .ops = &clk_rcg2_ops,
 932         },
 933 };
 934
 935 static const struct freq_tbl ftbl_mdp_clk_src[] = {
 936         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
 937         F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
 938         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
 939         F(145454545, P_GPLL0_OUT_MAIN, 5.5, 0, 0),
 940         F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
 941         F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
 942         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
 943         F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
 944         F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
 945         { }
 946 };
 947
 948 static struct clk_rcg2 mdp_clk_src = {
 949         .cmd_rcgr = 0x4d014,
 950         .mnd_width = 0,
 951         .hid_width = 5,
 952         .parent_map = gcc_parent_map_9,
 953         .freq_tbl = ftbl_mdp_clk_src,
 954         .clkr.hw.init = &(struct clk_init_data){
 955                 .name = "mdp_clk_src",
 956                 .parent_names = gcc_parent_names_9,
 957                 .num_parents = 5,
 958                 .ops = &clk_rcg2_ops,
 959         },
 960 };
 961
 962 static const struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
 963         F(1200000, P_XO, 16, 0, 0),
 964         { }
 965 };
 966
 967 static struct clk_rcg2 pcie_0_aux_clk_src = {
 968         .cmd_rcgr = 0x3e024,
 969         .mnd_width = 16,
 970         .hid_width = 5,
 971         .parent_map = gcc_parent_map_10,
 972         .freq_tbl = ftbl_pcie_0_aux_clk_src,
 973         .clkr.hw.init = &(struct clk_init_data){
 974                 .name = "pcie_0_aux_clk_src",
 975                 .parent_names = gcc_parent_names_10,
 976                 .num_parents = 3,
 977                 .ops = &clk_rcg2_ops,
 978         },
 979 };
 980
 981 static const struct freq_tbl ftbl_pcie_0_pipe_clk_src[] = {
 982         F(19200000, P_XO, 1, 0, 0),
 983         F(125000000, P_PCIE_0_PIPE_CLK, 2, 0, 0),
 984         F(250000000, P_PCIE_0_PIPE_CLK, 1, 0, 0),
 985         { }
 986 };
 987
 988 static struct clk_rcg2 pcie_0_pipe_clk_src = {
 989         .cmd_rcgr = 0x3e01c,
 990         .mnd_width = 0,
 991         .hid_width = 5,
 992         .parent_map = gcc_parent_map_11,
 993         .freq_tbl = ftbl_pcie_0_pipe_clk_src,
 994         .clkr.hw.init = &(struct clk_init_data){
 995                 .name = "pcie_0_pipe_clk_src",
 996                 .parent_names = gcc_parent_names_11,
 997                 .num_parents = 3,
 998                 .ops = &clk_rcg2_ops,
 999         },
1000 };
1001
1002 static struct clk_rcg2 pclk0_clk_src = {
1003         .cmd_rcgr = 0x4d000,
1004         .mnd_width = 8,
1005         .hid_width = 5,
1006         .parent_map = gcc_parent_map_12,
1007         .clkr.hw.init = &(struct clk_init_data){
1008                 .name = "pclk0_clk_src",
1009                 .parent_names = gcc_parent_names_12,
1010                 .num_parents = 4,
1011                 .flags = CLK_SET_RATE_PARENT,
1012                 .ops = &clk_pixel_ops,
1013         },
1014 };
1015
1016 static const struct freq_tbl ftbl_pdm2_clk_src[] = {
1017         F(19200000, P_XO, 1, 0, 0),
1018         F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
1019         { }
1020 };
1021
1022 static struct clk_rcg2 pdm2_clk_src = {
1023         .cmd_rcgr = 0x44010,
1024         .mnd_width = 0,
1025         .hid_width = 5,
1026         .parent_map = gcc_parent_map_0,
1027         .freq_tbl = ftbl_pdm2_clk_src,
1028         .clkr.hw.init = &(struct clk_init_data){
1029                 .name = "pdm2_clk_src",
1030                 .parent_names = gcc_parent_names_0,
1031                 .num_parents = 3,
1032                 .ops = &clk_rcg2_ops,
1033         },
1034 };
1035
1036 static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
1037         F(144000, P_XO, 16, 3, 25),
1038         F(400000, P_XO, 12, 1, 4),
1039         F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1040         F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1041         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1042         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1043         F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1044         F(192000000, P_GPLL4_OUT_MAIN, 6, 0, 0),
1045         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1046         F(384000000, P_GPLL4_OUT_MAIN, 3, 0, 0),
1047         { }
1048 };
1049
1050 static struct clk_rcg2 sdcc1_apps_clk_src = {
1051         .cmd_rcgr = 0x42004,
1052         .mnd_width = 8,
1053         .hid_width = 5,
1054         .parent_map = gcc_parent_map_13,
1055         .freq_tbl = ftbl_sdcc1_apps_clk_src,
1056         .clkr.hw.init = &(struct clk_init_data){
1057                 .name = "sdcc1_apps_clk_src",
1058                 .parent_names = gcc_parent_names_13,
1059                 .num_parents = 5,
1060                 .ops = &clk_rcg2_floor_ops,
1061         },
1062 };
1063
1064 static const struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
1065         F(160000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1066         F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1067         { }
1068 };
1069
1070 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
1071         .cmd_rcgr = 0x5d000,
1072         .mnd_width = 8,
1073         .hid_width = 5,
1074         .parent_map = gcc_parent_map_3,
1075         .freq_tbl = ftbl_sdcc1_ice_core_clk_src,
1076         .clkr.hw.init = &(struct clk_init_data){
1077                 .name = "sdcc1_ice_core_clk_src",
1078                 .parent_names = gcc_parent_names_3,
1079                 .num_parents = 4,
1080                 .ops = &clk_rcg2_ops,
1081         },
1082 };
1083
1084 static const struct freq_tbl ftbl_sdcc2_apps_clk_src[] = {
1085         F(144000, P_XO, 16, 3, 25),
1086         F(400000, P_XO, 12, 1, 4),
1087         F(20000000, P_GPLL0_OUT_MAIN, 10, 1, 4),
1088         F(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),
1089         F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
1090         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1091         F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1092         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1093         { }
1094 };
1095
1096 static struct clk_rcg2 sdcc2_apps_clk_src = {
1097         .cmd_rcgr = 0x43004,
1098         .mnd_width = 8,
1099         .hid_width = 5,
1100         .parent_map = gcc_parent_map_14,
1101         .freq_tbl = ftbl_sdcc2_apps_clk_src,
1102         .clkr.hw.init = &(struct clk_init_data){
1103                 .name = "sdcc2_apps_clk_src",
1104                 .parent_names = gcc_parent_names_14,
1105                 .num_parents = 4,
1106                 .ops = &clk_rcg2_floor_ops,
1107         },
1108 };
1109
1110 static struct clk_rcg2 usb20_mock_utmi_clk_src = {
1111         .cmd_rcgr = 0x41048,
1112         .mnd_width = 0,
1113         .hid_width = 5,
1114         .parent_map = gcc_parent_map_1,
1115         .freq_tbl = ftbl_esc0_clk_src,
1116         .clkr.hw.init = &(struct clk_init_data){
1117                 .name = "usb20_mock_utmi_clk_src",
1118                 .parent_names = gcc_parent_names_1,
1119                 .num_parents = 2,
1120                 .ops = &clk_rcg2_ops,
1121         },
1122 };
1123
1124 static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1125         F(19200000, P_XO, 1, 0, 0),
1126         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1127         F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1128         F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1129         { }
1130 };
1131
1132 static struct clk_rcg2 usb30_master_clk_src = {
1133         .cmd_rcgr = 0x39028,
1134         .mnd_width = 8,
1135         .hid_width = 5,
1136         .parent_map = gcc_parent_map_0,
1137         .freq_tbl = ftbl_usb30_master_clk_src,
1138         .clkr.hw.init = &(struct clk_init_data){
1139                 .name = "usb30_master_clk_src",
1140                 .parent_names = gcc_parent_names_0,
1141                 .num_parents = 3,
1142                 .ops = &clk_rcg2_ops,
1143         },
1144 };
1145
1146 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1147         .cmd_rcgr = 0x3901c,
1148         .mnd_width = 0,
1149         .hid_width = 5,
1150         .parent_map = gcc_parent_map_1,
1151         .freq_tbl = ftbl_esc0_clk_src,
1152         .clkr.hw.init = &(struct clk_init_data){
1153                 .name = "usb30_mock_utmi_clk_src",
1154                 .parent_names = gcc_parent_names_1,
1155                 .num_parents = 2,
1156                 .ops = &clk_rcg2_ops,
1157         },
1158 };
1159
1160 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1161         .cmd_rcgr = 0x3903c,
1162         .mnd_width = 0,
1163         .hid_width = 5,
1164         .parent_map = gcc_parent_map_1,
1165         .freq_tbl = ftbl_pcie_0_aux_clk_src,
1166         .clkr.hw.init = &(struct clk_init_data){
1167                 .name = "usb3_phy_aux_clk_src",
1168                 .parent_names = gcc_parent_names_1,
1169                 .num_parents = 2,
1170                 .ops = &clk_rcg2_ops,
1171         },
1172 };
1173
1174 static const struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1175         F(19200000, P_XO, 1, 0, 0),
1176         F(80000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1177         F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
1178         F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1179         F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
1180         { }
1181 };
1182
1183 static struct clk_rcg2 usb_hs_system_clk_src = {
1184         .cmd_rcgr = 0x41010,
1185         .mnd_width = 0,
1186         .hid_width = 5,
1187         .parent_map = gcc_parent_map_3,
1188         .freq_tbl = ftbl_usb_hs_system_clk_src,
1189         .clkr.hw.init = &(struct clk_init_data){
1190                 .name = "usb_hs_system_clk_src",
1191                 .parent_names = gcc_parent_names_3,
1192                 .num_parents = 4,
1193                 .ops = &clk_rcg2_ops,
1194         },
1195 };
1196
1197 static struct clk_rcg2 vsync_clk_src = {
1198         .cmd_rcgr = 0x4d02c,
1199         .mnd_width = 0,
1200         .hid_width = 5,
1201         .parent_map = gcc_parent_map_15,
1202         .freq_tbl = ftbl_esc0_clk_src,
1203         .clkr.hw.init = &(struct clk_init_data){
1204                 .name = "vsync_clk_src",
1205                 .parent_names = gcc_parent_names_15,
1206                 .num_parents = 3,
1207                 .ops = &clk_rcg2_ops,
1208         },
1209 };
1210
1211 static const struct freq_tbl ftbl_cdsp_bimc_clk_src[] = {
1212         F(19200000, P_XO, 1, 0, 0),
1213         F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
1214         F(266666667, P_GPLL0_OUT_MAIN, 3, 0, 0),
1215         F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
1216         { }
1217 };
1218
1219 static struct clk_rcg2 cdsp_bimc_clk_src = {
1220         .cmd_rcgr = 0x5e010,
1221         .mnd_width = 0,
1222         .hid_width = 5,
1223         .parent_map = gcc_parent_map_16,
1224         .freq_tbl = ftbl_cdsp_bimc_clk_src,
1225         .clkr.hw.init = &(struct clk_init_data) {
1226                 .name = "cdsp_bimc_clk_src",
1227                 .parent_names = gcc_parent_names_16,
1228                 .num_parents = 4,
1229                 .ops = &clk_rcg2_ops,
1230         },
1231 };
1232
1233 static struct clk_branch gcc_apss_ahb_clk = {
1234         .halt_reg = 0x4601c,
1235         .halt_check = BRANCH_HALT_VOTED,
1236         .clkr = {
1237                 .enable_reg = 0x45004,
1238                 .enable_mask = BIT(14),
1239                 .hw.init = &(struct clk_init_data){
1240                         .name = "gcc_apss_ahb_clk",
1241                         .parent_names = (const char *[]){
1242                                 "apss_ahb_clk_src",
1243                         },
1244                         .num_parents = 1,
1245                         .flags = CLK_SET_RATE_PARENT,
1246                         .ops = &clk_branch2_ops,
1247                 },
1248         },
1249 };
1250
1251 static struct clk_branch gcc_apss_tcu_clk = {
1252         .halt_reg = 0x5b004,
1253         .halt_check = BRANCH_VOTED,
1254         .clkr = {
1255                 .enable_reg = 0x4500c,
1256                 .enable_mask = BIT(1),
1257                 .hw.init = &(struct clk_init_data){
1258                         .name = "gcc_apss_tcu_clk",
1259                         .ops = &clk_branch2_ops,
1260                 },
1261         },
1262 };
1263
1264 static struct clk_branch gcc_bimc_gfx_clk = {
1265         .halt_reg = 0x59034,
1266         .halt_check = BRANCH_HALT,
1267         .clkr = {
1268                 .enable_reg = 0x59034,
1269                 .enable_mask = BIT(0),
1270                 .hw.init = &(struct clk_init_data){
1271                         .name = "gcc_bimc_gfx_clk",
1272                         .ops = &clk_branch2_ops,
1273                         .parent_names = (const char *[]){
1274                                 "gcc_apss_tcu_clk",
1275                         },
1276
1277                 },
1278         },
1279 };
1280
1281 static struct clk_branch gcc_bimc_gpu_clk = {
1282         .halt_reg = 0x59030,
1283         .halt_check = BRANCH_HALT,
1284         .clkr = {
1285                 .enable_reg = 0x59030,
1286                 .enable_mask = BIT(0),
1287                 .hw.init = &(struct clk_init_data){
1288                         .name = "gcc_bimc_gpu_clk",
1289                         .ops = &clk_branch2_ops,
1290                 },
1291         },
1292 };
1293
1294 static struct clk_branch gcc_bimc_cdsp_clk = {
1295         .halt_reg = 0x31030,
1296         .halt_check = BRANCH_HALT,
1297         .clkr = {
1298                 .enable_reg = 0x31030,
1299                 .enable_mask = BIT(0),
1300                 .hw.init = &(struct clk_init_data) {
1301                         .name = "gcc_bimc_cdsp_clk",
1302                         .parent_names = (const char *[]) {
1303                                 "cdsp_bimc_clk_src",
1304                         },
1305                         .num_parents = 1,
1306                         .flags = CLK_SET_RATE_PARENT,
1307                         .ops = &clk_branch2_ops,
1308                 },
1309         },
1310 };
1311
1312 static struct clk_branch gcc_bimc_mdss_clk = {
1313         .halt_reg = 0x31038,
1314         .halt_check = BRANCH_HALT,
1315         .clkr = {
1316                 .enable_reg = 0x31038,
1317                 .enable_mask = BIT(0),
1318                 .hw.init = &(struct clk_init_data){
1319                         .name = "gcc_bimc_mdss_clk",
1320                         .ops = &clk_branch2_ops,
1321                 },
1322         },
1323 };
1324
1325 static struct clk_branch gcc_blsp1_ahb_clk = {
1326         .halt_reg = 0x1008,
1327         .halt_check = BRANCH_HALT_VOTED,
1328         .clkr = {
1329                 .enable_reg = 0x45004,
1330                 .enable_mask = BIT(10),
1331                 .hw.init = &(struct clk_init_data){
1332                         .name = "gcc_blsp1_ahb_clk",
1333                         .ops = &clk_branch2_ops,
1334                 },
1335         },
1336 };
1337
1338 static struct clk_branch gcc_dcc_clk = {
1339         .halt_reg = 0x77004,
1340         .halt_check = BRANCH_HALT,
1341         .clkr = {
1342                 .enable_reg = 0x77004,
1343                 .enable_mask = BIT(0),
1344                 .hw.init = &(struct clk_init_data){
1345                         .name = "gcc_dcc_clk",
1346                         .ops = &clk_branch2_ops,
1347                 },
1348         },
1349 };
1350
1351 static struct clk_branch gcc_dcc_xo_clk = {
1352         .halt_reg = 0x77008,
1353         .halt_check = BRANCH_HALT,
1354         .clkr = {
1355                 .enable_reg = 0x77008,
1356                 .enable_mask = BIT(0),
1357                 .hw.init = &(struct clk_init_data){
1358                         .name = "gcc_dcc_xo_clk",
1359                         .ops = &clk_branch2_ops,
1360                 },
1361         },
1362 };
1363
1364 static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = {
1365         .halt_reg = 0x6028,
1366         .halt_check = BRANCH_HALT,
1367         .clkr = {
1368                 .enable_reg = 0x6028,
1369                 .enable_mask = BIT(0),
1370                 .hw.init = &(struct clk_init_data){
1371                         .name = "gcc_blsp1_qup0_i2c_apps_clk",
1372                         .parent_names = (const char *[]){
1373                                 "blsp1_qup0_i2c_apps_clk_src",
1374                         },
1375                         .num_parents = 1,
1376                         .flags = CLK_SET_RATE_PARENT,
1377                         .ops = &clk_branch2_ops,
1378                 },
1379         },
1380 };
1381
1382 static struct clk_branch gcc_blsp1_qup0_spi_apps_clk = {
1383         .halt_reg = 0x6024,
1384         .halt_check = BRANCH_HALT,
1385         .clkr = {
1386                 .enable_reg = 0x6024,
1387                 .enable_mask = BIT(0),
1388                 .hw.init = &(struct clk_init_data){
1389                         .name = "gcc_blsp1_qup0_spi_apps_clk",
1390                         .parent_names = (const char *[]){
1391                                 "blsp1_qup0_spi_apps_clk_src",
1392                         },
1393                         .num_parents = 1,
1394                         .flags = CLK_SET_RATE_PARENT,
1395                         .ops = &clk_branch2_ops,
1396                 },
1397         },
1398 };
1399
1400 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1401         .halt_reg = 0x2008,
1402         .halt_check = BRANCH_HALT,
1403         .clkr = {
1404                 .enable_reg = 0x2008,
1405                 .enable_mask = BIT(0),
1406                 .hw.init = &(struct clk_init_data){
1407                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1408                         .parent_names = (const char *[]){
1409                                 "blsp1_qup1_i2c_apps_clk_src",
1410                         },
1411                         .num_parents = 1,
1412                         .flags = CLK_SET_RATE_PARENT,
1413                         .ops = &clk_branch2_ops,
1414                 },
1415         },
1416 };
1417
1418 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1419         .halt_reg = 0x2004,
1420         .halt_check = BRANCH_HALT,
1421         .clkr = {
1422                 .enable_reg = 0x2004,
1423                 .enable_mask = BIT(0),
1424                 .hw.init = &(struct clk_init_data){
1425                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1426                         .parent_names = (const char *[]){
1427                                 "blsp1_qup1_spi_apps_clk_src",
1428                         },
1429                         .num_parents = 1,
1430                         .flags = CLK_SET_RATE_PARENT,
1431                         .ops = &clk_branch2_ops,
1432                 },
1433         },
1434 };
1435
1436 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1437         .halt_reg = 0x3010,
1438         .halt_check = BRANCH_HALT,
1439         .clkr = {
1440                 .enable_reg = 0x3010,
1441                 .enable_mask = BIT(0),
1442                 .hw.init = &(struct clk_init_data){
1443                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1444                         .parent_names = (const char *[]){
1445                                 "blsp1_qup2_i2c_apps_clk_src",
1446                         },
1447                         .num_parents = 1,
1448                         .flags = CLK_SET_RATE_PARENT,
1449                         .ops = &clk_branch2_ops,
1450                 },
1451         },
1452 };
1453
1454 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1455         .halt_reg = 0x300c,
1456         .halt_check = BRANCH_HALT,
1457         .clkr = {
1458                 .enable_reg = 0x300c,
1459                 .enable_mask = BIT(0),
1460                 .hw.init = &(struct clk_init_data){
1461                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1462                         .parent_names = (const char *[]){
1463                                 "blsp1_qup2_spi_apps_clk_src",
1464                         },
1465                         .num_parents = 1,
1466                         .flags = CLK_SET_RATE_PARENT,
1467                         .ops = &clk_branch2_ops,
1468                 },
1469         },
1470 };
1471
1472 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1473         .halt_reg = 0x4020,
1474         .halt_check = BRANCH_HALT,
1475         .clkr = {
1476                 .enable_reg = 0x4020,
1477                 .enable_mask = BIT(0),
1478                 .hw.init = &(struct clk_init_data){
1479                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1480                         .parent_names = (const char *[]){
1481                                 "blsp1_qup3_i2c_apps_clk_src",
1482                         },
1483                         .num_parents = 1,
1484                         .flags = CLK_SET_RATE_PARENT,
1485                         .ops = &clk_branch2_ops,
1486                 },
1487         },
1488 };
1489
1490 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1491         .halt_reg = 0x401c,
1492         .halt_check = BRANCH_HALT,
1493         .clkr = {
1494                 .enable_reg = 0x401c,
1495                 .enable_mask = BIT(0),
1496                 .hw.init = &(struct clk_init_data){
1497                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1498                         .parent_names = (const char *[]){
1499                                 "blsp1_qup3_spi_apps_clk_src",
1500                         },
1501                         .num_parents = 1,
1502                         .flags = CLK_SET_RATE_PARENT,
1503                         .ops = &clk_branch2_ops,
1504                 },
1505         },
1506 };
1507
1508 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1509         .halt_reg = 0x5020,
1510         .halt_check = BRANCH_HALT,
1511         .clkr = {
1512                 .enable_reg = 0x5020,
1513                 .enable_mask = BIT(0),
1514                 .hw.init = &(struct clk_init_data){
1515                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1516                         .parent_names = (const char *[]){
1517                                 "blsp1_qup4_i2c_apps_clk_src",
1518                         },
1519                         .num_parents = 1,
1520                         .flags = CLK_SET_RATE_PARENT,
1521                         .ops = &clk_branch2_ops,
1522                 },
1523         },
1524 };
1525
1526 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1527         .halt_reg = 0x501c,
1528         .halt_check = BRANCH_HALT,
1529         .clkr = {
1530                 .enable_reg = 0x501c,
1531                 .enable_mask = BIT(0),
1532                 .hw.init = &(struct clk_init_data){
1533                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1534                         .parent_names = (const char *[]){
1535                                 "blsp1_qup4_spi_apps_clk_src",
1536                         },
1537                         .num_parents = 1,
1538                         .flags = CLK_SET_RATE_PARENT,
1539                         .ops = &clk_branch2_ops,
1540                 },
1541         },
1542 };
1543
1544 static struct clk_branch gcc_blsp1_uart0_apps_clk = {
1545         .halt_reg = 0x6004,
1546         .halt_check = BRANCH_HALT,
1547         .clkr = {
1548                 .enable_reg = 0x6004,
1549                 .enable_mask = BIT(0),
1550                 .hw.init = &(struct clk_init_data){
1551                         .name = "gcc_blsp1_uart0_apps_clk",
1552                         .parent_names = (const char *[]){
1553                                 "blsp1_uart0_apps_clk_src",
1554                         },
1555                         .num_parents = 1,
1556                         .flags = CLK_SET_RATE_PARENT,
1557                         .ops = &clk_branch2_ops,
1558                 },
1559         },
1560 };
1561
1562 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1563         .halt_reg = 0x203c,
1564         .halt_check = BRANCH_HALT,
1565         .clkr = {
1566                 .enable_reg = 0x203c,
1567                 .enable_mask = BIT(0),
1568                 .hw.init = &(struct clk_init_data){
1569                         .name = "gcc_blsp1_uart1_apps_clk",
1570                         .parent_names = (const char *[]){
1571                                 "blsp1_uart1_apps_clk_src",
1572                         },
1573                         .num_parents = 1,
1574                         .flags = CLK_SET_RATE_PARENT,
1575                         .ops = &clk_branch2_ops,
1576                 },
1577         },
1578 };
1579
1580 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1581         .halt_reg = 0x302c,
1582         .halt_check = BRANCH_HALT,
1583         .clkr = {
1584                 .enable_reg = 0x302c,
1585                 .enable_mask = BIT(0),
1586                 .hw.init = &(struct clk_init_data){
1587                         .name = "gcc_blsp1_uart2_apps_clk",
1588                         .parent_names = (const char *[]){
1589                                 "blsp1_uart2_apps_clk_src",
1590                         },
1591                         .num_parents = 1,
1592                         .flags = CLK_SET_RATE_PARENT,
1593                         .ops = &clk_branch2_ops,
1594                 },
1595         },
1596 };
1597
1598 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1599         .halt_reg = 0x400c,
1600         .halt_check = BRANCH_HALT,
1601         .clkr = {
1602                 .enable_reg = 0x400c,
1603                 .enable_mask = BIT(0),
1604                 .hw.init = &(struct clk_init_data){
1605                         .name = "gcc_blsp1_uart3_apps_clk",
1606                         .parent_names = (const char *[]){
1607                                 "blsp1_uart3_apps_clk_src",
1608                         },
1609                         .num_parents = 1,
1610                         .flags = CLK_SET_RATE_PARENT,
1611                         .ops = &clk_branch2_ops,
1612                 },
1613         },
1614 };
1615
1616 static struct clk_branch gcc_blsp2_ahb_clk = {
1617         .halt_reg = 0xb008,
1618         .halt_check = BRANCH_HALT_VOTED,
1619         .clkr = {
1620                 .enable_reg = 0x45004,
1621                 .enable_mask = BIT(20),
1622                 .hw.init = &(struct clk_init_data){
1623                         .name = "gcc_blsp2_ahb_clk",
1624                         .ops = &clk_branch2_ops,
1625                 },
1626         },
1627 };
1628
1629 static struct clk_branch gcc_blsp2_qup0_i2c_apps_clk = {
1630         .halt_reg = 0xc008,
1631         .halt_check = BRANCH_HALT,
1632         .clkr = {
1633                 .enable_reg = 0xc008,
1634                 .enable_mask = BIT(0),
1635                 .hw.init = &(struct clk_init_data){
1636                         .name = "gcc_blsp2_qup0_i2c_apps_clk",
1637                         .parent_names = (const char *[]){
1638                                 "blsp2_qup0_i2c_apps_clk_src",
1639                         },
1640                         .num_parents = 1,
1641                         .flags = CLK_SET_RATE_PARENT,
1642                         .ops = &clk_branch2_ops,
1643                 },
1644         },
1645 };
1646
1647 static struct clk_branch gcc_blsp2_qup0_spi_apps_clk = {
1648         .halt_reg = 0xc004,
1649         .halt_check = BRANCH_HALT,
1650         .clkr = {
1651                 .enable_reg = 0xc004,
1652                 .enable_mask = BIT(0),
1653                 .hw.init = &(struct clk_init_data){
1654                         .name = "gcc_blsp2_qup0_spi_apps_clk",
1655                         .parent_names = (const char *[]){
1656                                 "blsp2_qup0_spi_apps_clk_src",
1657                         },
1658                         .num_parents = 1,
1659                         .flags = CLK_SET_RATE_PARENT,
1660                         .ops = &clk_branch2_ops,
1661                 },
1662         },
1663 };
1664
1665 static struct clk_branch gcc_blsp2_uart0_apps_clk = {
1666         .halt_reg = 0xc03c,
1667         .halt_check = BRANCH_HALT,
1668         .clkr = {
1669                 .enable_reg = 0xc03c,
1670                 .enable_mask = BIT(0),
1671                 .hw.init = &(struct clk_init_data){
1672                         .name = "gcc_blsp2_uart0_apps_clk",
1673                         .parent_names = (const char *[]){
1674                                 "blsp2_uart0_apps_clk_src",
1675                         },
1676                         .num_parents = 1,
1677                         .flags = CLK_SET_RATE_PARENT,
1678                         .ops = &clk_branch2_ops,
1679                 },
1680         },
1681 };
1682
1683 static struct clk_branch gcc_boot_rom_ahb_clk = {
1684         .halt_reg = 0x1300c,
1685         .halt_check = BRANCH_HALT_VOTED,
1686         .clkr = {
1687                 .enable_reg = 0x45004,
1688                 .enable_mask = BIT(7),
1689                 .hw.init = &(struct clk_init_data){
1690                         .name = "gcc_boot_rom_ahb_clk",
1691                         .ops = &clk_branch2_ops,
1692                 },
1693         },
1694 };
1695
1696 static struct clk_branch gcc_crypto_ahb_clk = {
1697         .halt_reg = 0x16024,
1698         .halt_check = BRANCH_VOTED,
1699         .clkr = {
1700                 .enable_reg = 0x45004,
1701                 .enable_mask = BIT(0),
1702                 .hw.init = &(struct clk_init_data){
1703                         .name = "gcc_crypto_ahb_clk",
1704                         .ops = &clk_branch2_ops,
1705                 },
1706         },
1707 };
1708
1709 static struct clk_branch gcc_crypto_axi_clk = {
1710         .halt_reg = 0x16020,
1711         .halt_check = BRANCH_VOTED,
1712         .clkr = {
1713                 .enable_reg = 0x45004,
1714                 .enable_mask = BIT(1),
1715                 .hw.init = &(struct clk_init_data){
1716                         .name = "gcc_crypto_axi_clk",
1717                         .ops = &clk_branch2_ops,
1718                 },
1719         },
1720 };
1721
1722 static struct clk_branch gcc_crypto_clk = {
1723         .halt_reg = 0x1601c,
1724         .halt_check = BRANCH_VOTED,
1725         .clkr = {
1726                 .enable_reg = 0x45004,
1727                 .enable_mask = BIT(2),
1728                 .hw.init = &(struct clk_init_data){
1729                         .name = "gcc_crypto_clk",
1730                         .ops = &clk_branch2_ops,
1731                 },
1732         },
1733 };
1734
1735 static struct clk_branch gcc_eth_axi_clk = {
1736         .halt_reg = 0x4e010,
1737         .halt_check = BRANCH_HALT,
1738         .clkr = {
1739                 .enable_reg = 0x4e010,
1740                 .enable_mask = BIT(0),
1741                 .hw.init = &(struct clk_init_data){
1742                         .name = "gcc_eth_axi_clk",
1743                         .ops = &clk_branch2_ops,
1744                 },
1745         },
1746 };
1747
1748 static struct clk_branch gcc_eth_ptp_clk = {
1749         .halt_reg = 0x4e004,
1750         .halt_check = BRANCH_HALT,
1751         .clkr = {
1752                 .enable_reg = 0x4e004,
1753                 .enable_mask = BIT(0),
1754                 .hw.init = &(struct clk_init_data){
1755                         .name = "gcc_eth_ptp_clk",
1756                         .parent_names = (const char *[]){
1757                                 "emac_ptp_clk_src",
1758                         },
1759                         .num_parents = 1,
1760                         .flags = CLK_SET_RATE_PARENT,
1761                         .ops = &clk_branch2_ops,
1762                 },
1763         },
1764 };
1765
1766 static struct clk_branch gcc_eth_rgmii_clk = {
1767         .halt_reg = 0x4e008,
1768         .halt_check = BRANCH_HALT,
1769         .clkr = {
1770                 .enable_reg = 0x4e008,
1771                 .enable_mask = BIT(0),
1772                 .hw.init = &(struct clk_init_data){
1773                         .name = "gcc_eth_rgmii_clk",
1774                         .parent_names = (const char *[]){
1775                                 "emac_clk_src",
1776                         },
1777                         .num_parents = 1,
1778                         .flags = CLK_SET_RATE_PARENT,
1779                         .ops = &clk_branch2_ops,
1780                 },
1781         },
1782 };
1783
1784 static struct clk_branch gcc_eth_slave_ahb_clk = {
1785         .halt_reg = 0x4e00c,
1786         .halt_check = BRANCH_HALT,
1787         .clkr = {
1788                 .enable_reg = 0x4e00c,
1789                 .enable_mask = BIT(0),
1790                 .hw.init = &(struct clk_init_data){
1791                         .name = "gcc_eth_slave_ahb_clk",
1792                         .ops = &clk_branch2_ops,
1793                 },
1794         },
1795 };
1796
1797 static struct clk_branch gcc_geni_ir_s_clk = {
1798         .halt_reg = 0xf008,
1799         .halt_check = BRANCH_HALT,
1800         .clkr = {
1801                 .enable_reg = 0xf008,
1802                 .enable_mask = BIT(0),
1803                 .hw.init = &(struct clk_init_data){
1804                         .name = "gcc_geni_ir_s_clk",
1805                         .ops = &clk_branch2_ops,
1806                 },
1807         },
1808 };
1809
1810 static struct clk_branch gcc_geni_ir_h_clk = {
1811         .halt_reg = 0xf004,
1812         .halt_check = BRANCH_HALT,
1813         .clkr = {
1814                 .enable_reg = 0xf004,
1815                 .enable_mask = BIT(0),
1816                 .hw.init = &(struct clk_init_data){
1817                         .name = "gcc_geni_ir_h_clk",
1818                         .ops = &clk_branch2_ops,
1819                 },
1820         },
1821 };
1822
1823 static struct clk_branch gcc_gfx_tcu_clk = {
1824         .halt_reg = 0x12020,
1825         .halt_check = BRANCH_VOTED,
1826         .clkr = {
1827                 .enable_reg = 0x4500C,
1828                 .enable_mask = BIT(2),
1829                 .hw.init = &(struct clk_init_data){
1830                         .name = "gcc_gfx_tcu_clk",
1831                         .ops = &clk_branch2_ops,
1832                 },
1833         },
1834 };
1835
1836 static struct clk_branch gcc_gfx_tbu_clk = {
1837         .halt_reg = 0x12010,
1838         .halt_check = BRANCH_VOTED,
1839         .clkr = {
1840                 .enable_reg = 0x4500C,
1841                 .enable_mask = BIT(3),
1842                 .hw.init = &(struct clk_init_data){
1843                         .name = "gcc_gfx_tbu_clk",
1844                         .ops = &clk_branch2_ops,
1845                 },
1846         },
1847 };
1848
1849 static struct clk_branch gcc_cdsp_tbu_clk = {
1850         .halt_reg = 0x1203c,
1851         .halt_check = BRANCH_VOTED,
1852         .clkr = {
1853                 .enable_reg = 0x13020,
1854                 .enable_mask = BIT(9),
1855                 .hw.init = &(struct clk_init_data) {
1856                         .name = "gcc_cdsp_tbu_clk",
1857                         .parent_names = (const char *[]) {
1858                                 "cdsp_bimc_clk_src",
1859                         },
1860                         .num_parents = 1,
1861                         .flags = CLK_SET_RATE_PARENT,
1862                         .ops = &clk_branch2_ops,
1863                 },
1864         },
1865 };
1866
1867 static struct clk_branch gcc_gp1_clk = {
1868         .halt_reg = 0x8000,
1869         .halt_check = BRANCH_HALT,
1870         .clkr = {
1871                 .enable_reg = 0x8000,
1872                 .enable_mask = BIT(0),
1873                 .hw.init = &(struct clk_init_data){
1874                         .name = "gcc_gp1_clk",
1875                         .parent_names = (const char *[]){
1876                                 "gp1_clk_src",
1877                         },
1878                         .num_parents = 1,
1879                         .flags = CLK_SET_RATE_PARENT,
1880                         .ops = &clk_branch2_ops,
1881                 },
1882         },
1883 };
1884
1885 static struct clk_branch gcc_gp2_clk = {
1886         .halt_reg = 0x9000,
1887         .halt_check = BRANCH_HALT,
1888         .clkr = {
1889                 .enable_reg = 0x9000,
1890                 .enable_mask = BIT(0),
1891                 .hw.init = &(struct clk_init_data){
1892                         .name = "gcc_gp2_clk",
1893                         .parent_names = (const char *[]){
1894                                 "gp2_clk_src",
1895                         },
1896                         .num_parents = 1,
1897                         .flags = CLK_SET_RATE_PARENT,
1898                         .ops = &clk_branch2_ops,
1899                 },
1900         },
1901 };
1902
1903 static struct clk_branch gcc_gp3_clk = {
1904         .halt_reg = 0xa000,
1905         .halt_check = BRANCH_HALT,
1906         .clkr = {
1907                 .enable_reg = 0xa000,
1908                 .enable_mask = BIT(0),
1909                 .hw.init = &(struct clk_init_data){
1910                         .name = "gcc_gp3_clk",
1911                         .parent_names = (const char *[]){
1912                                 "gp3_clk_src",
1913                         },
1914                         .num_parents = 1,
1915                         .flags = CLK_SET_RATE_PARENT,
1916                         .ops = &clk_branch2_ops,
1917                 },
1918         },
1919 };
1920
1921 static struct clk_branch gcc_gtcu_ahb_clk = {
1922         .halt_reg = 0x12044,
1923         .halt_check = BRANCH_VOTED,
1924         .clkr = {
1925                 .enable_reg = 0x4500c,
1926                 .enable_mask = BIT(13),
1927                 .hw.init = &(struct clk_init_data){
1928                         .name = "gcc_gtcu_ahb_clk",
1929                         .ops = &clk_branch2_ops,
1930                 },
1931         },
1932 };
1933
1934 static struct clk_branch gcc_mdp_tbu_clk = {
1935         .halt_reg = 0x1201c,
1936         .halt_check = BRANCH_VOTED,
1937         .clkr = {
1938                 .enable_reg = 0x4500c,
1939                 .enable_mask = BIT(4),
1940                 .hw.init = &(struct clk_init_data){
1941                         .name = "gcc_mdp_tbu_clk",
1942                         .ops = &clk_branch2_ops,
1943                 },
1944         },
1945 };
1946
1947 static struct clk_branch gcc_mdss_ahb_clk = {
1948         .halt_reg = 0x4d07c,
1949         .halt_check = BRANCH_HALT,
1950         .clkr = {
1951                 .enable_reg = 0x4d07c,
1952                 .enable_mask = BIT(0),
1953                 .hw.init = &(struct clk_init_data){
1954                         .name = "gcc_mdss_ahb_clk",
1955                         .ops = &clk_branch2_ops,
1956                 },
1957         },
1958 };
1959
1960 static struct clk_branch gcc_mdss_axi_clk = {
1961         .halt_reg = 0x4d080,
1962         .halt_check = BRANCH_HALT,
1963         .clkr = {
1964                 .enable_reg = 0x4d080,
1965                 .enable_mask = BIT(0),
1966                 .hw.init = &(struct clk_init_data){
1967                         .name = "gcc_mdss_axi_clk",
1968                         .ops = &clk_branch2_ops,
1969                 },
1970         },
1971 };
1972
1973 static struct clk_branch gcc_mdss_byte0_clk = {
1974         .halt_reg = 0x4d094,
1975         .halt_check = BRANCH_HALT,
1976         .clkr = {
1977                 .enable_reg = 0x4d094,
1978                 .enable_mask = BIT(0),
1979                 .hw.init = &(struct clk_init_data){
1980                         .name = "gcc_mdss_byte0_clk",
1981                         .parent_names = (const char *[]){
1982                                 "byte0_clk_src",
1983                         },
1984                         .num_parents = 1,
1985                         .flags = CLK_SET_RATE_PARENT,
1986                         .ops = &clk_branch2_ops,
1987                 },
1988         },
1989 };
1990
1991 static struct clk_branch gcc_mdss_esc0_clk = {
1992         .halt_reg = 0x4d098,
1993         .halt_check = BRANCH_HALT,
1994         .clkr = {
1995                 .enable_reg = 0x4d098,
1996                 .enable_mask = BIT(0),
1997                 .hw.init = &(struct clk_init_data){
1998                         .name = "gcc_mdss_esc0_clk",
1999                         .parent_names = (const char *[]){
2000                                 "esc0_clk_src",
2001                         },
2002                         .num_parents = 1,
2003                         .flags = CLK_SET_RATE_PARENT,
2004                         .ops = &clk_branch2_ops,
2005                 },
2006         },
2007 };
2008
2009 static struct clk_branch gcc_mdss_hdmi_app_clk = {
2010         .halt_reg = 0x4d0d8,
2011         .halt_check = BRANCH_HALT,
2012         .clkr = {
2013                 .enable_reg = 0x4d0d8,
2014                 .enable_mask = BIT(0),
2015                 .hw.init = &(struct clk_init_data){
2016                         .name = "gcc_mdss_hdmi_app_clk",
2017                         .parent_names = (const char *[]){
2018                                 "hdmi_app_clk_src",
2019                         },
2020                         .num_parents = 1,
2021                         .flags = CLK_SET_RATE_PARENT,
2022                         .ops = &clk_branch2_ops,
2023                 },
2024         },
2025 };
2026
2027 static struct clk_branch gcc_mdss_hdmi_pclk_clk = {
2028         .halt_reg = 0x4d0d4,
2029         .halt_check = BRANCH_HALT,
2030         .clkr = {
2031                 .enable_reg = 0x4d0d4,
2032                 .enable_mask = BIT(0),
2033                 .hw.init = &(struct clk_init_data){
2034                         .name = "gcc_mdss_hdmi_pclk_clk",
2035                         .parent_names = (const char *[]){
2036                                 "hdmi_pclk_clk_src",
2037                         },
2038                         .num_parents = 1,
2039                         .flags = CLK_SET_RATE_PARENT,
2040                         .ops = &clk_branch2_ops,
2041                 },
2042         },
2043 };
2044
2045 static struct clk_branch gcc_mdss_mdp_clk = {
2046         .halt_reg = 0x4d088,
2047         .halt_check = BRANCH_HALT,
2048         .clkr = {
2049                 .enable_reg = 0x4d088,
2050                 .enable_mask = BIT(0),
2051                 .hw.init = &(struct clk_init_data){
2052                         .name = "gcc_mdss_mdp_clk",
2053                         .parent_names = (const char *[]){
2054                                 "mdp_clk_src",
2055                         },
2056                         .num_parents = 1,
2057                         .flags = CLK_SET_RATE_PARENT,
2058                         .ops = &clk_branch2_ops,
2059                 },
2060         },
2061 };
2062
2063 static struct clk_branch gcc_mdss_pclk0_clk = {
2064         .halt_reg = 0x4d084,
2065         .halt_check = BRANCH_HALT,
2066         .clkr = {
2067                 .enable_reg = 0x4d084,
2068                 .enable_mask = BIT(0),
2069                 .hw.init = &(struct clk_init_data){
2070                         .name = "gcc_mdss_pclk0_clk",
2071                         .parent_names = (const char *[]){
2072                                 "pclk0_clk_src",
2073                         },
2074                         .num_parents = 1,
2075                         .flags = CLK_SET_RATE_PARENT,
2076                         .ops = &clk_branch2_ops,
2077                 },
2078         },
2079 };
2080
2081 static struct clk_branch gcc_mdss_vsync_clk = {
2082         .halt_reg = 0x4d090,
2083         .halt_check = BRANCH_HALT,
2084         .clkr = {
2085                 .enable_reg = 0x4d090,
2086                 .enable_mask = BIT(0),
2087                 .hw.init = &(struct clk_init_data){
2088                         .name = "gcc_mdss_vsync_clk",
2089                         .parent_names = (const char *[]){
2090                                 "vsync_clk_src",
2091                         },
2092                         .num_parents = 1,
2093                         .flags = CLK_SET_RATE_PARENT,
2094                         .ops = &clk_branch2_ops,
2095                 },
2096         },
2097 };
2098
2099 static struct clk_branch gcc_oxili_ahb_clk = {
2100         .halt_reg = 0x59028,
2101         .halt_check = BRANCH_HALT,
2102         .clkr = {
2103                 .enable_reg = 0x59028,
2104                 .enable_mask = BIT(0),
2105                 .hw.init = &(struct clk_init_data){
2106                         .name = "gcc_oxili_ahb_clk",
2107                         .ops = &clk_branch2_ops,
2108                 },
2109         },
2110 };
2111
2112 static struct clk_branch gcc_oxili_gfx3d_clk = {
2113         .halt_reg = 0x59020,
2114         .halt_check = BRANCH_HALT,
2115         .clkr = {
2116                 .enable_reg = 0x59020,
2117                 .enable_mask = BIT(0),
2118                 .hw.init = &(struct clk_init_data){
2119                         .name = "gcc_oxili_gfx3d_clk",
2120                         .parent_names = (const char *[]){
2121                                 "gfx3d_clk_src",
2122                         },
2123                         .num_parents = 1,
2124                         .flags = CLK_SET_RATE_PARENT,
2125                         .ops = &clk_branch2_ops,
2126                 },
2127         },
2128 };
2129
2130 static struct clk_branch gcc_pcie_0_aux_clk = {
2131         .halt_reg = 0x3e014,
2132         .halt_check = BRANCH_HALT_VOTED,
2133         .clkr = {
2134                 .enable_reg = 0x45004,
2135                 .enable_mask = BIT(27),
2136                 .hw.init = &(struct clk_init_data){
2137                         .name = "gcc_pcie_0_aux_clk",
2138                         .parent_names = (const char *[]){
2139                                 "pcie_0_aux_clk_src",
2140                         },
2141                         .num_parents = 1,
2142                         .flags = CLK_SET_RATE_PARENT,
2143                         .ops = &clk_branch2_ops,
2144                 },
2145         },
2146 };
2147
2148 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
2149         .halt_reg = 0x3e008,
2150         .halt_check = BRANCH_HALT_VOTED,
2151         .clkr = {
2152                 .enable_reg = 0x45004,
2153                 .enable_mask = BIT(11),
2154                 .hw.init = &(struct clk_init_data){
2155                         .name = "gcc_pcie_0_cfg_ahb_clk",
2156                         .ops = &clk_branch2_ops,
2157                 },
2158         },
2159 };
2160
2161 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
2162         .halt_reg = 0x3e018,
2163         .halt_check = BRANCH_HALT_VOTED,
2164         .clkr = {
2165                 .enable_reg = 0x45004,
2166                 .enable_mask = BIT(18),
2167                 .hw.init = &(struct clk_init_data){
2168                         .name = "gcc_pcie_0_mstr_axi_clk",
2169                         .ops = &clk_branch2_ops,
2170                 },
2171         },
2172 };
2173
2174 static struct clk_branch gcc_pcie_0_pipe_clk = {
2175         .halt_reg = 0x3e00c,
2176         .halt_check = BRANCH_HALT_VOTED,
2177         .clkr = {
2178                 .enable_reg = 0x45004,
2179                 .enable_mask = BIT(28),
2180                 .hw.init = &(struct clk_init_data){
2181                         .name = "gcc_pcie_0_pipe_clk",
2182                         .parent_names = (const char *[]){
2183                                 "pcie_0_pipe_clk_src",
2184                         },
2185                         .num_parents = 1,
2186                         .flags = CLK_SET_RATE_PARENT,
2187                         .ops = &clk_branch2_ops,
2188                 },
2189         },
2190 };
2191
2192 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
2193         .halt_reg = 0x3e010,
2194         .halt_check = BRANCH_HALT_VOTED,
2195         .clkr = {
2196                 .enable_reg = 0x45004,
2197                 .enable_mask = BIT(22),
2198                 .hw.init = &(struct clk_init_data){
2199                         .name = "gcc_pcie_0_slv_axi_clk",
2200                         .ops = &clk_branch2_ops,
2201                 },
2202         },
2203 };
2204
2205 static struct clk_branch gcc_pcnoc_usb2_clk = {
2206         .halt_reg = 0x27008,
2207         .halt_check = BRANCH_HALT,
2208         .clkr = {
2209                 .enable_reg = 0x27008,
2210                 .enable_mask = BIT(0),
2211                 .hw.init = &(struct clk_init_data){
2212                         .name = "gcc_pcnoc_usb2_clk",
2213                         .flags = CLK_IS_CRITICAL,
2214                         .ops = &clk_branch2_ops,
2215                 },
2216         },
2217 };
2218
2219 static struct clk_branch gcc_pcnoc_usb3_clk = {
2220         .halt_reg = 0x2700c,
2221         .halt_check = BRANCH_HALT,
2222         .clkr = {
2223                 .enable_reg = 0x2700c,
2224                 .enable_mask = BIT(0),
2225                 .hw.init = &(struct clk_init_data){
2226                         .name = "gcc_pcnoc_usb3_clk",
2227                         .flags = CLK_IS_CRITICAL,
2228                         .ops = &clk_branch2_ops,
2229                 },
2230         },
2231 };
2232
2233 static struct clk_branch gcc_pdm2_clk = {
2234         .halt_reg = 0x4400c,
2235         .halt_check = BRANCH_HALT,
2236         .clkr = {
2237                 .enable_reg = 0x4400c,
2238                 .enable_mask = BIT(0),
2239                 .hw.init = &(struct clk_init_data){
2240                         .name = "gcc_pdm2_clk",
2241                         .parent_names = (const char *[]){
2242                                 "pdm2_clk_src",
2243                         },
2244                         .num_parents = 1,
2245                         .flags = CLK_SET_RATE_PARENT,
2246                         .ops = &clk_branch2_ops,
2247                 },
2248         },
2249 };
2250
2251 static struct clk_branch gcc_pdm_ahb_clk = {
2252         .halt_reg = 0x44004,
2253         .halt_check = BRANCH_HALT,
2254         .clkr = {
2255                 .enable_reg = 0x44004,
2256                 .enable_mask = BIT(0),
2257                 .hw.init = &(struct clk_init_data){
2258                         .name = "gcc_pdm_ahb_clk",
2259                         .ops = &clk_branch2_ops,
2260                 },
2261         },
2262 };
2263
2264 static struct clk_branch gcc_prng_ahb_clk = {
2265         .halt_reg = 0x13004,
2266         .halt_check = BRANCH_HALT_VOTED,
2267         .clkr = {
2268                 .enable_reg = 0x45004,
2269                 .enable_mask = BIT(8),
2270                 .hw.init = &(struct clk_init_data){
2271                         .name = "gcc_prng_ahb_clk",
2272                         .ops = &clk_branch2_ops,
2273                 },
2274         },
2275 };
2276
2277 /* PWM clks do not have XO as parent as src clk is a balance root */
2278 static struct clk_branch gcc_pwm0_xo512_clk = {
2279         .halt_reg = 0x44018,
2280         .halt_check = BRANCH_HALT,
2281         .clkr = {
2282                 .enable_reg = 0x44018,
2283                 .enable_mask = BIT(0),
2284                 .hw.init = &(struct clk_init_data){
2285                         .name = "gcc_pwm0_xo512_clk",
2286                         .ops = &clk_branch2_ops,
2287                 },
2288         },
2289 };
2290
2291 static struct clk_branch gcc_pwm1_xo512_clk = {
2292         .halt_reg = 0x49004,
2293         .halt_check = BRANCH_HALT,
2294         .clkr = {
2295                 .enable_reg = 0x49004,
2296                 .enable_mask = BIT(0),
2297                 .hw.init = &(struct clk_init_data){
2298                         .name = "gcc_pwm1_xo512_clk",
2299                         .ops = &clk_branch2_ops,
2300                 },
2301         },
2302 };
2303
2304 static struct clk_branch gcc_pwm2_xo512_clk = {
2305         .halt_reg = 0x4a004,
2306         .halt_check = BRANCH_HALT,
2307         .clkr = {
2308                 .enable_reg = 0x4a004,
2309                 .enable_mask = BIT(0),
2310                 .hw.init = &(struct clk_init_data){
2311                         .name = "gcc_pwm2_xo512_clk",
2312                         .ops = &clk_branch2_ops,
2313                 },
2314         },
2315 };
2316
2317 static struct clk_branch gcc_qdss_dap_clk = {
2318         .halt_reg = 0x29084,
2319         .halt_check = BRANCH_VOTED,
2320         .clkr = {
2321                 .enable_reg = 0x45004,
2322                 .enable_mask = BIT(21),
2323                 .hw.init = &(struct clk_init_data){
2324                         .name = "gcc_qdss_dap_clk",
2325                         .ops = &clk_branch2_ops,
2326                 },
2327         },
2328 };
2329
2330 static struct clk_branch gcc_sdcc1_ahb_clk = {
2331         .halt_reg = 0x4201c,
2332         .halt_check = BRANCH_HALT,
2333         .clkr = {
2334                 .enable_reg = 0x4201c,
2335                 .enable_mask = BIT(0),
2336                 .hw.init = &(struct clk_init_data){
2337                         .name = "gcc_sdcc1_ahb_clk",
2338                         .ops = &clk_branch2_ops,
2339                 },
2340         },
2341 };
2342
2343 static struct clk_branch gcc_sdcc1_apps_clk = {
2344         .halt_reg = 0x42018,
2345         .halt_check = BRANCH_HALT,
2346         .clkr = {
2347                 .enable_reg = 0x42018,
2348                 .enable_mask = BIT(0),
2349                 .hw.init = &(struct clk_init_data){
2350                         .name = "gcc_sdcc1_apps_clk",
2351                         .parent_names = (const char *[]){
2352                                 "sdcc1_apps_clk_src",
2353                         },
2354                         .num_parents = 1,
2355                         .flags = CLK_SET_RATE_PARENT,
2356                         .ops = &clk_branch2_ops,
2357                 },
2358         },
2359 };
2360
2361 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2362         .halt_reg = 0x5d014,
2363         .halt_check = BRANCH_HALT,
2364         .clkr = {
2365                 .enable_reg = 0x5d014,
2366                 .enable_mask = BIT(0),
2367                 .hw.init = &(struct clk_init_data){
2368                         .name = "gcc_sdcc1_ice_core_clk",
2369                         .parent_names = (const char *[]){
2370                                 "sdcc1_ice_core_clk_src",
2371                         },
2372                         .num_parents = 1,
2373                         .flags = CLK_SET_RATE_PARENT,
2374                         .ops = &clk_branch2_ops,
2375                 },
2376         },
2377 };
2378
2379 static struct clk_branch gcc_cdsp_cfg_ahb_clk = {
2380         .halt_reg = 0x5e004,
2381         .halt_check = BRANCH_HALT,
2382         .clkr = {
2383                 .enable_reg = 0x5e004,
2384                 .enable_mask = BIT(0),
2385                 .hw.init = &(struct clk_init_data) {
2386                         .name = "gcc_cdsp_cfg_ahb_cbcr",
2387                         .ops = &clk_branch2_ops,
2388                 },
2389         },
2390 };
2391
2392 static struct clk_branch gcc_sdcc2_ahb_clk = {
2393         .halt_reg = 0x4301c,
2394         .halt_check = BRANCH_HALT,
2395         .clkr = {
2396                 .enable_reg = 0x4301c,
2397                 .enable_mask = BIT(0),
2398                 .hw.init = &(struct clk_init_data){
2399                         .name = "gcc_sdcc2_ahb_clk",
2400                         .ops = &clk_branch2_ops,
2401                 },
2402         },
2403 };
2404
2405 static struct clk_branch gcc_sdcc2_apps_clk = {
2406         .halt_reg = 0x43018,
2407         .halt_check = BRANCH_HALT,
2408         .clkr = {
2409                 .enable_reg = 0x43018,
2410                 .enable_mask = BIT(0),
2411                 .hw.init = &(struct clk_init_data){
2412                         .name = "gcc_sdcc2_apps_clk",
2413                         .parent_names = (const char *[]){
2414                                 "sdcc2_apps_clk_src",
2415                         },
2416                         .num_parents = 1,
2417                         .flags = CLK_SET_RATE_PARENT,
2418                         .ops = &clk_branch2_ops,
2419                 },
2420         },
2421 };
2422
2423 static struct clk_branch gcc_smmu_cfg_clk = {
2424         .halt_reg = 0x12038,
2425         .halt_check = BRANCH_VOTED,
2426         .clkr = {
2427                 .enable_reg = 0x3600C,
2428                 .enable_mask = BIT(12),
2429                 .hw.init = &(struct clk_init_data){
2430                         .name = "gcc_smmu_cfg_clk",
2431                         .ops = &clk_branch2_ops,
2432                 },
2433         },
2434 };
2435
2436 static struct clk_branch gcc_sys_noc_usb3_clk = {
2437         .halt_reg = 0x26014,
2438         .halt_check = BRANCH_HALT,
2439         .clkr = {
2440                 .enable_reg = 0x26014,
2441                 .enable_mask = BIT(0),
2442                 .hw.init = &(struct clk_init_data){
2443                         .name = "gcc_sys_noc_usb3_clk",
2444                         .parent_names = (const char *[]){
2445                                 "usb30_master_clk_src",
2446                         },
2447                         .num_parents = 1,
2448                         .ops = &clk_branch2_ops,
2449                 },
2450         },
2451 };
2452
2453 static struct clk_branch gcc_usb_hs_inactivity_timers_clk = {
2454         .halt_reg = 0x4100C,
2455         .halt_check = BRANCH_HALT,
2456         .clkr = {
2457                 .enable_reg = 0x4100C,
2458                 .enable_mask = BIT(0),
2459                 .hw.init = &(struct clk_init_data){
2460                         .name = "gcc_usb_hs_inactivity_timers_clk",
2461                         .ops = &clk_branch2_ops,
2462                 },
2463         },
2464 };
2465
2466 static struct clk_branch gcc_usb20_mock_utmi_clk = {
2467         .halt_reg = 0x41044,
2468         .halt_check = BRANCH_HALT,
2469         .clkr = {
2470                 .enable_reg = 0x41044,
2471                 .enable_mask = BIT(0),
2472                 .hw.init = &(struct clk_init_data){
2473                         .name = "gcc_usb20_mock_utmi_clk",
2474                         .parent_names = (const char *[]){
2475                                 "usb20_mock_utmi_clk_src",
2476                         },
2477                         .num_parents = 1,
2478                         .flags = CLK_SET_RATE_PARENT,
2479                         .ops = &clk_branch2_ops,
2480                 },
2481         },
2482 };
2483
2484 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
2485         .halt_reg = 0x4102c,
2486         .halt_check = BRANCH_HALT,
2487         .clkr = {
2488                 .enable_reg = 0x4102c,
2489                 .enable_mask = BIT(0),
2490                 .hw.init = &(struct clk_init_data){
2491                         .name = "gcc_usb2a_phy_sleep_clk",
2492                         .ops = &clk_branch2_ops,
2493                 },
2494         },
2495 };
2496
2497 static struct clk_branch gcc_usb30_master_clk = {
2498         .halt_reg = 0x3900c,
2499         .halt_check = BRANCH_HALT,
2500         .clkr = {
2501                 .enable_reg = 0x3900c,
2502                 .enable_mask = BIT(0),
2503                 .hw.init = &(struct clk_init_data){
2504                         .name = "gcc_usb30_master_clk",
2505                         .parent_names = (const char *[]){
2506                                 "usb30_master_clk_src",
2507                         },
2508                         .num_parents = 1,
2509                         .flags = CLK_SET_RATE_PARENT,
2510                         .ops = &clk_branch2_ops,
2511                 },
2512         },
2513 };
2514
2515 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2516         .halt_reg = 0x39014,
2517         .halt_check = BRANCH_HALT,
2518         .clkr = {
2519                 .enable_reg = 0x39014,
2520                 .enable_mask = BIT(0),
2521                 .hw.init = &(struct clk_init_data){
2522                         .name = "gcc_usb30_mock_utmi_clk",
2523                         .parent_names = (const char *[]){
2524                                 "usb30_mock_utmi_clk_src",
2525                         },
2526                         .num_parents = 1,
2527                         .flags = CLK_SET_RATE_PARENT,
2528                         .ops = &clk_branch2_ops,
2529                 },
2530         },
2531 };
2532
2533 static struct clk_branch gcc_usb30_sleep_clk = {
2534         .halt_reg = 0x39010,
2535         .halt_check = BRANCH_HALT,
2536         .clkr = {
2537                 .enable_reg = 0x39010,
2538                 .enable_mask = BIT(0),
2539                 .hw.init = &(struct clk_init_data){
2540                         .name = "gcc_usb30_sleep_clk",
2541                         .ops = &clk_branch2_ops,
2542                 },
2543         },
2544 };
2545
2546 static struct clk_branch gcc_usb3_phy_aux_clk = {
2547         .halt_reg = 0x39044,
2548         .halt_check = BRANCH_HALT,
2549         .clkr = {
2550                 .enable_reg = 0x39044,
2551                 .enable_mask = BIT(0),
2552                 .hw.init = &(struct clk_init_data){
2553                         .name = "gcc_usb3_phy_aux_clk",
2554                         .parent_names = (const char *[]){
2555                                 "usb3_phy_aux_clk_src",
2556                         },
2557                         .num_parents = 1,
2558                         .flags = CLK_SET_RATE_PARENT,
2559                         .ops = &clk_branch2_ops,
2560                 },
2561         },
2562 };
2563
2564 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2565         .halt_check = BRANCH_HALT_SKIP,
2566         .clkr = {
2567                 .enable_reg = 0x39018,
2568                 .enable_mask = BIT(0),
2569                 .hw.init = &(struct clk_init_data){
2570                         .name = "gcc_usb3_phy_pipe_clk",
2571                         .ops = &clk_branch2_ops,
2572                 },
2573         },
2574 };
2575
2576 static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
2577         .halt_reg = 0x41030,
2578         .halt_check = BRANCH_HALT,
2579         .clkr = {
2580                 .enable_reg = 0x41030,
2581                 .enable_mask = BIT(0),
2582                 .hw.init = &(struct clk_init_data){
2583                         .name = "gcc_usb_hs_phy_cfg_ahb_clk",
2584                         .ops = &clk_branch2_ops,
2585                 },
2586         },
2587 };
2588
2589 static struct clk_branch gcc_usb_hs_system_clk = {
2590         .halt_reg = 0x41004,
2591         .halt_check = BRANCH_HALT,
2592         .clkr = {
2593                 .enable_reg = 0x41004,
2594                 .enable_mask = BIT(0),
2595                 .hw.init = &(struct clk_init_data){
2596                         .name = "gcc_usb_hs_system_clk",
2597                         .parent_names = (const char *[]){
2598                                 "usb_hs_system_clk_src",
2599                         },
2600                         .num_parents = 1,
2601                         .flags = CLK_SET_RATE_PARENT,
2602                         .ops = &clk_branch2_ops,
2603                 },
2604         },
2605 };
2606
2607 static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = {
2608         .halt_reg = 0x1e004,
2609         .halt_check = BRANCH_HALT,
2610         .clkr = {
2611                 .enable_reg = 0x1e004,
2612                 .enable_mask = BIT(0),
2613                 .hw.init = &(struct clk_init_data){
2614                         .name = "gcc_wdsp_q6ss_ahbs_clk",
2615                         .ops = &clk_branch2_ops,
2616                 },
2617         },
2618 };
2619
2620 static struct clk_branch gcc_wdsp_q6ss_axim_clk = {
2621         .halt_reg = 0x1e008,
2622         .halt_check = BRANCH_HALT,
2623         .clkr = {
2624                 .enable_reg = 0x1e008,
2625                 .enable_mask = BIT(0),
2626                 .hw.init = &(struct clk_init_data){
2627                         .name = "gcc_wdsp_q6ss_axim_clk",
2628                         .ops = &clk_branch2_ops,
2629                 },
2630         },
2631 };
2632
2633 static struct clk_hw *gcc_qcs404_hws[] = {
2634         &cxo.hw,
2635 };
2636
2637 static struct clk_regmap *gcc_qcs404_clocks[] = {
2638         [GCC_APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
2639         [GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC] = &blsp1_qup0_i2c_apps_clk_src.clkr,
2640         [GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC] = &blsp1_qup0_spi_apps_clk_src.clkr,
2641         [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2642         [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2643         [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2644         [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2645         [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2646         [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2647         [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2648         [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2649         [GCC_BLSP1_UART0_APPS_CLK_SRC] = &blsp1_uart0_apps_clk_src.clkr,
2650         [GCC_BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2651         [GCC_BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2652         [GCC_BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2653         [GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC] = &blsp2_qup0_i2c_apps_clk_src.clkr,
2654         [GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC] = &blsp2_qup0_spi_apps_clk_src.clkr,
2655         [GCC_BLSP2_UART0_APPS_CLK_SRC] = &blsp2_uart0_apps_clk_src.clkr,
2656         [GCC_BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2657         [GCC_EMAC_CLK_SRC] = &emac_clk_src.clkr,
2658         [GCC_EMAC_PTP_CLK_SRC] = &emac_ptp_clk_src.clkr,
2659         [GCC_ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2660         [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
2661         [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
2662         [GCC_BIMC_CDSP_CLK] = &gcc_bimc_cdsp_clk.clkr,
2663         [GCC_BIMC_MDSS_CLK] = &gcc_bimc_mdss_clk.clkr,
2664         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2665         [GCC_BLSP1_QUP0_I2C_APPS_CLK] = &gcc_blsp1_qup0_i2c_apps_clk.clkr,
2666         [GCC_BLSP1_QUP0_SPI_APPS_CLK] = &gcc_blsp1_qup0_spi_apps_clk.clkr,
2667         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2668         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2669         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2670         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2671         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2672         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2673         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2674         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2675         [GCC_BLSP1_UART0_APPS_CLK] = &gcc_blsp1_uart0_apps_clk.clkr,
2676         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2677         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2678         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2679         [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2680         [GCC_BLSP2_QUP0_I2C_APPS_CLK] = &gcc_blsp2_qup0_i2c_apps_clk.clkr,
2681         [GCC_BLSP2_QUP0_SPI_APPS_CLK] = &gcc_blsp2_qup0_spi_apps_clk.clkr,
2682         [GCC_BLSP2_UART0_APPS_CLK] = &gcc_blsp2_uart0_apps_clk.clkr,
2683         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2684         [GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr,
2685         [GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr,
2686         [GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr,
2687         [GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr,
2688         [GCC_GENI_IR_S_CLK] = &gcc_geni_ir_s_clk.clkr,
2689         [GCC_GENI_IR_H_CLK] = &gcc_geni_ir_h_clk.clkr,
2690         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2691         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2692         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2693         [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr,
2694         [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr,
2695         [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr,
2696         [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr,
2697         [GCC_MDSS_HDMI_APP_CLK] = &gcc_mdss_hdmi_app_clk.clkr,
2698         [GCC_MDSS_HDMI_PCLK_CLK] = &gcc_mdss_hdmi_pclk_clk.clkr,
2699         [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr,
2700         [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr,
2701         [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr,
2702         [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr,
2703         [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr,
2704         [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2705         [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2706         [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2707         [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2708         [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2709         [GCC_PCNOC_USB2_CLK] = &gcc_pcnoc_usb2_clk.clkr,
2710         [GCC_PCNOC_USB3_CLK] = &gcc_pcnoc_usb3_clk.clkr,
2711         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2712         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2713         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2714         [GCC_PWM0_XO512_CLK] = &gcc_pwm0_xo512_clk.clkr,
2715         [GCC_PWM1_XO512_CLK] = &gcc_pwm1_xo512_clk.clkr,
2716         [GCC_PWM2_XO512_CLK] = &gcc_pwm2_xo512_clk.clkr,
2717         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2718         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2719         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
2720         [GCC_CDSP_CFG_AHB_CLK] = &gcc_cdsp_cfg_ahb_clk.clkr,
2721         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2722         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2723         [GCC_SYS_NOC_USB3_CLK] = &gcc_sys_noc_usb3_clk.clkr,
2724         [GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,
2725         [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
2726         [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2727         [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2728         [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2729         [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2730         [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2731         [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
2732         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2733         [GCC_GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr,
2734         [GCC_GP1_CLK_SRC] = &gp1_clk_src.clkr,
2735         [GCC_GP2_CLK_SRC] = &gp2_clk_src.clkr,
2736         [GCC_GP3_CLK_SRC] = &gp3_clk_src.clkr,
2737         [GCC_GPLL0_OUT_MAIN] = &gpll0_out_main.clkr,
2738         [GCC_GPLL0_AO_OUT_MAIN] = &gpll0_ao_out_main.clkr,
2739         [GCC_GPLL0_SLEEP_CLK_SRC] = &gpll0_sleep_clk_src.clkr,
2740         [GCC_GPLL1_OUT_MAIN] = &gpll1_out_main.clkr,
2741         [GCC_GPLL3_OUT_MAIN] = &gpll3_out_main.clkr,
2742         [GCC_GPLL4_OUT_MAIN] = &gpll4_out_main.clkr,
2743         [GCC_GPLL6] = &gpll6.clkr,
2744         [GCC_GPLL6_OUT_AUX] = &gpll6_out_aux,
2745         [GCC_HDMI_APP_CLK_SRC] = &hdmi_app_clk_src.clkr,
2746         [GCC_HDMI_PCLK_CLK_SRC] = &hdmi_pclk_clk_src.clkr,
2747         [GCC_MDP_CLK_SRC] = &mdp_clk_src.clkr,
2748         [GCC_PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2749         [GCC_PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2750         [GCC_PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2751         [GCC_PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2752         [GCC_SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2753         [GCC_SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
2754         [GCC_SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2755         [GCC_USB20_MOCK_UTMI_CLK_SRC] = &usb20_mock_utmi_clk_src.clkr,
2756         [GCC_USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2757         [GCC_USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2758         [GCC_USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2759         [GCC_USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2760         [GCC_VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2761         [GCC_CDSP_BIMC_CLK_SRC] = &cdsp_bimc_clk_src.clkr,
2762         [GCC_USB_HS_INACTIVITY_TIMERS_CLK] =
2763                         &gcc_usb_hs_inactivity_timers_clk.clkr,
2764         [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
2765         [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr,
2766         [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
2767         [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr,
2768         [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
2769         [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
2770         [GCC_CDSP_TBU_CLK] = &gcc_cdsp_tbu_clk.clkr,
2771         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
2772         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
2773         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
2774         [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr,
2775         [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
2776         [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
2777         [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr,
2778         [GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr,
2779         [GCC_WCSS_Q6_AXIM_CLK] =  &gcc_wdsp_q6ss_axim_clk.clkr,
2780
2781 };
2782
2783 static const struct qcom_reset_map gcc_qcs404_resets[] = {
2784         [GCC_GENI_IR_BCR] = { 0x0F000 },
2785         [GCC_CDSP_RESTART] = { 0x18000 },
2786         [GCC_USB_HS_BCR] = { 0x41000 },
2787         [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
2788         [GCC_QUSB2_PHY_BCR] = { 0x4103c },
2789         [GCC_USB_HS_PHY_CFG_AHB_BCR] = { 0x0000c, 1 },
2790         [GCC_USB2A_PHY_BCR] = { 0x0000c, 0 },
2791         [GCC_USB3_PHY_BCR] = { 0x39004 },
2792         [GCC_USB_30_BCR] = { 0x39000 },
2793         [GCC_USB3PHY_PHY_BCR] = { 0x39008 },
2794         [GCC_PCIE_0_BCR] = { 0x3e000 },
2795         [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
2796         [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 },
2797         [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c },
2798         [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6},
2799         [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 },
2800         [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 },
2801         [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 },
2802         [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 },
2803         [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 },
2804         [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 },
2805         [GCC_EMAC_BCR] = { 0x4e000 },
2806         [GCC_WDSP_RESTART] = {0x19000},
2807 };
2808
2809 static const struct regmap_config gcc_qcs404_regmap_config = {
2810         .reg_bits       = 32,
2811         .reg_stride     = 4,
2812         .val_bits       = 32,
2813         .max_register   = 0x7f000,
2814         .fast_io        = true,
2815 };
2816
2817 static const struct qcom_cc_desc gcc_qcs404_desc = {
2818         .config = &gcc_qcs404_regmap_config,
2819         .clks = gcc_qcs404_clocks,
2820         .num_clks = ARRAY_SIZE(gcc_qcs404_clocks),
2821         .resets = gcc_qcs404_resets,
2822         .num_resets = ARRAY_SIZE(gcc_qcs404_resets),
2823         .clk_hws = gcc_qcs404_hws,
2824         .num_clk_hws = ARRAY_SIZE(gcc_qcs404_hws),
2825 };
2826
2827 static const struct of_device_id gcc_qcs404_match_table[] = {
2828         { .compatible = "qcom,gcc-qcs404" },
2829         { }
2830 };
2831 MODULE_DEVICE_TABLE(of, gcc_qcs404_match_table);
2832
2833 static int gcc_qcs404_probe(struct platform_device *pdev)
2834 {
2835         struct regmap *regmap;
2836
2837         regmap = qcom_cc_map(pdev, &gcc_qcs404_desc);
2838         if (IS_ERR(regmap))
2839                 return PTR_ERR(regmap);
2840
2841         clk_alpha_pll_configure(&gpll3_out_main, regmap, &gpll3_config);
2842
2843         return qcom_cc_really_probe(pdev, &gcc_qcs404_desc, regmap);
2844 }
2845
2846 static struct platform_driver gcc_qcs404_driver = {
2847         .probe = gcc_qcs404_probe,
2848         .driver = {
2849                 .name = "gcc-qcs404",
2850                 .of_match_table = gcc_qcs404_match_table,
2851         },
2852 };
2853
2854 static int __init gcc_qcs404_init(void)
2855 {
2856         return platform_driver_register(&gcc_qcs404_driver);
2857 }
2858 subsys_initcall(gcc_qcs404_init);
2859
2860 static void __exit gcc_qcs404_exit(void)
2861 {
2862         platform_driver_unregister(&gcc_qcs404_driver);
2863 }
2864 module_exit(gcc_qcs404_exit);
2865
2866 MODULE_DESCRIPTION("Qualcomm GCC QCS404 Driver");
2867 MODULE_LICENSE("GPL v2");