drivers/clk/qcom/gcc-msm8960.c

   1 /*
   2  * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/bitops.h>
  16 #include <linux/err.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include <linux/reset-controller.h>
  24
  25 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
  26 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
  27
  28 #include "common.h"
  29 #include "clk-regmap.h"
  30 #include "clk-pll.h"
  31 #include "clk-rcg.h"
  32 #include "clk-branch.h"
  33 #include "reset.h"
  34
  35 static struct clk_pll pll3 = {
  36         .l_reg = 0x3164,
  37         .m_reg = 0x3168,
  38         .n_reg = 0x316c,
  39         .config_reg = 0x3174,
  40         .mode_reg = 0x3160,
  41         .status_reg = 0x3178,
  42         .status_bit = 16,
  43         .clkr.hw.init = &(struct clk_init_data){
  44                 .name = "pll3",
  45                 .parent_names = (const char *[]){ "pxo" },
  46                 .num_parents = 1,
  47                 .ops = &clk_pll_ops,
  48         },
  49 };
  50
  51 static struct clk_regmap pll4_vote = {
  52         .enable_reg = 0x34c0,
  53         .enable_mask = BIT(4),
  54         .hw.init = &(struct clk_init_data){
  55                 .name = "pll4_vote",
  56                 .parent_names = (const char *[]){ "pll4" },
  57                 .num_parents = 1,
  58                 .ops = &clk_pll_vote_ops,
  59         },
  60 };
  61
  62 static struct clk_pll pll8 = {
  63         .l_reg = 0x3144,
  64         .m_reg = 0x3148,
  65         .n_reg = 0x314c,
  66         .config_reg = 0x3154,
  67         .mode_reg = 0x3140,
  68         .status_reg = 0x3158,
  69         .status_bit = 16,
  70         .clkr.hw.init = &(struct clk_init_data){
  71                 .name = "pll8",
  72                 .parent_names = (const char *[]){ "pxo" },
  73                 .num_parents = 1,
  74                 .ops = &clk_pll_ops,
  75         },
  76 };
  77
  78 static struct clk_regmap pll8_vote = {
  79         .enable_reg = 0x34c0,
  80         .enable_mask = BIT(8),
  81         .hw.init = &(struct clk_init_data){
  82                 .name = "pll8_vote",
  83                 .parent_names = (const char *[]){ "pll8" },
  84                 .num_parents = 1,
  85                 .ops = &clk_pll_vote_ops,
  86         },
  87 };
  88
  89 static struct clk_pll pll14 = {
  90         .l_reg = 0x31c4,
  91         .m_reg = 0x31c8,
  92         .n_reg = 0x31cc,
  93         .config_reg = 0x31d4,
  94         .mode_reg = 0x31c0,
  95         .status_reg = 0x31d8,
  96         .status_bit = 16,
  97         .clkr.hw.init = &(struct clk_init_data){
  98                 .name = "pll14",
  99                 .parent_names = (const char *[]){ "pxo" },
 100                 .num_parents = 1,
 101                 .ops = &clk_pll_ops,
 102         },
 103 };
 104
 105 static struct clk_regmap pll14_vote = {
 106         .enable_reg = 0x34c0,
 107         .enable_mask = BIT(14),
 108         .hw.init = &(struct clk_init_data){
 109                 .name = "pll14_vote",
 110                 .parent_names = (const char *[]){ "pll14" },
 111                 .num_parents = 1,
 112                 .ops = &clk_pll_vote_ops,
 113         },
 114 };
 115
 116 enum {
 117         P_PXO,
 118         P_PLL8,
 119         P_PLL3,
 120         P_CXO,
 121 };
 122
 123 static const struct parent_map gcc_pxo_pll8_map[] = {
 124         { P_PXO, 0 },
 125         { P_PLL8, 3 }
 126 };
 127
 128 static const char * const gcc_pxo_pll8[] = {
 129         "pxo",
 130         "pll8_vote",
 131 };
 132
 133 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
 134         { P_PXO, 0 },
 135         { P_PLL8, 3 },
 136         { P_CXO, 5 }
 137 };
 138
 139 static const char * const gcc_pxo_pll8_cxo[] = {
 140         "pxo",
 141         "pll8_vote",
 142         "cxo",
 143 };
 144
 145 static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
 146         { P_PXO, 0 },
 147         { P_PLL8, 3 },
 148         { P_PLL3, 6 }
 149 };
 150
 151 static const char * const gcc_pxo_pll8_pll3[] = {
 152         "pxo",
 153         "pll8_vote",
 154         "pll3",
 155 };
 156
 157 static struct freq_tbl clk_tbl_gsbi_uart[] = {
 158         {  1843200, P_PLL8, 2,  6, 625 },
 159         {  3686400, P_PLL8, 2, 12, 625 },
 160         {  7372800, P_PLL8, 2, 24, 625 },
 161         { 14745600, P_PLL8, 2, 48, 625 },
 162         { 16000000, P_PLL8, 4,  1,   6 },
 163         { 24000000, P_PLL8, 4,  1,   4 },
 164         { 32000000, P_PLL8, 4,  1,   3 },
 165         { 40000000, P_PLL8, 1,  5,  48 },
 166         { 46400000, P_PLL8, 1, 29, 240 },
 167         { 48000000, P_PLL8, 4,  1,   2 },
 168         { 51200000, P_PLL8, 1,  2,  15 },
 169         { 56000000, P_PLL8, 1,  7,  48 },
 170         { 58982400, P_PLL8, 1, 96, 625 },
 171         { 64000000, P_PLL8, 2,  1,   3 },
 172         { }
 173 };
 174
 175 static struct clk_rcg gsbi1_uart_src = {
 176         .ns_reg = 0x29d4,
 177         .md_reg = 0x29d0,
 178         .mn = {
 179                 .mnctr_en_bit = 8,
 180                 .mnctr_reset_bit = 7,
 181                 .mnctr_mode_shift = 5,
 182                 .n_val_shift = 16,
 183                 .m_val_shift = 16,
 184                 .width = 16,
 185         },
 186         .p = {
 187                 .pre_div_shift = 3,
 188                 .pre_div_width = 2,
 189         },
 190         .s = {
 191                 .src_sel_shift = 0,
 192                 .parent_map = gcc_pxo_pll8_map,
 193         },
 194         .freq_tbl = clk_tbl_gsbi_uart,
 195         .clkr = {
 196                 .enable_reg = 0x29d4,
 197                 .enable_mask = BIT(11),
 198                 .hw.init = &(struct clk_init_data){
 199                         .name = "gsbi1_uart_src",
 200                         .parent_names = gcc_pxo_pll8,
 201                         .num_parents = 2,
 202                         .ops = &clk_rcg_ops,
 203                         .flags = CLK_SET_PARENT_GATE,
 204                 },
 205         },
 206 };
 207
 208 static struct clk_branch gsbi1_uart_clk = {
 209         .halt_reg = 0x2fcc,
 210         .halt_bit = 10,
 211         .clkr = {
 212                 .enable_reg = 0x29d4,
 213                 .enable_mask = BIT(9),
 214                 .hw.init = &(struct clk_init_data){
 215                         .name = "gsbi1_uart_clk",
 216                         .parent_names = (const char *[]){
 217                                 "gsbi1_uart_src",
 218                         },
 219                         .num_parents = 1,
 220                         .ops = &clk_branch_ops,
 221                         .flags = CLK_SET_RATE_PARENT,
 222                 },
 223         },
 224 };
 225
 226 static struct clk_rcg gsbi2_uart_src = {
 227         .ns_reg = 0x29f4,
 228         .md_reg = 0x29f0,
 229         .mn = {
 230                 .mnctr_en_bit = 8,
 231                 .mnctr_reset_bit = 7,
 232                 .mnctr_mode_shift = 5,
 233                 .n_val_shift = 16,
 234                 .m_val_shift = 16,
 235                 .width = 16,
 236         },
 237         .p = {
 238                 .pre_div_shift = 3,
 239                 .pre_div_width = 2,
 240         },
 241         .s = {
 242                 .src_sel_shift = 0,
 243                 .parent_map = gcc_pxo_pll8_map,
 244         },
 245         .freq_tbl = clk_tbl_gsbi_uart,
 246         .clkr = {
 247                 .enable_reg = 0x29f4,
 248                 .enable_mask = BIT(11),
 249                 .hw.init = &(struct clk_init_data){
 250                         .name = "gsbi2_uart_src",
 251                         .parent_names = gcc_pxo_pll8,
 252                         .num_parents = 2,
 253                         .ops = &clk_rcg_ops,
 254                         .flags = CLK_SET_PARENT_GATE,
 255                 },
 256         },
 257 };
 258
 259 static struct clk_branch gsbi2_uart_clk = {
 260         .halt_reg = 0x2fcc,
 261         .halt_bit = 6,
 262         .clkr = {
 263                 .enable_reg = 0x29f4,
 264                 .enable_mask = BIT(9),
 265                 .hw.init = &(struct clk_init_data){
 266                         .name = "gsbi2_uart_clk",
 267                         .parent_names = (const char *[]){
 268                                 "gsbi2_uart_src",
 269                         },
 270                         .num_parents = 1,
 271                         .ops = &clk_branch_ops,
 272                         .flags = CLK_SET_RATE_PARENT,
 273                 },
 274         },
 275 };
 276
 277 static struct clk_rcg gsbi3_uart_src = {
 278         .ns_reg = 0x2a14,
 279         .md_reg = 0x2a10,
 280         .mn = {
 281                 .mnctr_en_bit = 8,
 282                 .mnctr_reset_bit = 7,
 283                 .mnctr_mode_shift = 5,
 284                 .n_val_shift = 16,
 285                 .m_val_shift = 16,
 286                 .width = 16,
 287         },
 288         .p = {
 289                 .pre_div_shift = 3,
 290                 .pre_div_width = 2,
 291         },
 292         .s = {
 293                 .src_sel_shift = 0,
 294                 .parent_map = gcc_pxo_pll8_map,
 295         },
 296         .freq_tbl = clk_tbl_gsbi_uart,
 297         .clkr = {
 298                 .enable_reg = 0x2a14,
 299                 .enable_mask = BIT(11),
 300                 .hw.init = &(struct clk_init_data){
 301                         .name = "gsbi3_uart_src",
 302                         .parent_names = gcc_pxo_pll8,
 303                         .num_parents = 2,
 304                         .ops = &clk_rcg_ops,
 305                         .flags = CLK_SET_PARENT_GATE,
 306                 },
 307         },
 308 };
 309
 310 static struct clk_branch gsbi3_uart_clk = {
 311         .halt_reg = 0x2fcc,
 312         .halt_bit = 2,
 313         .clkr = {
 314                 .enable_reg = 0x2a14,
 315                 .enable_mask = BIT(9),
 316                 .hw.init = &(struct clk_init_data){
 317                         .name = "gsbi3_uart_clk",
 318                         .parent_names = (const char *[]){
 319                                 "gsbi3_uart_src",
 320                         },
 321                         .num_parents = 1,
 322                         .ops = &clk_branch_ops,
 323                         .flags = CLK_SET_RATE_PARENT,
 324                 },
 325         },
 326 };
 327
 328 static struct clk_rcg gsbi4_uart_src = {
 329         .ns_reg = 0x2a34,
 330         .md_reg = 0x2a30,
 331         .mn = {
 332                 .mnctr_en_bit = 8,
 333                 .mnctr_reset_bit = 7,
 334                 .mnctr_mode_shift = 5,
 335                 .n_val_shift = 16,
 336                 .m_val_shift = 16,
 337                 .width = 16,
 338         },
 339         .p = {
 340                 .pre_div_shift = 3,
 341                 .pre_div_width = 2,
 342         },
 343         .s = {
 344                 .src_sel_shift = 0,
 345                 .parent_map = gcc_pxo_pll8_map,
 346         },
 347         .freq_tbl = clk_tbl_gsbi_uart,
 348         .clkr = {
 349                 .enable_reg = 0x2a34,
 350                 .enable_mask = BIT(11),
 351                 .hw.init = &(struct clk_init_data){
 352                         .name = "gsbi4_uart_src",
 353                         .parent_names = gcc_pxo_pll8,
 354                         .num_parents = 2,
 355                         .ops = &clk_rcg_ops,
 356                         .flags = CLK_SET_PARENT_GATE,
 357                 },
 358         },
 359 };
 360
 361 static struct clk_branch gsbi4_uart_clk = {
 362         .halt_reg = 0x2fd0,
 363         .halt_bit = 26,
 364         .clkr = {
 365                 .enable_reg = 0x2a34,
 366                 .enable_mask = BIT(9),
 367                 .hw.init = &(struct clk_init_data){
 368                         .name = "gsbi4_uart_clk",
 369                         .parent_names = (const char *[]){
 370                                 "gsbi4_uart_src",
 371                         },
 372                         .num_parents = 1,
 373                         .ops = &clk_branch_ops,
 374                         .flags = CLK_SET_RATE_PARENT,
 375                 },
 376         },
 377 };
 378
 379 static struct clk_rcg gsbi5_uart_src = {
 380         .ns_reg = 0x2a54,
 381         .md_reg = 0x2a50,
 382         .mn = {
 383                 .mnctr_en_bit = 8,
 384                 .mnctr_reset_bit = 7,
 385                 .mnctr_mode_shift = 5,
 386                 .n_val_shift = 16,
 387                 .m_val_shift = 16,
 388                 .width = 16,
 389         },
 390         .p = {
 391                 .pre_div_shift = 3,
 392                 .pre_div_width = 2,
 393         },
 394         .s = {
 395                 .src_sel_shift = 0,
 396                 .parent_map = gcc_pxo_pll8_map,
 397         },
 398         .freq_tbl = clk_tbl_gsbi_uart,
 399         .clkr = {
 400                 .enable_reg = 0x2a54,
 401                 .enable_mask = BIT(11),
 402                 .hw.init = &(struct clk_init_data){
 403                         .name = "gsbi5_uart_src",
 404                         .parent_names = gcc_pxo_pll8,
 405                         .num_parents = 2,
 406                         .ops = &clk_rcg_ops,
 407                         .flags = CLK_SET_PARENT_GATE,
 408                 },
 409         },
 410 };
 411
 412 static struct clk_branch gsbi5_uart_clk = {
 413         .halt_reg = 0x2fd0,
 414         .halt_bit = 22,
 415         .clkr = {
 416                 .enable_reg = 0x2a54,
 417                 .enable_mask = BIT(9),
 418                 .hw.init = &(struct clk_init_data){
 419                         .name = "gsbi5_uart_clk",
 420                         .parent_names = (const char *[]){
 421                                 "gsbi5_uart_src",
 422                         },
 423                         .num_parents = 1,
 424                         .ops = &clk_branch_ops,
 425                         .flags = CLK_SET_RATE_PARENT,
 426                 },
 427         },
 428 };
 429
 430 static struct clk_rcg gsbi6_uart_src = {
 431         .ns_reg = 0x2a74,
 432         .md_reg = 0x2a70,
 433         .mn = {
 434                 .mnctr_en_bit = 8,
 435                 .mnctr_reset_bit = 7,
 436                 .mnctr_mode_shift = 5,
 437                 .n_val_shift = 16,
 438                 .m_val_shift = 16,
 439                 .width = 16,
 440         },
 441         .p = {
 442                 .pre_div_shift = 3,
 443                 .pre_div_width = 2,
 444         },
 445         .s = {
 446                 .src_sel_shift = 0,
 447                 .parent_map = gcc_pxo_pll8_map,
 448         },
 449         .freq_tbl = clk_tbl_gsbi_uart,
 450         .clkr = {
 451                 .enable_reg = 0x2a74,
 452                 .enable_mask = BIT(11),
 453                 .hw.init = &(struct clk_init_data){
 454                         .name = "gsbi6_uart_src",
 455                         .parent_names = gcc_pxo_pll8,
 456                         .num_parents = 2,
 457                         .ops = &clk_rcg_ops,
 458                         .flags = CLK_SET_PARENT_GATE,
 459                 },
 460         },
 461 };
 462
 463 static struct clk_branch gsbi6_uart_clk = {
 464         .halt_reg = 0x2fd0,
 465         .halt_bit = 18,
 466         .clkr = {
 467                 .enable_reg = 0x2a74,
 468                 .enable_mask = BIT(9),
 469                 .hw.init = &(struct clk_init_data){
 470                         .name = "gsbi6_uart_clk",
 471                         .parent_names = (const char *[]){
 472                                 "gsbi6_uart_src",
 473                         },
 474                         .num_parents = 1,
 475                         .ops = &clk_branch_ops,
 476                         .flags = CLK_SET_RATE_PARENT,
 477                 },
 478         },
 479 };
 480
 481 static struct clk_rcg gsbi7_uart_src = {
 482         .ns_reg = 0x2a94,
 483         .md_reg = 0x2a90,
 484         .mn = {
 485                 .mnctr_en_bit = 8,
 486                 .mnctr_reset_bit = 7,
 487                 .mnctr_mode_shift = 5,
 488                 .n_val_shift = 16,
 489                 .m_val_shift = 16,
 490                 .width = 16,
 491         },
 492         .p = {
 493                 .pre_div_shift = 3,
 494                 .pre_div_width = 2,
 495         },
 496         .s = {
 497                 .src_sel_shift = 0,
 498                 .parent_map = gcc_pxo_pll8_map,
 499         },
 500         .freq_tbl = clk_tbl_gsbi_uart,
 501         .clkr = {
 502                 .enable_reg = 0x2a94,
 503                 .enable_mask = BIT(11),
 504                 .hw.init = &(struct clk_init_data){
 505                         .name = "gsbi7_uart_src",
 506                         .parent_names = gcc_pxo_pll8,
 507                         .num_parents = 2,
 508                         .ops = &clk_rcg_ops,
 509                         .flags = CLK_SET_PARENT_GATE,
 510                 },
 511         },
 512 };
 513
 514 static struct clk_branch gsbi7_uart_clk = {
 515         .halt_reg = 0x2fd0,
 516         .halt_bit = 14,
 517         .clkr = {
 518                 .enable_reg = 0x2a94,
 519                 .enable_mask = BIT(9),
 520                 .hw.init = &(struct clk_init_data){
 521                         .name = "gsbi7_uart_clk",
 522                         .parent_names = (const char *[]){
 523                                 "gsbi7_uart_src",
 524                         },
 525                         .num_parents = 1,
 526                         .ops = &clk_branch_ops,
 527                         .flags = CLK_SET_RATE_PARENT,
 528                 },
 529         },
 530 };
 531
 532 static struct clk_rcg gsbi8_uart_src = {
 533         .ns_reg = 0x2ab4,
 534         .md_reg = 0x2ab0,
 535         .mn = {
 536                 .mnctr_en_bit = 8,
 537                 .mnctr_reset_bit = 7,
 538                 .mnctr_mode_shift = 5,
 539                 .n_val_shift = 16,
 540                 .m_val_shift = 16,
 541                 .width = 16,
 542         },
 543         .p = {
 544                 .pre_div_shift = 3,
 545                 .pre_div_width = 2,
 546         },
 547         .s = {
 548                 .src_sel_shift = 0,
 549                 .parent_map = gcc_pxo_pll8_map,
 550         },
 551         .freq_tbl = clk_tbl_gsbi_uart,
 552         .clkr = {
 553                 .enable_reg = 0x2ab4,
 554                 .enable_mask = BIT(11),
 555                 .hw.init = &(struct clk_init_data){
 556                         .name = "gsbi8_uart_src",
 557                         .parent_names = gcc_pxo_pll8,
 558                         .num_parents = 2,
 559                         .ops = &clk_rcg_ops,
 560                         .flags = CLK_SET_PARENT_GATE,
 561                 },
 562         },
 563 };
 564
 565 static struct clk_branch gsbi8_uart_clk = {
 566         .halt_reg = 0x2fd0,
 567         .halt_bit = 10,
 568         .clkr = {
 569                 .enable_reg = 0x2ab4,
 570                 .enable_mask = BIT(9),
 571                 .hw.init = &(struct clk_init_data){
 572                         .name = "gsbi8_uart_clk",
 573                         .parent_names = (const char *[]){ "gsbi8_uart_src" },
 574                         .num_parents = 1,
 575                         .ops = &clk_branch_ops,
 576                         .flags = CLK_SET_RATE_PARENT,
 577                 },
 578         },
 579 };
 580
 581 static struct clk_rcg gsbi9_uart_src = {
 582         .ns_reg = 0x2ad4,
 583         .md_reg = 0x2ad0,
 584         .mn = {
 585                 .mnctr_en_bit = 8,
 586                 .mnctr_reset_bit = 7,
 587                 .mnctr_mode_shift = 5,
 588                 .n_val_shift = 16,
 589                 .m_val_shift = 16,
 590                 .width = 16,
 591         },
 592         .p = {
 593                 .pre_div_shift = 3,
 594                 .pre_div_width = 2,
 595         },
 596         .s = {
 597                 .src_sel_shift = 0,
 598                 .parent_map = gcc_pxo_pll8_map,
 599         },
 600         .freq_tbl = clk_tbl_gsbi_uart,
 601         .clkr = {
 602                 .enable_reg = 0x2ad4,
 603                 .enable_mask = BIT(11),
 604                 .hw.init = &(struct clk_init_data){
 605                         .name = "gsbi9_uart_src",
 606                         .parent_names = gcc_pxo_pll8,
 607                         .num_parents = 2,
 608                         .ops = &clk_rcg_ops,
 609                         .flags = CLK_SET_PARENT_GATE,
 610                 },
 611         },
 612 };
 613
 614 static struct clk_branch gsbi9_uart_clk = {
 615         .halt_reg = 0x2fd0,
 616         .halt_bit = 6,
 617         .clkr = {
 618                 .enable_reg = 0x2ad4,
 619                 .enable_mask = BIT(9),
 620                 .hw.init = &(struct clk_init_data){
 621                         .name = "gsbi9_uart_clk",
 622                         .parent_names = (const char *[]){ "gsbi9_uart_src" },
 623                         .num_parents = 1,
 624                         .ops = &clk_branch_ops,
 625                         .flags = CLK_SET_RATE_PARENT,
 626                 },
 627         },
 628 };
 629
 630 static struct clk_rcg gsbi10_uart_src = {
 631         .ns_reg = 0x2af4,
 632         .md_reg = 0x2af0,
 633         .mn = {
 634                 .mnctr_en_bit = 8,
 635                 .mnctr_reset_bit = 7,
 636                 .mnctr_mode_shift = 5,
 637                 .n_val_shift = 16,
 638                 .m_val_shift = 16,
 639                 .width = 16,
 640         },
 641         .p = {
 642                 .pre_div_shift = 3,
 643                 .pre_div_width = 2,
 644         },
 645         .s = {
 646                 .src_sel_shift = 0,
 647                 .parent_map = gcc_pxo_pll8_map,
 648         },
 649         .freq_tbl = clk_tbl_gsbi_uart,
 650         .clkr = {
 651                 .enable_reg = 0x2af4,
 652                 .enable_mask = BIT(11),
 653                 .hw.init = &(struct clk_init_data){
 654                         .name = "gsbi10_uart_src",
 655                         .parent_names = gcc_pxo_pll8,
 656                         .num_parents = 2,
 657                         .ops = &clk_rcg_ops,
 658                         .flags = CLK_SET_PARENT_GATE,
 659                 },
 660         },
 661 };
 662
 663 static struct clk_branch gsbi10_uart_clk = {
 664         .halt_reg = 0x2fd0,
 665         .halt_bit = 2,
 666         .clkr = {
 667                 .enable_reg = 0x2af4,
 668                 .enable_mask = BIT(9),
 669                 .hw.init = &(struct clk_init_data){
 670                         .name = "gsbi10_uart_clk",
 671                         .parent_names = (const char *[]){ "gsbi10_uart_src" },
 672                         .num_parents = 1,
 673                         .ops = &clk_branch_ops,
 674                         .flags = CLK_SET_RATE_PARENT,
 675                 },
 676         },
 677 };
 678
 679 static struct clk_rcg gsbi11_uart_src = {
 680         .ns_reg = 0x2b14,
 681         .md_reg = 0x2b10,
 682         .mn = {
 683                 .mnctr_en_bit = 8,
 684                 .mnctr_reset_bit = 7,
 685                 .mnctr_mode_shift = 5,
 686                 .n_val_shift = 16,
 687                 .m_val_shift = 16,
 688                 .width = 16,
 689         },
 690         .p = {
 691                 .pre_div_shift = 3,
 692                 .pre_div_width = 2,
 693         },
 694         .s = {
 695                 .src_sel_shift = 0,
 696                 .parent_map = gcc_pxo_pll8_map,
 697         },
 698         .freq_tbl = clk_tbl_gsbi_uart,
 699         .clkr = {
 700                 .enable_reg = 0x2b14,
 701                 .enable_mask = BIT(11),
 702                 .hw.init = &(struct clk_init_data){
 703                         .name = "gsbi11_uart_src",
 704                         .parent_names = gcc_pxo_pll8,
 705                         .num_parents = 2,
 706                         .ops = &clk_rcg_ops,
 707                         .flags = CLK_SET_PARENT_GATE,
 708                 },
 709         },
 710 };
 711
 712 static struct clk_branch gsbi11_uart_clk = {
 713         .halt_reg = 0x2fd4,
 714         .halt_bit = 17,
 715         .clkr = {
 716                 .enable_reg = 0x2b14,
 717                 .enable_mask = BIT(9),
 718                 .hw.init = &(struct clk_init_data){
 719                         .name = "gsbi11_uart_clk",
 720                         .parent_names = (const char *[]){ "gsbi11_uart_src" },
 721                         .num_parents = 1,
 722                         .ops = &clk_branch_ops,
 723                         .flags = CLK_SET_RATE_PARENT,
 724                 },
 725         },
 726 };
 727
 728 static struct clk_rcg gsbi12_uart_src = {
 729         .ns_reg = 0x2b34,
 730         .md_reg = 0x2b30,
 731         .mn = {
 732                 .mnctr_en_bit = 8,
 733                 .mnctr_reset_bit = 7,
 734                 .mnctr_mode_shift = 5,
 735                 .n_val_shift = 16,
 736                 .m_val_shift = 16,
 737                 .width = 16,
 738         },
 739         .p = {
 740                 .pre_div_shift = 3,
 741                 .pre_div_width = 2,
 742         },
 743         .s = {
 744                 .src_sel_shift = 0,
 745                 .parent_map = gcc_pxo_pll8_map,
 746         },
 747         .freq_tbl = clk_tbl_gsbi_uart,
 748         .clkr = {
 749                 .enable_reg = 0x2b34,
 750                 .enable_mask = BIT(11),
 751                 .hw.init = &(struct clk_init_data){
 752                         .name = "gsbi12_uart_src",
 753                         .parent_names = gcc_pxo_pll8,
 754                         .num_parents = 2,
 755                         .ops = &clk_rcg_ops,
 756                         .flags = CLK_SET_PARENT_GATE,
 757                 },
 758         },
 759 };
 760
 761 static struct clk_branch gsbi12_uart_clk = {
 762         .halt_reg = 0x2fd4,
 763         .halt_bit = 13,
 764         .clkr = {
 765                 .enable_reg = 0x2b34,
 766                 .enable_mask = BIT(9),
 767                 .hw.init = &(struct clk_init_data){
 768                         .name = "gsbi12_uart_clk",
 769                         .parent_names = (const char *[]){ "gsbi12_uart_src" },
 770                         .num_parents = 1,
 771                         .ops = &clk_branch_ops,
 772                         .flags = CLK_SET_RATE_PARENT,
 773                 },
 774         },
 775 };
 776
 777 static struct freq_tbl clk_tbl_gsbi_qup[] = {
 778         {  1100000, P_PXO,  1, 2, 49 },
 779         {  5400000, P_PXO,  1, 1,  5 },
 780         { 10800000, P_PXO,  1, 2,  5 },
 781         { 15060000, P_PLL8, 1, 2, 51 },
 782         { 24000000, P_PLL8, 4, 1,  4 },
 783         { 25600000, P_PLL8, 1, 1, 15 },
 784         { 27000000, P_PXO,  1, 0,  0 },
 785         { 48000000, P_PLL8, 4, 1,  2 },
 786         { 51200000, P_PLL8, 1, 2, 15 },
 787         { }
 788 };
 789
 790 static struct clk_rcg gsbi1_qup_src = {
 791         .ns_reg = 0x29cc,
 792         .md_reg = 0x29c8,
 793         .mn = {
 794                 .mnctr_en_bit = 8,
 795                 .mnctr_reset_bit = 7,
 796                 .mnctr_mode_shift = 5,
 797                 .n_val_shift = 16,
 798                 .m_val_shift = 16,
 799                 .width = 8,
 800         },
 801         .p = {
 802                 .pre_div_shift = 3,
 803                 .pre_div_width = 2,
 804         },
 805         .s = {
 806                 .src_sel_shift = 0,
 807                 .parent_map = gcc_pxo_pll8_map,
 808         },
 809         .freq_tbl = clk_tbl_gsbi_qup,
 810         .clkr = {
 811                 .enable_reg = 0x29cc,
 812                 .enable_mask = BIT(11),
 813                 .hw.init = &(struct clk_init_data){
 814                         .name = "gsbi1_qup_src",
 815                         .parent_names = gcc_pxo_pll8,
 816                         .num_parents = 2,
 817                         .ops = &clk_rcg_ops,
 818                         .flags = CLK_SET_PARENT_GATE,
 819                 },
 820         },
 821 };
 822
 823 static struct clk_branch gsbi1_qup_clk = {
 824         .halt_reg = 0x2fcc,
 825         .halt_bit = 9,
 826         .clkr = {
 827                 .enable_reg = 0x29cc,
 828                 .enable_mask = BIT(9),
 829                 .hw.init = &(struct clk_init_data){
 830                         .name = "gsbi1_qup_clk",
 831                         .parent_names = (const char *[]){ "gsbi1_qup_src" },
 832                         .num_parents = 1,
 833                         .ops = &clk_branch_ops,
 834                         .flags = CLK_SET_RATE_PARENT,
 835                 },
 836         },
 837 };
 838
 839 static struct clk_rcg gsbi2_qup_src = {
 840         .ns_reg = 0x29ec,
 841         .md_reg = 0x29e8,
 842         .mn = {
 843                 .mnctr_en_bit = 8,
 844                 .mnctr_reset_bit = 7,
 845                 .mnctr_mode_shift = 5,
 846                 .n_val_shift = 16,
 847                 .m_val_shift = 16,
 848                 .width = 8,
 849         },
 850         .p = {
 851                 .pre_div_shift = 3,
 852                 .pre_div_width = 2,
 853         },
 854         .s = {
 855                 .src_sel_shift = 0,
 856                 .parent_map = gcc_pxo_pll8_map,
 857         },
 858         .freq_tbl = clk_tbl_gsbi_qup,
 859         .clkr = {
 860                 .enable_reg = 0x29ec,
 861                 .enable_mask = BIT(11),
 862                 .hw.init = &(struct clk_init_data){
 863                         .name = "gsbi2_qup_src",
 864                         .parent_names = gcc_pxo_pll8,
 865                         .num_parents = 2,
 866                         .ops = &clk_rcg_ops,
 867                         .flags = CLK_SET_PARENT_GATE,
 868                 },
 869         },
 870 };
 871
 872 static struct clk_branch gsbi2_qup_clk = {
 873         .halt_reg = 0x2fcc,
 874         .halt_bit = 4,
 875         .clkr = {
 876                 .enable_reg = 0x29ec,
 877                 .enable_mask = BIT(9),
 878                 .hw.init = &(struct clk_init_data){
 879                         .name = "gsbi2_qup_clk",
 880                         .parent_names = (const char *[]){ "gsbi2_qup_src" },
 881                         .num_parents = 1,
 882                         .ops = &clk_branch_ops,
 883                         .flags = CLK_SET_RATE_PARENT,
 884                 },
 885         },
 886 };
 887
 888 static struct clk_rcg gsbi3_qup_src = {
 889         .ns_reg = 0x2a0c,
 890         .md_reg = 0x2a08,
 891         .mn = {
 892                 .mnctr_en_bit = 8,
 893                 .mnctr_reset_bit = 7,
 894                 .mnctr_mode_shift = 5,
 895                 .n_val_shift = 16,
 896                 .m_val_shift = 16,
 897                 .width = 8,
 898         },
 899         .p = {
 900                 .pre_div_shift = 3,
 901                 .pre_div_width = 2,
 902         },
 903         .s = {
 904                 .src_sel_shift = 0,
 905                 .parent_map = gcc_pxo_pll8_map,
 906         },
 907         .freq_tbl = clk_tbl_gsbi_qup,
 908         .clkr = {
 909                 .enable_reg = 0x2a0c,
 910                 .enable_mask = BIT(11),
 911                 .hw.init = &(struct clk_init_data){
 912                         .name = "gsbi3_qup_src",
 913                         .parent_names = gcc_pxo_pll8,
 914                         .num_parents = 2,
 915                         .ops = &clk_rcg_ops,
 916                         .flags = CLK_SET_PARENT_GATE,
 917                 },
 918         },
 919 };
 920
 921 static struct clk_branch gsbi3_qup_clk = {
 922         .halt_reg = 0x2fcc,
 923         .halt_bit = 0,
 924         .clkr = {
 925                 .enable_reg = 0x2a0c,
 926                 .enable_mask = BIT(9),
 927                 .hw.init = &(struct clk_init_data){
 928                         .name = "gsbi3_qup_clk",
 929                         .parent_names = (const char *[]){ "gsbi3_qup_src" },
 930                         .num_parents = 1,
 931                         .ops = &clk_branch_ops,
 932                         .flags = CLK_SET_RATE_PARENT,
 933                 },
 934         },
 935 };
 936
 937 static struct clk_rcg gsbi4_qup_src = {
 938         .ns_reg = 0x2a2c,
 939         .md_reg = 0x2a28,
 940         .mn = {
 941                 .mnctr_en_bit = 8,
 942                 .mnctr_reset_bit = 7,
 943                 .mnctr_mode_shift = 5,
 944                 .n_val_shift = 16,
 945                 .m_val_shift = 16,
 946                 .width = 8,
 947         },
 948         .p = {
 949                 .pre_div_shift = 3,
 950                 .pre_div_width = 2,
 951         },
 952         .s = {
 953                 .src_sel_shift = 0,
 954                 .parent_map = gcc_pxo_pll8_map,
 955         },
 956         .freq_tbl = clk_tbl_gsbi_qup,
 957         .clkr = {
 958                 .enable_reg = 0x2a2c,
 959                 .enable_mask = BIT(11),
 960                 .hw.init = &(struct clk_init_data){
 961                         .name = "gsbi4_qup_src",
 962                         .parent_names = gcc_pxo_pll8,
 963                         .num_parents = 2,
 964                         .ops = &clk_rcg_ops,
 965                         .flags = CLK_SET_PARENT_GATE,
 966                 },
 967         },
 968 };
 969
 970 static struct clk_branch gsbi4_qup_clk = {
 971         .halt_reg = 0x2fd0,
 972         .halt_bit = 24,
 973         .clkr = {
 974                 .enable_reg = 0x2a2c,
 975                 .enable_mask = BIT(9),
 976                 .hw.init = &(struct clk_init_data){
 977                         .name = "gsbi4_qup_clk",
 978                         .parent_names = (const char *[]){ "gsbi4_qup_src" },
 979                         .num_parents = 1,
 980                         .ops = &clk_branch_ops,
 981                         .flags = CLK_SET_RATE_PARENT,
 982                 },
 983         },
 984 };
 985
 986 static struct clk_rcg gsbi5_qup_src = {
 987         .ns_reg = 0x2a4c,
 988         .md_reg = 0x2a48,
 989         .mn = {
 990                 .mnctr_en_bit = 8,
 991                 .mnctr_reset_bit = 7,
 992                 .mnctr_mode_shift = 5,
 993                 .n_val_shift = 16,
 994                 .m_val_shift = 16,
 995                 .width = 8,
 996         },
 997         .p = {
 998                 .pre_div_shift = 3,
 999                 .pre_div_width = 2,
1000         },
1001         .s = {
1002                 .src_sel_shift = 0,
1003                 .parent_map = gcc_pxo_pll8_map,
1004         },
1005         .freq_tbl = clk_tbl_gsbi_qup,
1006         .clkr = {
1007                 .enable_reg = 0x2a4c,
1008                 .enable_mask = BIT(11),
1009                 .hw.init = &(struct clk_init_data){
1010                         .name = "gsbi5_qup_src",
1011                         .parent_names = gcc_pxo_pll8,
1012                         .num_parents = 2,
1013                         .ops = &clk_rcg_ops,
1014                         .flags = CLK_SET_PARENT_GATE,
1015                 },
1016         },
1017 };
1018
1019 static struct clk_branch gsbi5_qup_clk = {
1020         .halt_reg = 0x2fd0,
1021         .halt_bit = 20,
1022         .clkr = {
1023                 .enable_reg = 0x2a4c,
1024                 .enable_mask = BIT(9),
1025                 .hw.init = &(struct clk_init_data){
1026                         .name = "gsbi5_qup_clk",
1027                         .parent_names = (const char *[]){ "gsbi5_qup_src" },
1028                         .num_parents = 1,
1029                         .ops = &clk_branch_ops,
1030                         .flags = CLK_SET_RATE_PARENT,
1031                 },
1032         },
1033 };
1034
1035 static struct clk_rcg gsbi6_qup_src = {
1036         .ns_reg = 0x2a6c,
1037         .md_reg = 0x2a68,
1038         .mn = {
1039                 .mnctr_en_bit = 8,
1040                 .mnctr_reset_bit = 7,
1041                 .mnctr_mode_shift = 5,
1042                 .n_val_shift = 16,
1043                 .m_val_shift = 16,
1044                 .width = 8,
1045         },
1046         .p = {
1047                 .pre_div_shift = 3,
1048                 .pre_div_width = 2,
1049         },
1050         .s = {
1051                 .src_sel_shift = 0,
1052                 .parent_map = gcc_pxo_pll8_map,
1053         },
1054         .freq_tbl = clk_tbl_gsbi_qup,
1055         .clkr = {
1056                 .enable_reg = 0x2a6c,
1057                 .enable_mask = BIT(11),
1058                 .hw.init = &(struct clk_init_data){
1059                         .name = "gsbi6_qup_src",
1060                         .parent_names = gcc_pxo_pll8,
1061                         .num_parents = 2,
1062                         .ops = &clk_rcg_ops,
1063                         .flags = CLK_SET_PARENT_GATE,
1064                 },
1065         },
1066 };
1067
1068 static struct clk_branch gsbi6_qup_clk = {
1069         .halt_reg = 0x2fd0,
1070         .halt_bit = 16,
1071         .clkr = {
1072                 .enable_reg = 0x2a6c,
1073                 .enable_mask = BIT(9),
1074                 .hw.init = &(struct clk_init_data){
1075                         .name = "gsbi6_qup_clk",
1076                         .parent_names = (const char *[]){ "gsbi6_qup_src" },
1077                         .num_parents = 1,
1078                         .ops = &clk_branch_ops,
1079                         .flags = CLK_SET_RATE_PARENT,
1080                 },
1081         },
1082 };
1083
1084 static struct clk_rcg gsbi7_qup_src = {
1085         .ns_reg = 0x2a8c,
1086         .md_reg = 0x2a88,
1087         .mn = {
1088                 .mnctr_en_bit = 8,
1089                 .mnctr_reset_bit = 7,
1090                 .mnctr_mode_shift = 5,
1091                 .n_val_shift = 16,
1092                 .m_val_shift = 16,
1093                 .width = 8,
1094         },
1095         .p = {
1096                 .pre_div_shift = 3,
1097                 .pre_div_width = 2,
1098         },
1099         .s = {
1100                 .src_sel_shift = 0,
1101                 .parent_map = gcc_pxo_pll8_map,
1102         },
1103         .freq_tbl = clk_tbl_gsbi_qup,
1104         .clkr = {
1105                 .enable_reg = 0x2a8c,
1106                 .enable_mask = BIT(11),
1107                 .hw.init = &(struct clk_init_data){
1108                         .name = "gsbi7_qup_src",
1109                         .parent_names = gcc_pxo_pll8,
1110                         .num_parents = 2,
1111                         .ops = &clk_rcg_ops,
1112                         .flags = CLK_SET_PARENT_GATE,
1113                 },
1114         },
1115 };
1116
1117 static struct clk_branch gsbi7_qup_clk = {
1118         .halt_reg = 0x2fd0,
1119         .halt_bit = 12,
1120         .clkr = {
1121                 .enable_reg = 0x2a8c,
1122                 .enable_mask = BIT(9),
1123                 .hw.init = &(struct clk_init_data){
1124                         .name = "gsbi7_qup_clk",
1125                         .parent_names = (const char *[]){ "gsbi7_qup_src" },
1126                         .num_parents = 1,
1127                         .ops = &clk_branch_ops,
1128                         .flags = CLK_SET_RATE_PARENT,
1129                 },
1130         },
1131 };
1132
1133 static struct clk_rcg gsbi8_qup_src = {
1134         .ns_reg = 0x2aac,
1135         .md_reg = 0x2aa8,
1136         .mn = {
1137                 .mnctr_en_bit = 8,
1138                 .mnctr_reset_bit = 7,
1139                 .mnctr_mode_shift = 5,
1140                 .n_val_shift = 16,
1141                 .m_val_shift = 16,
1142                 .width = 8,
1143         },
1144         .p = {
1145                 .pre_div_shift = 3,
1146                 .pre_div_width = 2,
1147         },
1148         .s = {
1149                 .src_sel_shift = 0,
1150                 .parent_map = gcc_pxo_pll8_map,
1151         },
1152         .freq_tbl = clk_tbl_gsbi_qup,
1153         .clkr = {
1154                 .enable_reg = 0x2aac,
1155                 .enable_mask = BIT(11),
1156                 .hw.init = &(struct clk_init_data){
1157                         .name = "gsbi8_qup_src",
1158                         .parent_names = gcc_pxo_pll8,
1159                         .num_parents = 2,
1160                         .ops = &clk_rcg_ops,
1161                         .flags = CLK_SET_PARENT_GATE,
1162                 },
1163         },
1164 };
1165
1166 static struct clk_branch gsbi8_qup_clk = {
1167         .halt_reg = 0x2fd0,
1168         .halt_bit = 8,
1169         .clkr = {
1170                 .enable_reg = 0x2aac,
1171                 .enable_mask = BIT(9),
1172                 .hw.init = &(struct clk_init_data){
1173                         .name = "gsbi8_qup_clk",
1174                         .parent_names = (const char *[]){ "gsbi8_qup_src" },
1175                         .num_parents = 1,
1176                         .ops = &clk_branch_ops,
1177                         .flags = CLK_SET_RATE_PARENT,
1178                 },
1179         },
1180 };
1181
1182 static struct clk_rcg gsbi9_qup_src = {
1183         .ns_reg = 0x2acc,
1184         .md_reg = 0x2ac8,
1185         .mn = {
1186                 .mnctr_en_bit = 8,
1187                 .mnctr_reset_bit = 7,
1188                 .mnctr_mode_shift = 5,
1189                 .n_val_shift = 16,
1190                 .m_val_shift = 16,
1191                 .width = 8,
1192         },
1193         .p = {
1194                 .pre_div_shift = 3,
1195                 .pre_div_width = 2,
1196         },
1197         .s = {
1198                 .src_sel_shift = 0,
1199                 .parent_map = gcc_pxo_pll8_map,
1200         },
1201         .freq_tbl = clk_tbl_gsbi_qup,
1202         .clkr = {
1203                 .enable_reg = 0x2acc,
1204                 .enable_mask = BIT(11),
1205                 .hw.init = &(struct clk_init_data){
1206                         .name = "gsbi9_qup_src",
1207                         .parent_names = gcc_pxo_pll8,
1208                         .num_parents = 2,
1209                         .ops = &clk_rcg_ops,
1210                         .flags = CLK_SET_PARENT_GATE,
1211                 },
1212         },
1213 };
1214
1215 static struct clk_branch gsbi9_qup_clk = {
1216         .halt_reg = 0x2fd0,
1217         .halt_bit = 4,
1218         .clkr = {
1219                 .enable_reg = 0x2acc,
1220                 .enable_mask = BIT(9),
1221                 .hw.init = &(struct clk_init_data){
1222                         .name = "gsbi9_qup_clk",
1223                         .parent_names = (const char *[]){ "gsbi9_qup_src" },
1224                         .num_parents = 1,
1225                         .ops = &clk_branch_ops,
1226                         .flags = CLK_SET_RATE_PARENT,
1227                 },
1228         },
1229 };
1230
1231 static struct clk_rcg gsbi10_qup_src = {
1232         .ns_reg = 0x2aec,
1233         .md_reg = 0x2ae8,
1234         .mn = {
1235                 .mnctr_en_bit = 8,
1236                 .mnctr_reset_bit = 7,
1237                 .mnctr_mode_shift = 5,
1238                 .n_val_shift = 16,
1239                 .m_val_shift = 16,
1240                 .width = 8,
1241         },
1242         .p = {
1243                 .pre_div_shift = 3,
1244                 .pre_div_width = 2,
1245         },
1246         .s = {
1247                 .src_sel_shift = 0,
1248                 .parent_map = gcc_pxo_pll8_map,
1249         },
1250         .freq_tbl = clk_tbl_gsbi_qup,
1251         .clkr = {
1252                 .enable_reg = 0x2aec,
1253                 .enable_mask = BIT(11),
1254                 .hw.init = &(struct clk_init_data){
1255                         .name = "gsbi10_qup_src",
1256                         .parent_names = gcc_pxo_pll8,
1257                         .num_parents = 2,
1258                         .ops = &clk_rcg_ops,
1259                         .flags = CLK_SET_PARENT_GATE,
1260                 },
1261         },
1262 };
1263
1264 static struct clk_branch gsbi10_qup_clk = {
1265         .halt_reg = 0x2fd0,
1266         .halt_bit = 0,
1267         .clkr = {
1268                 .enable_reg = 0x2aec,
1269                 .enable_mask = BIT(9),
1270                 .hw.init = &(struct clk_init_data){
1271                         .name = "gsbi10_qup_clk",
1272                         .parent_names = (const char *[]){ "gsbi10_qup_src" },
1273                         .num_parents = 1,
1274                         .ops = &clk_branch_ops,
1275                         .flags = CLK_SET_RATE_PARENT,
1276                 },
1277         },
1278 };
1279
1280 static struct clk_rcg gsbi11_qup_src = {
1281         .ns_reg = 0x2b0c,
1282         .md_reg = 0x2b08,
1283         .mn = {
1284                 .mnctr_en_bit = 8,
1285                 .mnctr_reset_bit = 7,
1286                 .mnctr_mode_shift = 5,
1287                 .n_val_shift = 16,
1288                 .m_val_shift = 16,
1289                 .width = 8,
1290         },
1291         .p = {
1292                 .pre_div_shift = 3,
1293                 .pre_div_width = 2,
1294         },
1295         .s = {
1296                 .src_sel_shift = 0,
1297                 .parent_map = gcc_pxo_pll8_map,
1298         },
1299         .freq_tbl = clk_tbl_gsbi_qup,
1300         .clkr = {
1301                 .enable_reg = 0x2b0c,
1302                 .enable_mask = BIT(11),
1303                 .hw.init = &(struct clk_init_data){
1304                         .name = "gsbi11_qup_src",
1305                         .parent_names = gcc_pxo_pll8,
1306                         .num_parents = 2,
1307                         .ops = &clk_rcg_ops,
1308                         .flags = CLK_SET_PARENT_GATE,
1309                 },
1310         },
1311 };
1312
1313 static struct clk_branch gsbi11_qup_clk = {
1314         .halt_reg = 0x2fd4,
1315         .halt_bit = 15,
1316         .clkr = {
1317                 .enable_reg = 0x2b0c,
1318                 .enable_mask = BIT(9),
1319                 .hw.init = &(struct clk_init_data){
1320                         .name = "gsbi11_qup_clk",
1321                         .parent_names = (const char *[]){ "gsbi11_qup_src" },
1322                         .num_parents = 1,
1323                         .ops = &clk_branch_ops,
1324                         .flags = CLK_SET_RATE_PARENT,
1325                 },
1326         },
1327 };
1328
1329 static struct clk_rcg gsbi12_qup_src = {
1330         .ns_reg = 0x2b2c,
1331         .md_reg = 0x2b28,
1332         .mn = {
1333                 .mnctr_en_bit = 8,
1334                 .mnctr_reset_bit = 7,
1335                 .mnctr_mode_shift = 5,
1336                 .n_val_shift = 16,
1337                 .m_val_shift = 16,
1338                 .width = 8,
1339         },
1340         .p = {
1341                 .pre_div_shift = 3,
1342                 .pre_div_width = 2,
1343         },
1344         .s = {
1345                 .src_sel_shift = 0,
1346                 .parent_map = gcc_pxo_pll8_map,
1347         },
1348         .freq_tbl = clk_tbl_gsbi_qup,
1349         .clkr = {
1350                 .enable_reg = 0x2b2c,
1351                 .enable_mask = BIT(11),
1352                 .hw.init = &(struct clk_init_data){
1353                         .name = "gsbi12_qup_src",
1354                         .parent_names = gcc_pxo_pll8,
1355                         .num_parents = 2,
1356                         .ops = &clk_rcg_ops,
1357                         .flags = CLK_SET_PARENT_GATE,
1358                 },
1359         },
1360 };
1361
1362 static struct clk_branch gsbi12_qup_clk = {
1363         .halt_reg = 0x2fd4,
1364         .halt_bit = 11,
1365         .clkr = {
1366                 .enable_reg = 0x2b2c,
1367                 .enable_mask = BIT(9),
1368                 .hw.init = &(struct clk_init_data){
1369                         .name = "gsbi12_qup_clk",
1370                         .parent_names = (const char *[]){ "gsbi12_qup_src" },
1371                         .num_parents = 1,
1372                         .ops = &clk_branch_ops,
1373                         .flags = CLK_SET_RATE_PARENT,
1374                 },
1375         },
1376 };
1377
1378 static const struct freq_tbl clk_tbl_gp[] = {
1379         { 9600000, P_CXO,  2, 0, 0 },
1380         { 13500000, P_PXO,  2, 0, 0 },
1381         { 19200000, P_CXO,  1, 0, 0 },
1382         { 27000000, P_PXO,  1, 0, 0 },
1383         { 64000000, P_PLL8, 2, 1, 3 },
1384         { 76800000, P_PLL8, 1, 1, 5 },
1385         { 96000000, P_PLL8, 4, 0, 0 },
1386         { 128000000, P_PLL8, 3, 0, 0 },
1387         { 192000000, P_PLL8, 2, 0, 0 },
1388         { }
1389 };
1390
1391 static struct clk_rcg gp0_src = {
1392         .ns_reg = 0x2d24,
1393         .md_reg = 0x2d00,
1394         .mn = {
1395                 .mnctr_en_bit = 8,
1396                 .mnctr_reset_bit = 7,
1397                 .mnctr_mode_shift = 5,
1398                 .n_val_shift = 16,
1399                 .m_val_shift = 16,
1400                 .width = 8,
1401         },
1402         .p = {
1403                 .pre_div_shift = 3,
1404                 .pre_div_width = 2,
1405         },
1406         .s = {
1407                 .src_sel_shift = 0,
1408                 .parent_map = gcc_pxo_pll8_cxo_map,
1409         },
1410         .freq_tbl = clk_tbl_gp,
1411         .clkr = {
1412                 .enable_reg = 0x2d24,
1413                 .enable_mask = BIT(11),
1414                 .hw.init = &(struct clk_init_data){
1415                         .name = "gp0_src",
1416                         .parent_names = gcc_pxo_pll8_cxo,
1417                         .num_parents = 3,
1418                         .ops = &clk_rcg_ops,
1419                         .flags = CLK_SET_PARENT_GATE,
1420                 },
1421         }
1422 };
1423
1424 static struct clk_branch gp0_clk = {
1425         .halt_reg = 0x2fd8,
1426         .halt_bit = 7,
1427         .clkr = {
1428                 .enable_reg = 0x2d24,
1429                 .enable_mask = BIT(9),
1430                 .hw.init = &(struct clk_init_data){
1431                         .name = "gp0_clk",
1432                         .parent_names = (const char *[]){ "gp0_src" },
1433                         .num_parents = 1,
1434                         .ops = &clk_branch_ops,
1435                         .flags = CLK_SET_RATE_PARENT,
1436                 },
1437         },
1438 };
1439
1440 static struct clk_rcg gp1_src = {
1441         .ns_reg = 0x2d44,
1442         .md_reg = 0x2d40,
1443         .mn = {
1444                 .mnctr_en_bit = 8,
1445                 .mnctr_reset_bit = 7,
1446                 .mnctr_mode_shift = 5,
1447                 .n_val_shift = 16,
1448                 .m_val_shift = 16,
1449                 .width = 8,
1450         },
1451         .p = {
1452                 .pre_div_shift = 3,
1453                 .pre_div_width = 2,
1454         },
1455         .s = {
1456                 .src_sel_shift = 0,
1457                 .parent_map = gcc_pxo_pll8_cxo_map,
1458         },
1459         .freq_tbl = clk_tbl_gp,
1460         .clkr = {
1461                 .enable_reg = 0x2d44,
1462                 .enable_mask = BIT(11),
1463                 .hw.init = &(struct clk_init_data){
1464                         .name = "gp1_src",
1465                         .parent_names = gcc_pxo_pll8_cxo,
1466                         .num_parents = 3,
1467                         .ops = &clk_rcg_ops,
1468                         .flags = CLK_SET_RATE_GATE,
1469                 },
1470         }
1471 };
1472
1473 static struct clk_branch gp1_clk = {
1474         .halt_reg = 0x2fd8,
1475         .halt_bit = 6,
1476         .clkr = {
1477                 .enable_reg = 0x2d44,
1478                 .enable_mask = BIT(9),
1479                 .hw.init = &(struct clk_init_data){
1480                         .name = "gp1_clk",
1481                         .parent_names = (const char *[]){ "gp1_src" },
1482                         .num_parents = 1,
1483                         .ops = &clk_branch_ops,
1484                         .flags = CLK_SET_RATE_PARENT,
1485                 },
1486         },
1487 };
1488
1489 static struct clk_rcg gp2_src = {
1490         .ns_reg = 0x2d64,
1491         .md_reg = 0x2d60,
1492         .mn = {
1493                 .mnctr_en_bit = 8,
1494                 .mnctr_reset_bit = 7,
1495                 .mnctr_mode_shift = 5,
1496                 .n_val_shift = 16,
1497                 .m_val_shift = 16,
1498                 .width = 8,
1499         },
1500         .p = {
1501                 .pre_div_shift = 3,
1502                 .pre_div_width = 2,
1503         },
1504         .s = {
1505                 .src_sel_shift = 0,
1506                 .parent_map = gcc_pxo_pll8_cxo_map,
1507         },
1508         .freq_tbl = clk_tbl_gp,
1509         .clkr = {
1510                 .enable_reg = 0x2d64,
1511                 .enable_mask = BIT(11),
1512                 .hw.init = &(struct clk_init_data){
1513                         .name = "gp2_src",
1514                         .parent_names = gcc_pxo_pll8_cxo,
1515                         .num_parents = 3,
1516                         .ops = &clk_rcg_ops,
1517                         .flags = CLK_SET_RATE_GATE,
1518                 },
1519         }
1520 };
1521
1522 static struct clk_branch gp2_clk = {
1523         .halt_reg = 0x2fd8,
1524         .halt_bit = 5,
1525         .clkr = {
1526                 .enable_reg = 0x2d64,
1527                 .enable_mask = BIT(9),
1528                 .hw.init = &(struct clk_init_data){
1529                         .name = "gp2_clk",
1530                         .parent_names = (const char *[]){ "gp2_src" },
1531                         .num_parents = 1,
1532                         .ops = &clk_branch_ops,
1533                         .flags = CLK_SET_RATE_PARENT,
1534                 },
1535         },
1536 };
1537
1538 static struct clk_branch pmem_clk = {
1539         .hwcg_reg = 0x25a0,
1540         .hwcg_bit = 6,
1541         .halt_reg = 0x2fc8,
1542         .halt_bit = 20,
1543         .clkr = {
1544                 .enable_reg = 0x25a0,
1545                 .enable_mask = BIT(4),
1546                 .hw.init = &(struct clk_init_data){
1547                         .name = "pmem_clk",
1548                         .ops = &clk_branch_ops,
1549                 },
1550         },
1551 };
1552
1553 static struct clk_rcg prng_src = {
1554         .ns_reg = 0x2e80,
1555         .p = {
1556                 .pre_div_shift = 3,
1557                 .pre_div_width = 4,
1558         },
1559         .s = {
1560                 .src_sel_shift = 0,
1561                 .parent_map = gcc_pxo_pll8_map,
1562         },
1563         .clkr = {
1564                 .hw.init = &(struct clk_init_data){
1565                         .name = "prng_src",
1566                         .parent_names = gcc_pxo_pll8,
1567                         .num_parents = 2,
1568                         .ops = &clk_rcg_ops,
1569                 },
1570         },
1571 };
1572
1573 static struct clk_branch prng_clk = {
1574         .halt_reg = 0x2fd8,
1575         .halt_check = BRANCH_HALT_VOTED,
1576         .halt_bit = 10,
1577         .clkr = {
1578                 .enable_reg = 0x3080,
1579                 .enable_mask = BIT(10),
1580                 .hw.init = &(struct clk_init_data){
1581                         .name = "prng_clk",
1582                         .parent_names = (const char *[]){ "prng_src" },
1583                         .num_parents = 1,
1584                         .ops = &clk_branch_ops,
1585                 },
1586         },
1587 };
1588
1589 static const struct freq_tbl clk_tbl_sdc[] = {
1590         {    144000, P_PXO,   3, 2, 125 },
1591         {    400000, P_PLL8,  4, 1, 240 },
1592         {  16000000, P_PLL8,  4, 1,   6 },
1593         {  17070000, P_PLL8,  1, 2,  45 },
1594         {  20210000, P_PLL8,  1, 1,  19 },
1595         {  24000000, P_PLL8,  4, 1,   4 },
1596         {  48000000, P_PLL8,  4, 1,   2 },
1597         {  64000000, P_PLL8,  3, 1,   2 },
1598         {  96000000, P_PLL8,  4, 0,   0 },
1599         { 192000000, P_PLL8,  2, 0,   0 },
1600         { }
1601 };
1602
1603 static struct clk_rcg sdc1_src = {
1604         .ns_reg = 0x282c,
1605         .md_reg = 0x2828,
1606         .mn = {
1607                 .mnctr_en_bit = 8,
1608                 .mnctr_reset_bit = 7,
1609                 .mnctr_mode_shift = 5,
1610                 .n_val_shift = 16,
1611                 .m_val_shift = 16,
1612                 .width = 8,
1613         },
1614         .p = {
1615                 .pre_div_shift = 3,
1616                 .pre_div_width = 2,
1617         },
1618         .s = {
1619                 .src_sel_shift = 0,
1620                 .parent_map = gcc_pxo_pll8_map,
1621         },
1622         .freq_tbl = clk_tbl_sdc,
1623         .clkr = {
1624                 .enable_reg = 0x282c,
1625                 .enable_mask = BIT(11),
1626                 .hw.init = &(struct clk_init_data){
1627                         .name = "sdc1_src",
1628                         .parent_names = gcc_pxo_pll8,
1629                         .num_parents = 2,
1630                         .ops = &clk_rcg_ops,
1631                         .flags = CLK_SET_RATE_GATE,
1632                 },
1633         }
1634 };
1635
1636 static struct clk_branch sdc1_clk = {
1637         .halt_reg = 0x2fc8,
1638         .halt_bit = 6,
1639         .clkr = {
1640                 .enable_reg = 0x282c,
1641                 .enable_mask = BIT(9),
1642                 .hw.init = &(struct clk_init_data){
1643                         .name = "sdc1_clk",
1644                         .parent_names = (const char *[]){ "sdc1_src" },
1645                         .num_parents = 1,
1646                         .ops = &clk_branch_ops,
1647                         .flags = CLK_SET_RATE_PARENT,
1648                 },
1649         },
1650 };
1651
1652 static struct clk_rcg sdc2_src = {
1653         .ns_reg = 0x284c,
1654         .md_reg = 0x2848,
1655         .mn = {
1656                 .mnctr_en_bit = 8,
1657                 .mnctr_reset_bit = 7,
1658                 .mnctr_mode_shift = 5,
1659                 .n_val_shift = 16,
1660                 .m_val_shift = 16,
1661                 .width = 8,
1662         },
1663         .p = {
1664                 .pre_div_shift = 3,
1665                 .pre_div_width = 2,
1666         },
1667         .s = {
1668                 .src_sel_shift = 0,
1669                 .parent_map = gcc_pxo_pll8_map,
1670         },
1671         .freq_tbl = clk_tbl_sdc,
1672         .clkr = {
1673                 .enable_reg = 0x284c,
1674                 .enable_mask = BIT(11),
1675                 .hw.init = &(struct clk_init_data){
1676                         .name = "sdc2_src",
1677                         .parent_names = gcc_pxo_pll8,
1678                         .num_parents = 2,
1679                         .ops = &clk_rcg_ops,
1680                         .flags = CLK_SET_RATE_GATE,
1681                 },
1682         }
1683 };
1684
1685 static struct clk_branch sdc2_clk = {
1686         .halt_reg = 0x2fc8,
1687         .halt_bit = 5,
1688         .clkr = {
1689                 .enable_reg = 0x284c,
1690                 .enable_mask = BIT(9),
1691                 .hw.init = &(struct clk_init_data){
1692                         .name = "sdc2_clk",
1693                         .parent_names = (const char *[]){ "sdc2_src" },
1694                         .num_parents = 1,
1695                         .ops = &clk_branch_ops,
1696                         .flags = CLK_SET_RATE_PARENT,
1697                 },
1698         },
1699 };
1700
1701 static struct clk_rcg sdc3_src = {
1702         .ns_reg = 0x286c,
1703         .md_reg = 0x2868,
1704         .mn = {
1705                 .mnctr_en_bit = 8,
1706                 .mnctr_reset_bit = 7,
1707                 .mnctr_mode_shift = 5,
1708                 .n_val_shift = 16,
1709                 .m_val_shift = 16,
1710                 .width = 8,
1711         },
1712         .p = {
1713                 .pre_div_shift = 3,
1714                 .pre_div_width = 2,
1715         },
1716         .s = {
1717                 .src_sel_shift = 0,
1718                 .parent_map = gcc_pxo_pll8_map,
1719         },
1720         .freq_tbl = clk_tbl_sdc,
1721         .clkr = {
1722                 .enable_reg = 0x286c,
1723                 .enable_mask = BIT(11),
1724                 .hw.init = &(struct clk_init_data){
1725                         .name = "sdc3_src",
1726                         .parent_names = gcc_pxo_pll8,
1727                         .num_parents = 2,
1728                         .ops = &clk_rcg_ops,
1729                         .flags = CLK_SET_RATE_GATE,
1730                 },
1731         }
1732 };
1733
1734 static struct clk_branch sdc3_clk = {
1735         .halt_reg = 0x2fc8,
1736         .halt_bit = 4,
1737         .clkr = {
1738                 .enable_reg = 0x286c,
1739                 .enable_mask = BIT(9),
1740                 .hw.init = &(struct clk_init_data){
1741                         .name = "sdc3_clk",
1742                         .parent_names = (const char *[]){ "sdc3_src" },
1743                         .num_parents = 1,
1744                         .ops = &clk_branch_ops,
1745                         .flags = CLK_SET_RATE_PARENT,
1746                 },
1747         },
1748 };
1749
1750 static struct clk_rcg sdc4_src = {
1751         .ns_reg = 0x288c,
1752         .md_reg = 0x2888,
1753         .mn = {
1754                 .mnctr_en_bit = 8,
1755                 .mnctr_reset_bit = 7,
1756                 .mnctr_mode_shift = 5,
1757                 .n_val_shift = 16,
1758                 .m_val_shift = 16,
1759                 .width = 8,
1760         },
1761         .p = {
1762                 .pre_div_shift = 3,
1763                 .pre_div_width = 2,
1764         },
1765         .s = {
1766                 .src_sel_shift = 0,
1767                 .parent_map = gcc_pxo_pll8_map,
1768         },
1769         .freq_tbl = clk_tbl_sdc,
1770         .clkr = {
1771                 .enable_reg = 0x288c,
1772                 .enable_mask = BIT(11),
1773                 .hw.init = &(struct clk_init_data){
1774                         .name = "sdc4_src",
1775                         .parent_names = gcc_pxo_pll8,
1776                         .num_parents = 2,
1777                         .ops = &clk_rcg_ops,
1778                         .flags = CLK_SET_RATE_GATE,
1779                 },
1780         }
1781 };
1782
1783 static struct clk_branch sdc4_clk = {
1784         .halt_reg = 0x2fc8,
1785         .halt_bit = 3,
1786         .clkr = {
1787                 .enable_reg = 0x288c,
1788                 .enable_mask = BIT(9),
1789                 .hw.init = &(struct clk_init_data){
1790                         .name = "sdc4_clk",
1791                         .parent_names = (const char *[]){ "sdc4_src" },
1792                         .num_parents = 1,
1793                         .ops = &clk_branch_ops,
1794                         .flags = CLK_SET_RATE_PARENT,
1795                 },
1796         },
1797 };
1798
1799 static struct clk_rcg sdc5_src = {
1800         .ns_reg = 0x28ac,
1801         .md_reg = 0x28a8,
1802         .mn = {
1803                 .mnctr_en_bit = 8,
1804                 .mnctr_reset_bit = 7,
1805                 .mnctr_mode_shift = 5,
1806                 .n_val_shift = 16,
1807                 .m_val_shift = 16,
1808                 .width = 8,
1809         },
1810         .p = {
1811                 .pre_div_shift = 3,
1812                 .pre_div_width = 2,
1813         },
1814         .s = {
1815                 .src_sel_shift = 0,
1816                 .parent_map = gcc_pxo_pll8_map,
1817         },
1818         .freq_tbl = clk_tbl_sdc,
1819         .clkr = {
1820                 .enable_reg = 0x28ac,
1821                 .enable_mask = BIT(11),
1822                 .hw.init = &(struct clk_init_data){
1823                         .name = "sdc5_src",
1824                         .parent_names = gcc_pxo_pll8,
1825                         .num_parents = 2,
1826                         .ops = &clk_rcg_ops,
1827                         .flags = CLK_SET_RATE_GATE,
1828                 },
1829         }
1830 };
1831
1832 static struct clk_branch sdc5_clk = {
1833         .halt_reg = 0x2fc8,
1834         .halt_bit = 2,
1835         .clkr = {
1836                 .enable_reg = 0x28ac,
1837                 .enable_mask = BIT(9),
1838                 .hw.init = &(struct clk_init_data){
1839                         .name = "sdc5_clk",
1840                         .parent_names = (const char *[]){ "sdc5_src" },
1841                         .num_parents = 1,
1842                         .ops = &clk_branch_ops,
1843                         .flags = CLK_SET_RATE_PARENT,
1844                 },
1845         },
1846 };
1847
1848 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1849         { 105000, P_PXO,  1, 1, 256 },
1850         { }
1851 };
1852
1853 static struct clk_rcg tsif_ref_src = {
1854         .ns_reg = 0x2710,
1855         .md_reg = 0x270c,
1856         .mn = {
1857                 .mnctr_en_bit = 8,
1858                 .mnctr_reset_bit = 7,
1859                 .mnctr_mode_shift = 5,
1860                 .n_val_shift = 16,
1861                 .m_val_shift = 16,
1862                 .width = 16,
1863         },
1864         .p = {
1865                 .pre_div_shift = 3,
1866                 .pre_div_width = 2,
1867         },
1868         .s = {
1869                 .src_sel_shift = 0,
1870                 .parent_map = gcc_pxo_pll8_map,
1871         },
1872         .freq_tbl = clk_tbl_tsif_ref,
1873         .clkr = {
1874                 .enable_reg = 0x2710,
1875                 .enable_mask = BIT(11),
1876                 .hw.init = &(struct clk_init_data){
1877                         .name = "tsif_ref_src",
1878                         .parent_names = gcc_pxo_pll8,
1879                         .num_parents = 2,
1880                         .ops = &clk_rcg_ops,
1881                         .flags = CLK_SET_RATE_GATE,
1882                 },
1883         }
1884 };
1885
1886 static struct clk_branch tsif_ref_clk = {
1887         .halt_reg = 0x2fd4,
1888         .halt_bit = 5,
1889         .clkr = {
1890                 .enable_reg = 0x2710,
1891                 .enable_mask = BIT(9),
1892                 .hw.init = &(struct clk_init_data){
1893                         .name = "tsif_ref_clk",
1894                         .parent_names = (const char *[]){ "tsif_ref_src" },
1895                         .num_parents = 1,
1896                         .ops = &clk_branch_ops,
1897                         .flags = CLK_SET_RATE_PARENT,
1898                 },
1899         },
1900 };
1901
1902 static const struct freq_tbl clk_tbl_usb[] = {
1903         { 60000000, P_PLL8, 1, 5, 32 },
1904         { }
1905 };
1906
1907 static struct clk_rcg usb_hs1_xcvr_src = {
1908         .ns_reg = 0x290c,
1909         .md_reg = 0x2908,
1910         .mn = {
1911                 .mnctr_en_bit = 8,
1912                 .mnctr_reset_bit = 7,
1913                 .mnctr_mode_shift = 5,
1914                 .n_val_shift = 16,
1915                 .m_val_shift = 16,
1916                 .width = 8,
1917         },
1918         .p = {
1919                 .pre_div_shift = 3,
1920                 .pre_div_width = 2,
1921         },
1922         .s = {
1923                 .src_sel_shift = 0,
1924                 .parent_map = gcc_pxo_pll8_map,
1925         },
1926         .freq_tbl = clk_tbl_usb,
1927         .clkr = {
1928                 .enable_reg = 0x290c,
1929                 .enable_mask = BIT(11),
1930                 .hw.init = &(struct clk_init_data){
1931                         .name = "usb_hs1_xcvr_src",
1932                         .parent_names = gcc_pxo_pll8,
1933                         .num_parents = 2,
1934                         .ops = &clk_rcg_ops,
1935                         .flags = CLK_SET_RATE_GATE,
1936                 },
1937         }
1938 };
1939
1940 static struct clk_branch usb_hs1_xcvr_clk = {
1941         .halt_reg = 0x2fc8,
1942         .halt_bit = 0,
1943         .clkr = {
1944                 .enable_reg = 0x290c,
1945                 .enable_mask = BIT(9),
1946                 .hw.init = &(struct clk_init_data){
1947                         .name = "usb_hs1_xcvr_clk",
1948                         .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
1949                         .num_parents = 1,
1950                         .ops = &clk_branch_ops,
1951                         .flags = CLK_SET_RATE_PARENT,
1952                 },
1953         },
1954 };
1955
1956 static struct clk_rcg usb_hs3_xcvr_src = {
1957         .ns_reg = 0x370c,
1958         .md_reg = 0x3708,
1959         .mn = {
1960                 .mnctr_en_bit = 8,
1961                 .mnctr_reset_bit = 7,
1962                 .mnctr_mode_shift = 5,
1963                 .n_val_shift = 16,
1964                 .m_val_shift = 16,
1965                 .width = 8,
1966         },
1967         .p = {
1968                 .pre_div_shift = 3,
1969                 .pre_div_width = 2,
1970         },
1971         .s = {
1972                 .src_sel_shift = 0,
1973                 .parent_map = gcc_pxo_pll8_map,
1974         },
1975         .freq_tbl = clk_tbl_usb,
1976         .clkr = {
1977                 .enable_reg = 0x370c,
1978                 .enable_mask = BIT(11),
1979                 .hw.init = &(struct clk_init_data){
1980                         .name = "usb_hs3_xcvr_src",
1981                         .parent_names = gcc_pxo_pll8,
1982                         .num_parents = 2,
1983                         .ops = &clk_rcg_ops,
1984                         .flags = CLK_SET_RATE_GATE,
1985                 },
1986         }
1987 };
1988
1989 static struct clk_branch usb_hs3_xcvr_clk = {
1990         .halt_reg = 0x2fc8,
1991         .halt_bit = 30,
1992         .clkr = {
1993                 .enable_reg = 0x370c,
1994                 .enable_mask = BIT(9),
1995                 .hw.init = &(struct clk_init_data){
1996                         .name = "usb_hs3_xcvr_clk",
1997                         .parent_names = (const char *[]){ "usb_hs3_xcvr_src" },
1998                         .num_parents = 1,
1999                         .ops = &clk_branch_ops,
2000                         .flags = CLK_SET_RATE_PARENT,
2001                 },
2002         },
2003 };
2004
2005 static struct clk_rcg usb_hs4_xcvr_src = {
2006         .ns_reg = 0x372c,
2007         .md_reg = 0x3728,
2008         .mn = {
2009                 .mnctr_en_bit = 8,
2010                 .mnctr_reset_bit = 7,
2011                 .mnctr_mode_shift = 5,
2012                 .n_val_shift = 16,
2013                 .m_val_shift = 16,
2014                 .width = 8,
2015         },
2016         .p = {
2017                 .pre_div_shift = 3,
2018                 .pre_div_width = 2,
2019         },
2020         .s = {
2021                 .src_sel_shift = 0,
2022                 .parent_map = gcc_pxo_pll8_map,
2023         },
2024         .freq_tbl = clk_tbl_usb,
2025         .clkr = {
2026                 .enable_reg = 0x372c,
2027                 .enable_mask = BIT(11),
2028                 .hw.init = &(struct clk_init_data){
2029                         .name = "usb_hs4_xcvr_src",
2030                         .parent_names = gcc_pxo_pll8,
2031                         .num_parents = 2,
2032                         .ops = &clk_rcg_ops,
2033                         .flags = CLK_SET_RATE_GATE,
2034                 },
2035         }
2036 };
2037
2038 static struct clk_branch usb_hs4_xcvr_clk = {
2039         .halt_reg = 0x2fc8,
2040         .halt_bit = 2,
2041         .clkr = {
2042                 .enable_reg = 0x372c,
2043                 .enable_mask = BIT(9),
2044                 .hw.init = &(struct clk_init_data){
2045                         .name = "usb_hs4_xcvr_clk",
2046                         .parent_names = (const char *[]){ "usb_hs4_xcvr_src" },
2047                         .num_parents = 1,
2048                         .ops = &clk_branch_ops,
2049                         .flags = CLK_SET_RATE_PARENT,
2050                 },
2051         },
2052 };
2053
2054 static struct clk_rcg usb_hsic_xcvr_fs_src = {
2055         .ns_reg = 0x2928,
2056         .md_reg = 0x2924,
2057         .mn = {
2058                 .mnctr_en_bit = 8,
2059                 .mnctr_reset_bit = 7,
2060                 .mnctr_mode_shift = 5,
2061                 .n_val_shift = 16,
2062                 .m_val_shift = 16,
2063                 .width = 8,
2064         },
2065         .p = {
2066                 .pre_div_shift = 3,
2067                 .pre_div_width = 2,
2068         },
2069         .s = {
2070                 .src_sel_shift = 0,
2071                 .parent_map = gcc_pxo_pll8_map,
2072         },
2073         .freq_tbl = clk_tbl_usb,
2074         .clkr = {
2075                 .enable_reg = 0x2928,
2076                 .enable_mask = BIT(11),
2077                 .hw.init = &(struct clk_init_data){
2078                         .name = "usb_hsic_xcvr_fs_src",
2079                         .parent_names = gcc_pxo_pll8,
2080                         .num_parents = 2,
2081                         .ops = &clk_rcg_ops,
2082                         .flags = CLK_SET_RATE_GATE,
2083                 },
2084         }
2085 };
2086
2087 static const char * const usb_hsic_xcvr_fs_src_p[] = { "usb_hsic_xcvr_fs_src" };
2088
2089 static struct clk_branch usb_hsic_xcvr_fs_clk = {
2090         .halt_reg = 0x2fc8,
2091         .halt_bit = 2,
2092         .clkr = {
2093                 .enable_reg = 0x2928,
2094                 .enable_mask = BIT(9),
2095                 .hw.init = &(struct clk_init_data){
2096                         .name = "usb_hsic_xcvr_fs_clk",
2097                         .parent_names = usb_hsic_xcvr_fs_src_p,
2098                         .num_parents = 1,
2099                         .ops = &clk_branch_ops,
2100                         .flags = CLK_SET_RATE_PARENT,
2101                 },
2102         },
2103 };
2104
2105 static struct clk_branch usb_hsic_system_clk = {
2106         .halt_reg = 0x2fcc,
2107         .halt_bit = 24,
2108         .clkr = {
2109                 .enable_reg = 0x292c,
2110                 .enable_mask = BIT(4),
2111                 .hw.init = &(struct clk_init_data){
2112                         .parent_names = usb_hsic_xcvr_fs_src_p,
2113                         .num_parents = 1,
2114                         .name = "usb_hsic_system_clk",
2115                         .ops = &clk_branch_ops,
2116                         .flags = CLK_SET_RATE_PARENT,
2117                 },
2118         },
2119 };
2120
2121 static struct clk_branch usb_hsic_hsic_clk = {
2122         .halt_reg = 0x2fcc,
2123         .halt_bit = 19,
2124         .clkr = {
2125                 .enable_reg = 0x2b44,
2126                 .enable_mask = BIT(0),
2127                 .hw.init = &(struct clk_init_data){
2128                         .parent_names = (const char *[]){ "pll14_vote" },
2129                         .num_parents = 1,
2130                         .name = "usb_hsic_hsic_clk",
2131                         .ops = &clk_branch_ops,
2132                 },
2133         },
2134 };
2135
2136 static struct clk_branch usb_hsic_hsio_cal_clk = {
2137         .halt_reg = 0x2fcc,
2138         .halt_bit = 23,
2139         .clkr = {
2140                 .enable_reg = 0x2b48,
2141                 .enable_mask = BIT(0),
2142                 .hw.init = &(struct clk_init_data){
2143                         .name = "usb_hsic_hsio_cal_clk",
2144                         .ops = &clk_branch_ops,
2145                 },
2146         },
2147 };
2148
2149 static struct clk_rcg usb_fs1_xcvr_fs_src = {
2150         .ns_reg = 0x2968,
2151         .md_reg = 0x2964,
2152         .mn = {
2153                 .mnctr_en_bit = 8,
2154                 .mnctr_reset_bit = 7,
2155                 .mnctr_mode_shift = 5,
2156                 .n_val_shift = 16,
2157                 .m_val_shift = 16,
2158                 .width = 8,
2159         },
2160         .p = {
2161                 .pre_div_shift = 3,
2162                 .pre_div_width = 2,
2163         },
2164         .s = {
2165                 .src_sel_shift = 0,
2166                 .parent_map = gcc_pxo_pll8_map,
2167         },
2168         .freq_tbl = clk_tbl_usb,
2169         .clkr = {
2170                 .enable_reg = 0x2968,
2171                 .enable_mask = BIT(11),
2172                 .hw.init = &(struct clk_init_data){
2173                         .name = "usb_fs1_xcvr_fs_src",
2174                         .parent_names = gcc_pxo_pll8,
2175                         .num_parents = 2,
2176                         .ops = &clk_rcg_ops,
2177                         .flags = CLK_SET_RATE_GATE,
2178                 },
2179         }
2180 };
2181
2182 static const char * const usb_fs1_xcvr_fs_src_p[] = { "usb_fs1_xcvr_fs_src" };
2183
2184 static struct clk_branch usb_fs1_xcvr_fs_clk = {
2185         .halt_reg = 0x2fcc,
2186         .halt_bit = 15,
2187         .clkr = {
2188                 .enable_reg = 0x2968,
2189                 .enable_mask = BIT(9),
2190                 .hw.init = &(struct clk_init_data){
2191                         .name = "usb_fs1_xcvr_fs_clk",
2192                         .parent_names = usb_fs1_xcvr_fs_src_p,
2193                         .num_parents = 1,
2194                         .ops = &clk_branch_ops,
2195                         .flags = CLK_SET_RATE_PARENT,
2196                 },
2197         },
2198 };
2199
2200 static struct clk_branch usb_fs1_system_clk = {
2201         .halt_reg = 0x2fcc,
2202         .halt_bit = 16,
2203         .clkr = {
2204                 .enable_reg = 0x296c,
2205                 .enable_mask = BIT(4),
2206                 .hw.init = &(struct clk_init_data){
2207                         .parent_names = usb_fs1_xcvr_fs_src_p,
2208                         .num_parents = 1,
2209                         .name = "usb_fs1_system_clk",
2210                         .ops = &clk_branch_ops,
2211                         .flags = CLK_SET_RATE_PARENT,
2212                 },
2213         },
2214 };
2215
2216 static struct clk_rcg usb_fs2_xcvr_fs_src = {
2217         .ns_reg = 0x2988,
2218         .md_reg = 0x2984,
2219         .mn = {
2220                 .mnctr_en_bit = 8,
2221                 .mnctr_reset_bit = 7,
2222                 .mnctr_mode_shift = 5,
2223                 .n_val_shift = 16,
2224                 .m_val_shift = 16,
2225                 .width = 8,
2226         },
2227         .p = {
2228                 .pre_div_shift = 3,
2229                 .pre_div_width = 2,
2230         },
2231         .s = {
2232                 .src_sel_shift = 0,
2233                 .parent_map = gcc_pxo_pll8_map,
2234         },
2235         .freq_tbl = clk_tbl_usb,
2236         .clkr = {
2237                 .enable_reg = 0x2988,
2238                 .enable_mask = BIT(11),
2239                 .hw.init = &(struct clk_init_data){
2240                         .name = "usb_fs2_xcvr_fs_src",
2241                         .parent_names = gcc_pxo_pll8,
2242                         .num_parents = 2,
2243                         .ops = &clk_rcg_ops,
2244                         .flags = CLK_SET_RATE_GATE,
2245                 },
2246         }
2247 };
2248
2249 static const char * const usb_fs2_xcvr_fs_src_p[] = { "usb_fs2_xcvr_fs_src" };
2250
2251 static struct clk_branch usb_fs2_xcvr_fs_clk = {
2252         .halt_reg = 0x2fcc,
2253         .halt_bit = 12,
2254         .clkr = {
2255                 .enable_reg = 0x2988,
2256                 .enable_mask = BIT(9),
2257                 .hw.init = &(struct clk_init_data){
2258                         .name = "usb_fs2_xcvr_fs_clk",
2259                         .parent_names = usb_fs2_xcvr_fs_src_p,
2260                         .num_parents = 1,
2261                         .ops = &clk_branch_ops,
2262                         .flags = CLK_SET_RATE_PARENT,
2263                 },
2264         },
2265 };
2266
2267 static struct clk_branch usb_fs2_system_clk = {
2268         .halt_reg = 0x2fcc,
2269         .halt_bit = 13,
2270         .clkr = {
2271                 .enable_reg = 0x298c,
2272                 .enable_mask = BIT(4),
2273                 .hw.init = &(struct clk_init_data){
2274                         .name = "usb_fs2_system_clk",
2275                         .parent_names = usb_fs2_xcvr_fs_src_p,
2276                         .num_parents = 1,
2277                         .ops = &clk_branch_ops,
2278                         .flags = CLK_SET_RATE_PARENT,
2279                 },
2280         },
2281 };
2282
2283 static struct clk_branch ce1_core_clk = {
2284         .hwcg_reg = 0x2724,
2285         .hwcg_bit = 6,
2286         .halt_reg = 0x2fd4,
2287         .halt_bit = 27,
2288         .clkr = {
2289                 .enable_reg = 0x2724,
2290                 .enable_mask = BIT(4),
2291                 .hw.init = &(struct clk_init_data){
2292                         .name = "ce1_core_clk",
2293                         .ops = &clk_branch_ops,
2294                 },
2295         },
2296 };
2297
2298 static struct clk_branch ce1_h_clk = {
2299         .halt_reg = 0x2fd4,
2300         .halt_bit = 1,
2301         .clkr = {
2302                 .enable_reg = 0x2720,
2303                 .enable_mask = BIT(4),
2304                 .hw.init = &(struct clk_init_data){
2305                         .name = "ce1_h_clk",
2306                         .ops = &clk_branch_ops,
2307                 },
2308         },
2309 };
2310
2311 static struct clk_branch dma_bam_h_clk = {
2312         .hwcg_reg = 0x25c0,
2313         .hwcg_bit = 6,
2314         .halt_reg = 0x2fc8,
2315         .halt_bit = 12,
2316         .clkr = {
2317                 .enable_reg = 0x25c0,
2318                 .enable_mask = BIT(4),
2319                 .hw.init = &(struct clk_init_data){
2320                         .name = "dma_bam_h_clk",
2321                         .ops = &clk_branch_ops,
2322                 },
2323         },
2324 };
2325
2326 static struct clk_branch gsbi1_h_clk = {
2327         .hwcg_reg = 0x29c0,
2328         .hwcg_bit = 6,
2329         .halt_reg = 0x2fcc,
2330         .halt_bit = 11,
2331         .clkr = {
2332                 .enable_reg = 0x29c0,
2333                 .enable_mask = BIT(4),
2334                 .hw.init = &(struct clk_init_data){
2335                         .name = "gsbi1_h_clk",
2336                         .ops = &clk_branch_ops,
2337                 },
2338         },
2339 };
2340
2341 static struct clk_branch gsbi2_h_clk = {
2342         .hwcg_reg = 0x29e0,
2343         .hwcg_bit = 6,
2344         .halt_reg = 0x2fcc,
2345         .halt_bit = 7,
2346         .clkr = {
2347                 .enable_reg = 0x29e0,
2348                 .enable_mask = BIT(4),
2349                 .hw.init = &(struct clk_init_data){
2350                         .name = "gsbi2_h_clk",
2351                         .ops = &clk_branch_ops,
2352                 },
2353         },
2354 };
2355
2356 static struct clk_branch gsbi3_h_clk = {
2357         .hwcg_reg = 0x2a00,
2358         .hwcg_bit = 6,
2359         .halt_reg = 0x2fcc,
2360         .halt_bit = 3,
2361         .clkr = {
2362                 .enable_reg = 0x2a00,
2363                 .enable_mask = BIT(4),
2364                 .hw.init = &(struct clk_init_data){
2365                         .name = "gsbi3_h_clk",
2366                         .ops = &clk_branch_ops,
2367                 },
2368         },
2369 };
2370
2371 static struct clk_branch gsbi4_h_clk = {
2372         .hwcg_reg = 0x2a20,
2373         .hwcg_bit = 6,
2374         .halt_reg = 0x2fd0,
2375         .halt_bit = 27,
2376         .clkr = {
2377                 .enable_reg = 0x2a20,
2378                 .enable_mask = BIT(4),
2379                 .hw.init = &(struct clk_init_data){
2380                         .name = "gsbi4_h_clk",
2381                         .ops = &clk_branch_ops,
2382                 },
2383         },
2384 };
2385
2386 static struct clk_branch gsbi5_h_clk = {
2387         .hwcg_reg = 0x2a40,
2388         .hwcg_bit = 6,
2389         .halt_reg = 0x2fd0,
2390         .halt_bit = 23,
2391         .clkr = {
2392                 .enable_reg = 0x2a40,
2393                 .enable_mask = BIT(4),
2394                 .hw.init = &(struct clk_init_data){
2395                         .name = "gsbi5_h_clk",
2396                         .ops = &clk_branch_ops,
2397                 },
2398         },
2399 };
2400
2401 static struct clk_branch gsbi6_h_clk = {
2402         .hwcg_reg = 0x2a60,
2403         .hwcg_bit = 6,
2404         .halt_reg = 0x2fd0,
2405         .halt_bit = 19,
2406         .clkr = {
2407                 .enable_reg = 0x2a60,
2408                 .enable_mask = BIT(4),
2409                 .hw.init = &(struct clk_init_data){
2410                         .name = "gsbi6_h_clk",
2411                         .ops = &clk_branch_ops,
2412                 },
2413         },
2414 };
2415
2416 static struct clk_branch gsbi7_h_clk = {
2417         .hwcg_reg = 0x2a80,
2418         .hwcg_bit = 6,
2419         .halt_reg = 0x2fd0,
2420         .halt_bit = 15,
2421         .clkr = {
2422                 .enable_reg = 0x2a80,
2423                 .enable_mask = BIT(4),
2424                 .hw.init = &(struct clk_init_data){
2425                         .name = "gsbi7_h_clk",
2426                         .ops = &clk_branch_ops,
2427                 },
2428         },
2429 };
2430
2431 static struct clk_branch gsbi8_h_clk = {
2432         .hwcg_reg = 0x2aa0,
2433         .hwcg_bit = 6,
2434         .halt_reg = 0x2fd0,
2435         .halt_bit = 11,
2436         .clkr = {
2437                 .enable_reg = 0x2aa0,
2438                 .enable_mask = BIT(4),
2439                 .hw.init = &(struct clk_init_data){
2440                         .name = "gsbi8_h_clk",
2441                         .ops = &clk_branch_ops,
2442                 },
2443         },
2444 };
2445
2446 static struct clk_branch gsbi9_h_clk = {
2447         .hwcg_reg = 0x2ac0,
2448         .hwcg_bit = 6,
2449         .halt_reg = 0x2fd0,
2450         .halt_bit = 7,
2451         .clkr = {
2452                 .enable_reg = 0x2ac0,
2453                 .enable_mask = BIT(4),
2454                 .hw.init = &(struct clk_init_data){
2455                         .name = "gsbi9_h_clk",
2456                         .ops = &clk_branch_ops,
2457                 },
2458         },
2459 };
2460
2461 static struct clk_branch gsbi10_h_clk = {
2462         .hwcg_reg = 0x2ae0,
2463         .hwcg_bit = 6,
2464         .halt_reg = 0x2fd0,
2465         .halt_bit = 3,
2466         .clkr = {
2467                 .enable_reg = 0x2ae0,
2468                 .enable_mask = BIT(4),
2469                 .hw.init = &(struct clk_init_data){
2470                         .name = "gsbi10_h_clk",
2471                         .ops = &clk_branch_ops,
2472                 },
2473         },
2474 };
2475
2476 static struct clk_branch gsbi11_h_clk = {
2477         .hwcg_reg = 0x2b00,
2478         .hwcg_bit = 6,
2479         .halt_reg = 0x2fd4,
2480         .halt_bit = 18,
2481         .clkr = {
2482                 .enable_reg = 0x2b00,
2483                 .enable_mask = BIT(4),
2484                 .hw.init = &(struct clk_init_data){
2485                         .name = "gsbi11_h_clk",
2486                         .ops = &clk_branch_ops,
2487                 },
2488         },
2489 };
2490
2491 static struct clk_branch gsbi12_h_clk = {
2492         .hwcg_reg = 0x2b20,
2493         .hwcg_bit = 6,
2494         .halt_reg = 0x2fd4,
2495         .halt_bit = 14,
2496         .clkr = {
2497                 .enable_reg = 0x2b20,
2498                 .enable_mask = BIT(4),
2499                 .hw.init = &(struct clk_init_data){
2500                         .name = "gsbi12_h_clk",
2501                         .ops = &clk_branch_ops,
2502                 },
2503         },
2504 };
2505
2506 static struct clk_branch tsif_h_clk = {
2507         .hwcg_reg = 0x2700,
2508         .hwcg_bit = 6,
2509         .halt_reg = 0x2fd4,
2510         .halt_bit = 7,
2511         .clkr = {
2512                 .enable_reg = 0x2700,
2513                 .enable_mask = BIT(4),
2514                 .hw.init = &(struct clk_init_data){
2515                         .name = "tsif_h_clk",
2516                         .ops = &clk_branch_ops,
2517                 },
2518         },
2519 };
2520
2521 static struct clk_branch usb_fs1_h_clk = {
2522         .halt_reg = 0x2fcc,
2523         .halt_bit = 17,
2524         .clkr = {
2525                 .enable_reg = 0x2960,
2526                 .enable_mask = BIT(4),
2527                 .hw.init = &(struct clk_init_data){
2528                         .name = "usb_fs1_h_clk",
2529                         .ops = &clk_branch_ops,
2530                 },
2531         },
2532 };
2533
2534 static struct clk_branch usb_fs2_h_clk = {
2535         .halt_reg = 0x2fcc,
2536         .halt_bit = 14,
2537         .clkr = {
2538                 .enable_reg = 0x2980,
2539                 .enable_mask = BIT(4),
2540                 .hw.init = &(struct clk_init_data){
2541                         .name = "usb_fs2_h_clk",
2542                         .ops = &clk_branch_ops,
2543                 },
2544         },
2545 };
2546
2547 static struct clk_branch usb_hs1_h_clk = {
2548         .hwcg_reg = 0x2900,
2549         .hwcg_bit = 6,
2550         .halt_reg = 0x2fc8,
2551         .halt_bit = 1,
2552         .clkr = {
2553                 .enable_reg = 0x2900,
2554                 .enable_mask = BIT(4),
2555                 .hw.init = &(struct clk_init_data){
2556                         .name = "usb_hs1_h_clk",
2557                         .ops = &clk_branch_ops,
2558                 },
2559         },
2560 };
2561
2562 static struct clk_branch usb_hs3_h_clk = {
2563         .halt_reg = 0x2fc8,
2564         .halt_bit = 31,
2565         .clkr = {
2566                 .enable_reg = 0x3700,
2567                 .enable_mask = BIT(4),
2568                 .hw.init = &(struct clk_init_data){
2569                         .name = "usb_hs3_h_clk",
2570                         .ops = &clk_branch_ops,
2571                 },
2572         },
2573 };
2574
2575 static struct clk_branch usb_hs4_h_clk = {
2576         .halt_reg = 0x2fc8,
2577         .halt_bit = 7,
2578         .clkr = {
2579                 .enable_reg = 0x3720,
2580                 .enable_mask = BIT(4),
2581                 .hw.init = &(struct clk_init_data){
2582                         .name = "usb_hs4_h_clk",
2583                         .ops = &clk_branch_ops,
2584                 },
2585         },
2586 };
2587
2588 static struct clk_branch usb_hsic_h_clk = {
2589         .halt_reg = 0x2fcc,
2590         .halt_bit = 28,
2591         .clkr = {
2592                 .enable_reg = 0x2920,
2593                 .enable_mask = BIT(4),
2594                 .hw.init = &(struct clk_init_data){
2595                         .name = "usb_hsic_h_clk",
2596                         .ops = &clk_branch_ops,
2597                 },
2598         },
2599 };
2600
2601 static struct clk_branch sdc1_h_clk = {
2602         .hwcg_reg = 0x2820,
2603         .hwcg_bit = 6,
2604         .halt_reg = 0x2fc8,
2605         .halt_bit = 11,
2606         .clkr = {
2607                 .enable_reg = 0x2820,
2608                 .enable_mask = BIT(4),
2609                 .hw.init = &(struct clk_init_data){
2610                         .name = "sdc1_h_clk",
2611                         .ops = &clk_branch_ops,
2612                 },
2613         },
2614 };
2615
2616 static struct clk_branch sdc2_h_clk = {
2617         .hwcg_reg = 0x2840,
2618         .hwcg_bit = 6,
2619         .halt_reg = 0x2fc8,
2620         .halt_bit = 10,
2621         .clkr = {
2622                 .enable_reg = 0x2840,
2623                 .enable_mask = BIT(4),
2624                 .hw.init = &(struct clk_init_data){
2625                         .name = "sdc2_h_clk",
2626                         .ops = &clk_branch_ops,
2627                 },
2628         },
2629 };
2630
2631 static struct clk_branch sdc3_h_clk = {
2632         .hwcg_reg = 0x2860,
2633         .hwcg_bit = 6,
2634         .halt_reg = 0x2fc8,
2635         .halt_bit = 9,
2636         .clkr = {
2637                 .enable_reg = 0x2860,
2638                 .enable_mask = BIT(4),
2639                 .hw.init = &(struct clk_init_data){
2640                         .name = "sdc3_h_clk",
2641                         .ops = &clk_branch_ops,
2642                 },
2643         },
2644 };
2645
2646 static struct clk_branch sdc4_h_clk = {
2647         .hwcg_reg = 0x2880,
2648         .hwcg_bit = 6,
2649         .halt_reg = 0x2fc8,
2650         .halt_bit = 8,
2651         .clkr = {
2652                 .enable_reg = 0x2880,
2653                 .enable_mask = BIT(4),
2654                 .hw.init = &(struct clk_init_data){
2655                         .name = "sdc4_h_clk",
2656                         .ops = &clk_branch_ops,
2657                 },
2658         },
2659 };
2660
2661 static struct clk_branch sdc5_h_clk = {
2662         .hwcg_reg = 0x28a0,
2663         .hwcg_bit = 6,
2664         .halt_reg = 0x2fc8,
2665         .halt_bit = 7,
2666         .clkr = {
2667                 .enable_reg = 0x28a0,
2668                 .enable_mask = BIT(4),
2669                 .hw.init = &(struct clk_init_data){
2670                         .name = "sdc5_h_clk",
2671                         .ops = &clk_branch_ops,
2672                 },
2673         },
2674 };
2675
2676 static struct clk_branch adm0_clk = {
2677         .halt_reg = 0x2fdc,
2678         .halt_check = BRANCH_HALT_VOTED,
2679         .halt_bit = 14,
2680         .clkr = {
2681                 .enable_reg = 0x3080,
2682                 .enable_mask = BIT(2),
2683                 .hw.init = &(struct clk_init_data){
2684                         .name = "adm0_clk",
2685                         .ops = &clk_branch_ops,
2686                 },
2687         },
2688 };
2689
2690 static struct clk_branch adm0_pbus_clk = {
2691         .hwcg_reg = 0x2208,
2692         .hwcg_bit = 6,
2693         .halt_reg = 0x2fdc,
2694         .halt_check = BRANCH_HALT_VOTED,
2695         .halt_bit = 13,
2696         .clkr = {
2697                 .enable_reg = 0x3080,
2698                 .enable_mask = BIT(3),
2699                 .hw.init = &(struct clk_init_data){
2700                         .name = "adm0_pbus_clk",
2701                         .ops = &clk_branch_ops,
2702                 },
2703         },
2704 };
2705
2706 static struct freq_tbl clk_tbl_ce3[] = {
2707         { 48000000, P_PLL8, 8 },
2708         { 100000000, P_PLL3, 12 },
2709         { 120000000, P_PLL3, 10 },
2710         { }
2711 };
2712
2713 static struct clk_rcg ce3_src = {
2714         .ns_reg = 0x36c0,
2715         .p = {
2716                 .pre_div_shift = 3,
2717                 .pre_div_width = 4,
2718         },
2719         .s = {
2720                 .src_sel_shift = 0,
2721                 .parent_map = gcc_pxo_pll8_pll3_map,
2722         },
2723         .freq_tbl = clk_tbl_ce3,
2724         .clkr = {
2725                 .enable_reg = 0x36c0,
2726                 .enable_mask = BIT(7),
2727                 .hw.init = &(struct clk_init_data){
2728                         .name = "ce3_src",
2729                         .parent_names = gcc_pxo_pll8_pll3,
2730                         .num_parents = 3,
2731                         .ops = &clk_rcg_ops,
2732                         .flags = CLK_SET_RATE_GATE,
2733                 },
2734         },
2735 };
2736
2737 static struct clk_branch ce3_core_clk = {
2738         .halt_reg = 0x2fdc,
2739         .halt_bit = 5,
2740         .clkr = {
2741                 .enable_reg = 0x36cc,
2742                 .enable_mask = BIT(4),
2743                 .hw.init = &(struct clk_init_data){
2744                         .name = "ce3_core_clk",
2745                         .parent_names = (const char *[]){ "ce3_src" },
2746                         .num_parents = 1,
2747                         .ops = &clk_branch_ops,
2748                         .flags = CLK_SET_RATE_PARENT,
2749                 },
2750         },
2751 };
2752
2753 static struct clk_branch ce3_h_clk = {
2754         .halt_reg = 0x2fc4,
2755         .halt_bit = 16,
2756         .clkr = {
2757                 .enable_reg = 0x36c4,
2758                 .enable_mask = BIT(4),
2759                 .hw.init = &(struct clk_init_data){
2760                         .name = "ce3_h_clk",
2761                         .parent_names = (const char *[]){ "ce3_src" },
2762                         .num_parents = 1,
2763                         .ops = &clk_branch_ops,
2764                         .flags = CLK_SET_RATE_PARENT,
2765                 },
2766         },
2767 };
2768
2769 static const struct freq_tbl clk_tbl_sata_ref[] = {
2770         { 48000000, P_PLL8, 8, 0, 0 },
2771         { 100000000, P_PLL3, 12, 0, 0 },
2772         { }
2773 };
2774
2775 static struct clk_rcg sata_clk_src = {
2776         .ns_reg = 0x2c08,
2777         .p = {
2778                 .pre_div_shift = 3,
2779                 .pre_div_width = 4,
2780         },
2781         .s = {
2782                 .src_sel_shift = 0,
2783                 .parent_map = gcc_pxo_pll8_pll3_map,
2784         },
2785         .freq_tbl = clk_tbl_sata_ref,
2786         .clkr = {
2787                 .enable_reg = 0x2c08,
2788                 .enable_mask = BIT(7),
2789                 .hw.init = &(struct clk_init_data){
2790                         .name = "sata_clk_src",
2791                         .parent_names = gcc_pxo_pll8_pll3,
2792                         .num_parents = 3,
2793                         .ops = &clk_rcg_ops,
2794                         .flags = CLK_SET_RATE_GATE,
2795                 },
2796         },
2797 };
2798
2799 static struct clk_branch sata_rxoob_clk = {
2800         .halt_reg = 0x2fdc,
2801         .halt_bit = 26,
2802         .clkr = {
2803                 .enable_reg = 0x2c0c,
2804                 .enable_mask = BIT(4),
2805                 .hw.init = &(struct clk_init_data){
2806                         .name = "sata_rxoob_clk",
2807                         .parent_names = (const char *[]){ "sata_clk_src" },
2808                         .num_parents = 1,
2809                         .ops = &clk_branch_ops,
2810                         .flags = CLK_SET_RATE_PARENT,
2811                 },
2812         },
2813 };
2814
2815 static struct clk_branch sata_pmalive_clk = {
2816         .halt_reg = 0x2fdc,
2817         .halt_bit = 25,
2818         .clkr = {
2819                 .enable_reg = 0x2c10,
2820                 .enable_mask = BIT(4),
2821                 .hw.init = &(struct clk_init_data){
2822                         .name = "sata_pmalive_clk",
2823                         .parent_names = (const char *[]){ "sata_clk_src" },
2824                         .num_parents = 1,
2825                         .ops = &clk_branch_ops,
2826                         .flags = CLK_SET_RATE_PARENT,
2827                 },
2828         },
2829 };
2830
2831 static struct clk_branch sata_phy_ref_clk = {
2832         .halt_reg = 0x2fdc,
2833         .halt_bit = 24,
2834         .clkr = {
2835                 .enable_reg = 0x2c14,
2836                 .enable_mask = BIT(4),
2837                 .hw.init = &(struct clk_init_data){
2838                         .name = "sata_phy_ref_clk",
2839                         .parent_names = (const char *[]){ "pxo" },
2840                         .num_parents = 1,
2841                         .ops = &clk_branch_ops,
2842                 },
2843         },
2844 };
2845
2846 static struct clk_branch sata_a_clk = {
2847         .halt_reg = 0x2fc0,
2848         .halt_bit = 12,
2849         .clkr = {
2850                 .enable_reg = 0x2c20,
2851                 .enable_mask = BIT(4),
2852                 .hw.init = &(struct clk_init_data){
2853                         .name = "sata_a_clk",
2854                         .ops = &clk_branch_ops,
2855                 },
2856         },
2857 };
2858
2859 static struct clk_branch sata_h_clk = {
2860         .halt_reg = 0x2fdc,
2861         .halt_bit = 27,
2862         .clkr = {
2863                 .enable_reg = 0x2c00,
2864                 .enable_mask = BIT(4),
2865                 .hw.init = &(struct clk_init_data){
2866                         .name = "sata_h_clk",
2867                         .ops = &clk_branch_ops,
2868                 },
2869         },
2870 };
2871
2872 static struct clk_branch sfab_sata_s_h_clk = {
2873         .halt_reg = 0x2fc4,
2874         .halt_bit = 14,
2875         .clkr = {
2876                 .enable_reg = 0x2480,
2877                 .enable_mask = BIT(4),
2878                 .hw.init = &(struct clk_init_data){
2879                         .name = "sfab_sata_s_h_clk",
2880                         .ops = &clk_branch_ops,
2881                 },
2882         },
2883 };
2884
2885 static struct clk_branch sata_phy_cfg_clk = {
2886         .halt_reg = 0x2fcc,
2887         .halt_bit = 12,
2888         .clkr = {
2889                 .enable_reg = 0x2c40,
2890                 .enable_mask = BIT(4),
2891                 .hw.init = &(struct clk_init_data){
2892                         .name = "sata_phy_cfg_clk",
2893                         .ops = &clk_branch_ops,
2894                 },
2895         },
2896 };
2897
2898 static struct clk_branch pcie_phy_ref_clk = {
2899         .halt_reg = 0x2fdc,
2900         .halt_bit = 29,
2901         .clkr = {
2902                 .enable_reg = 0x22d0,
2903                 .enable_mask = BIT(4),
2904                 .hw.init = &(struct clk_init_data){
2905                         .name = "pcie_phy_ref_clk",
2906                         .ops = &clk_branch_ops,
2907                 },
2908         },
2909 };
2910
2911 static struct clk_branch pcie_h_clk = {
2912         .halt_reg = 0x2fd4,
2913         .halt_bit = 8,
2914         .clkr = {
2915                 .enable_reg = 0x22cc,
2916                 .enable_mask = BIT(4),
2917                 .hw.init = &(struct clk_init_data){
2918                         .name = "pcie_h_clk",
2919                         .ops = &clk_branch_ops,
2920                 },
2921         },
2922 };
2923
2924 static struct clk_branch pcie_a_clk = {
2925         .halt_reg = 0x2fc0,
2926         .halt_bit = 13,
2927         .clkr = {
2928                 .enable_reg = 0x22c0,
2929                 .enable_mask = BIT(4),
2930                 .hw.init = &(struct clk_init_data){
2931                         .name = "pcie_a_clk",
2932                         .ops = &clk_branch_ops,
2933                 },
2934         },
2935 };
2936
2937 static struct clk_branch pmic_arb0_h_clk = {
2938         .halt_reg = 0x2fd8,
2939         .halt_check = BRANCH_HALT_VOTED,
2940         .halt_bit = 22,
2941         .clkr = {
2942                 .enable_reg = 0x3080,
2943                 .enable_mask = BIT(8),
2944                 .hw.init = &(struct clk_init_data){
2945                         .name = "pmic_arb0_h_clk",
2946                         .ops = &clk_branch_ops,
2947                 },
2948         },
2949 };
2950
2951 static struct clk_branch pmic_arb1_h_clk = {
2952         .halt_reg = 0x2fd8,
2953         .halt_check = BRANCH_HALT_VOTED,
2954         .halt_bit = 21,
2955         .clkr = {
2956                 .enable_reg = 0x3080,
2957                 .enable_mask = BIT(9),
2958                 .hw.init = &(struct clk_init_data){
2959                         .name = "pmic_arb1_h_clk",
2960                         .ops = &clk_branch_ops,
2961                 },
2962         },
2963 };
2964
2965 static struct clk_branch pmic_ssbi2_clk = {
2966         .halt_reg = 0x2fd8,
2967         .halt_check = BRANCH_HALT_VOTED,
2968         .halt_bit = 23,
2969         .clkr = {
2970                 .enable_reg = 0x3080,
2971                 .enable_mask = BIT(7),
2972                 .hw.init = &(struct clk_init_data){
2973                         .name = "pmic_ssbi2_clk",
2974                         .ops = &clk_branch_ops,
2975                 },
2976         },
2977 };
2978
2979 static struct clk_branch rpm_msg_ram_h_clk = {
2980         .hwcg_reg = 0x27e0,
2981         .hwcg_bit = 6,
2982         .halt_reg = 0x2fd8,
2983         .halt_check = BRANCH_HALT_VOTED,
2984         .halt_bit = 12,
2985         .clkr = {
2986                 .enable_reg = 0x3080,
2987                 .enable_mask = BIT(6),
2988                 .hw.init = &(struct clk_init_data){
2989                         .name = "rpm_msg_ram_h_clk",
2990                         .ops = &clk_branch_ops,
2991                 },
2992         },
2993 };
2994
2995 static struct clk_regmap *gcc_msm8960_clks[] = {
2996         [PLL3] = &pll3.clkr,
2997         [PLL4_VOTE] = &pll4_vote,
2998         [PLL8] = &pll8.clkr,
2999         [PLL8_VOTE] = &pll8_vote,
3000         [PLL14] = &pll14.clkr,
3001         [PLL14_VOTE] = &pll14_vote,
3002         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3003         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3004         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3005         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3006         [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3007         [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3008         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3009         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3010         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3011         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3012         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3013         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3014         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3015         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3016         [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
3017         [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
3018         [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
3019         [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
3020         [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
3021         [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
3022         [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
3023         [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
3024         [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
3025         [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
3026         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3027         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3028         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3029         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3030         [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3031         [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3032         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3033         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3034         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3035         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3036         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3037         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3038         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3039         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3040         [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
3041         [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
3042         [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
3043         [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
3044         [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
3045         [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
3046         [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
3047         [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
3048         [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
3049         [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
3050         [GP0_SRC] = &gp0_src.clkr,
3051         [GP0_CLK] = &gp0_clk.clkr,
3052         [GP1_SRC] = &gp1_src.clkr,
3053         [GP1_CLK] = &gp1_clk.clkr,
3054         [GP2_SRC] = &gp2_src.clkr,
3055         [GP2_CLK] = &gp2_clk.clkr,
3056         [PMEM_A_CLK] = &pmem_clk.clkr,
3057         [PRNG_SRC] = &prng_src.clkr,
3058         [PRNG_CLK] = &prng_clk.clkr,
3059         [SDC1_SRC] = &sdc1_src.clkr,
3060         [SDC1_CLK] = &sdc1_clk.clkr,
3061         [SDC2_SRC] = &sdc2_src.clkr,
3062         [SDC2_CLK] = &sdc2_clk.clkr,
3063         [SDC3_SRC] = &sdc3_src.clkr,
3064         [SDC3_CLK] = &sdc3_clk.clkr,
3065         [SDC4_SRC] = &sdc4_src.clkr,
3066         [SDC4_CLK] = &sdc4_clk.clkr,
3067         [SDC5_SRC] = &sdc5_src.clkr,
3068         [SDC5_CLK] = &sdc5_clk.clkr,
3069         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3070         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3071         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3072         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3073         [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3074         [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3075         [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3076         [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3077         [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3078         [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3079         [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3080         [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3081         [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
3082         [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
3083         [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
3084         [CE1_CORE_CLK] = &ce1_core_clk.clkr,
3085         [CE1_H_CLK] = &ce1_h_clk.clkr,
3086         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3087         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3088         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3089         [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3090         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3091         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3092         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3093         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3094         [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
3095         [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
3096         [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
3097         [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
3098         [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
3099         [TSIF_H_CLK] = &tsif_h_clk.clkr,
3100         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3101         [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
3102         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3103         [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3104         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3105         [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3106         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3107         [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3108         [SDC5_H_CLK] = &sdc5_h_clk.clkr,
3109         [ADM0_CLK] = &adm0_clk.clkr,
3110         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3111         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3112         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3113         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3114         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3115 };
3116
3117 static const struct qcom_reset_map gcc_msm8960_resets[] = {
3118         [SFAB_MSS_Q6_SW_RESET] = { 0x2040, 7 },
3119         [SFAB_MSS_Q6_FW_RESET] = { 0x2044, 7 },
3120         [QDSS_STM_RESET] = { 0x2060, 6 },
3121         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3122         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3123         [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3124         [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3125         [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3126         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3127         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3128         [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3129         [ADM0_C2_RESET] = { 0x220c, 4},
3130         [ADM0_C1_RESET] = { 0x220c, 3},
3131         [ADM0_C0_RESET] = { 0x220c, 2},
3132         [ADM0_PBUS_RESET] = { 0x220c, 1 },
3133         [ADM0_RESET] = { 0x220c },
3134         [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3135         [QDSS_POR_RESET] = { 0x2260, 4 },
3136         [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3137         [QDSS_HRESET_RESET] = { 0x2260, 2 },
3138         [QDSS_AXI_RESET] = { 0x2260, 1 },
3139         [QDSS_DBG_RESET] = { 0x2260 },
3140         [PCIE_A_RESET] = { 0x22c0, 7 },
3141         [PCIE_AUX_RESET] = { 0x22c8, 7 },
3142         [PCIE_H_RESET] = { 0x22d0, 7 },
3143         [SFAB_PCIE_M_RESET] = { 0x22d4, 1 },
3144         [SFAB_PCIE_S_RESET] = { 0x22d4 },
3145         [SFAB_MSS_M_RESET] = { 0x2340, 7 },
3146         [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3147         [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3148         [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3149         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3150         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3151         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3152         [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3153         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3154         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3155         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3156         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3157         [DFAB_ARB0_RESET] = { 0x2560, 7 },
3158         [DFAB_ARB1_RESET] = { 0x2564, 7 },
3159         [PPSS_PROC_RESET] = { 0x2594, 1 },
3160         [PPSS_RESET] = { 0x2594},
3161         [DMA_BAM_RESET] = { 0x25c0, 7 },
3162         [SPS_TIC_H_RESET] = { 0x2600, 7 },
3163         [SLIMBUS_H_RESET] = { 0x2620, 7 },
3164         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3165         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3166         [TSIF_H_RESET] = { 0x2700, 7 },
3167         [CE1_H_RESET] = { 0x2720, 7 },
3168         [CE1_CORE_RESET] = { 0x2724, 7 },
3169         [CE1_SLEEP_RESET] = { 0x2728, 7 },
3170         [CE2_H_RESET] = { 0x2740, 7 },
3171         [CE2_CORE_RESET] = { 0x2744, 7 },
3172         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3173         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3174         [RPM_PROC_RESET] = { 0x27c0, 7 },
3175         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3176         [SDC1_RESET] = { 0x2830 },
3177         [SDC2_RESET] = { 0x2850 },
3178         [SDC3_RESET] = { 0x2870 },
3179         [SDC4_RESET] = { 0x2890 },
3180         [SDC5_RESET] = { 0x28b0 },
3181         [DFAB_A2_RESET] = { 0x28c0, 7 },
3182         [USB_HS1_RESET] = { 0x2910 },
3183         [USB_HSIC_RESET] = { 0x2934 },
3184         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3185         [USB_FS1_RESET] = { 0x2974 },
3186         [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
3187         [USB_FS2_RESET] = { 0x2994 },
3188         [GSBI1_RESET] = { 0x29dc },
3189         [GSBI2_RESET] = { 0x29fc },
3190         [GSBI3_RESET] = { 0x2a1c },
3191         [GSBI4_RESET] = { 0x2a3c },
3192         [GSBI5_RESET] = { 0x2a5c },
3193         [GSBI6_RESET] = { 0x2a7c },
3194         [GSBI7_RESET] = { 0x2a9c },
3195         [GSBI8_RESET] = { 0x2abc },
3196         [GSBI9_RESET] = { 0x2adc },
3197         [GSBI10_RESET] = { 0x2afc },
3198         [GSBI11_RESET] = { 0x2b1c },
3199         [GSBI12_RESET] = { 0x2b3c },
3200         [SPDM_RESET] = { 0x2b6c },
3201         [TLMM_H_RESET] = { 0x2ba0, 7 },
3202         [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
3203         [MSS_SLP_RESET] = { 0x2c60, 7 },
3204         [MSS_Q6SW_JTAG_RESET] = { 0x2c68, 7 },
3205         [MSS_Q6FW_JTAG_RESET] = { 0x2c6c, 7 },
3206         [MSS_RESET] = { 0x2c64 },
3207         [SATA_H_RESET] = { 0x2c80, 7 },
3208         [SATA_RXOOB_RESE] = { 0x2c8c, 7 },
3209         [SATA_PMALIVE_RESET] = { 0x2c90, 7 },
3210         [SATA_SFAB_M_RESET] = { 0x2c98, 7 },
3211         [TSSC_RESET] = { 0x2ca0, 7 },
3212         [PDM_RESET] = { 0x2cc0, 12 },
3213         [MPM_H_RESET] = { 0x2da0, 7 },
3214         [MPM_RESET] = { 0x2da4 },
3215         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3216         [PRNG_RESET] = { 0x2e80, 12 },
3217         [RIVA_RESET] = { 0x35e0 },
3218 };
3219
3220 static struct clk_regmap *gcc_apq8064_clks[] = {
3221         [PLL3] = &pll3.clkr,
3222         [PLL4_VOTE] = &pll4_vote,
3223         [PLL8] = &pll8.clkr,
3224         [PLL8_VOTE] = &pll8_vote,
3225         [PLL14] = &pll14.clkr,
3226         [PLL14_VOTE] = &pll14_vote,
3227         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3228         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3229         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3230         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3231         [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
3232         [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
3233         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
3234         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
3235         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
3236         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
3237         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
3238         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
3239         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
3240         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
3241         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
3242         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
3243         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
3244         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
3245         [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
3246         [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
3247         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
3248         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
3249         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
3250         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
3251         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
3252         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
3253         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
3254         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
3255         [GP0_SRC] = &gp0_src.clkr,
3256         [GP0_CLK] = &gp0_clk.clkr,
3257         [GP1_SRC] = &gp1_src.clkr,
3258         [GP1_CLK] = &gp1_clk.clkr,
3259         [GP2_SRC] = &gp2_src.clkr,
3260         [GP2_CLK] = &gp2_clk.clkr,
3261         [PMEM_A_CLK] = &pmem_clk.clkr,
3262         [PRNG_SRC] = &prng_src.clkr,
3263         [PRNG_CLK] = &prng_clk.clkr,
3264         [SDC1_SRC] = &sdc1_src.clkr,
3265         [SDC1_CLK] = &sdc1_clk.clkr,
3266         [SDC2_SRC] = &sdc2_src.clkr,
3267         [SDC2_CLK] = &sdc2_clk.clkr,
3268         [SDC3_SRC] = &sdc3_src.clkr,
3269         [SDC3_CLK] = &sdc3_clk.clkr,
3270         [SDC4_SRC] = &sdc4_src.clkr,
3271         [SDC4_CLK] = &sdc4_clk.clkr,
3272         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
3273         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
3274         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
3275         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
3276         [USB_HS3_XCVR_SRC] = &usb_hs3_xcvr_src.clkr,
3277         [USB_HS3_XCVR_CLK] = &usb_hs3_xcvr_clk.clkr,
3278         [USB_HS4_XCVR_SRC] = &usb_hs4_xcvr_src.clkr,
3279         [USB_HS4_XCVR_CLK] = &usb_hs4_xcvr_clk.clkr,
3280         [USB_HSIC_XCVR_FS_SRC] = &usb_hsic_xcvr_fs_src.clkr,
3281         [USB_HSIC_XCVR_FS_CLK] = &usb_hsic_xcvr_fs_clk.clkr,
3282         [USB_HSIC_SYSTEM_CLK] = &usb_hsic_system_clk.clkr,
3283         [USB_HSIC_HSIC_CLK] = &usb_hsic_hsic_clk.clkr,
3284         [USB_HSIC_HSIO_CAL_CLK] = &usb_hsic_hsio_cal_clk.clkr,
3285         [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
3286         [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
3287         [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
3288         [SATA_H_CLK] = &sata_h_clk.clkr,
3289         [SATA_CLK_SRC] = &sata_clk_src.clkr,
3290         [SATA_RXOOB_CLK] = &sata_rxoob_clk.clkr,
3291         [SATA_PMALIVE_CLK] = &sata_pmalive_clk.clkr,
3292         [SATA_PHY_REF_CLK] = &sata_phy_ref_clk.clkr,
3293         [SATA_PHY_CFG_CLK] = &sata_phy_cfg_clk.clkr,
3294         [SATA_A_CLK] = &sata_a_clk.clkr,
3295         [SFAB_SATA_S_H_CLK] = &sfab_sata_s_h_clk.clkr,
3296         [CE3_SRC] = &ce3_src.clkr,
3297         [CE3_CORE_CLK] = &ce3_core_clk.clkr,
3298         [CE3_H_CLK] = &ce3_h_clk.clkr,
3299         [DMA_BAM_H_CLK] = &dma_bam_h_clk.clkr,
3300         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
3301         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
3302         [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
3303         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
3304         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
3305         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
3306         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
3307         [TSIF_H_CLK] = &tsif_h_clk.clkr,
3308         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
3309         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
3310         [USB_HSIC_H_CLK] = &usb_hsic_h_clk.clkr,
3311         [USB_HS3_H_CLK] = &usb_hs3_h_clk.clkr,
3312         [USB_HS4_H_CLK] = &usb_hs4_h_clk.clkr,
3313         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
3314         [SDC2_H_CLK] = &sdc2_h_clk.clkr,
3315         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
3316         [SDC4_H_CLK] = &sdc4_h_clk.clkr,
3317         [ADM0_CLK] = &adm0_clk.clkr,
3318         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
3319         [PCIE_A_CLK] = &pcie_a_clk.clkr,
3320         [PCIE_PHY_REF_CLK] = &pcie_phy_ref_clk.clkr,
3321         [PCIE_H_CLK] = &pcie_h_clk.clkr,
3322         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
3323         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
3324         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
3325         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
3326 };
3327
3328 static const struct qcom_reset_map gcc_apq8064_resets[] = {
3329         [QDSS_STM_RESET] = { 0x2060, 6 },
3330         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3331         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3332         [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
3333         [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },
3334         [AFAB_EBI1_CH1_RESET] = { 0x20c4, 7},
3335         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
3336         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
3337         [SFAB_ADM0_M2_RESET] = { 0x21e8, 7 },
3338         [ADM0_C2_RESET] = { 0x220c, 4},
3339         [ADM0_C1_RESET] = { 0x220c, 3},
3340         [ADM0_C0_RESET] = { 0x220c, 2},
3341         [ADM0_PBUS_RESET] = { 0x220c, 1 },
3342         [ADM0_RESET] = { 0x220c },
3343         [QDSS_CLKS_SW_RESET] = { 0x2260, 5 },
3344         [QDSS_POR_RESET] = { 0x2260, 4 },
3345         [QDSS_TSCTR_RESET] = { 0x2260, 3 },
3346         [QDSS_HRESET_RESET] = { 0x2260, 2 },
3347         [QDSS_AXI_RESET] = { 0x2260, 1 },
3348         [QDSS_DBG_RESET] = { 0x2260 },
3349         [SFAB_PCIE_M_RESET] = { 0x22d8, 1 },
3350         [SFAB_PCIE_S_RESET] = { 0x22d8 },
3351         [PCIE_EXT_PCI_RESET] = { 0x22dc, 6 },
3352         [PCIE_PHY_RESET] = { 0x22dc, 5 },
3353         [PCIE_PCI_RESET] = { 0x22dc, 4 },
3354         [PCIE_POR_RESET] = { 0x22dc, 3 },
3355         [PCIE_HCLK_RESET] = { 0x22dc, 2 },
3356         [PCIE_ACLK_RESET] = { 0x22dc },
3357         [SFAB_USB3_M_RESET] = { 0x2360, 7 },
3358         [SFAB_RIVA_M_RESET] = { 0x2380, 7 },
3359         [SFAB_LPASS_RESET] = { 0x23a0, 7 },
3360         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
3361         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
3362         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
3363         [SFAB_SATA_S_RESET] = { 0x2480, 7 },
3364         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
3365         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
3366         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
3367         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
3368         [DFAB_ARB0_RESET] = { 0x2560, 7 },
3369         [DFAB_ARB1_RESET] = { 0x2564, 7 },
3370         [PPSS_PROC_RESET] = { 0x2594, 1 },
3371         [PPSS_RESET] = { 0x2594},
3372         [DMA_BAM_RESET] = { 0x25c0, 7 },
3373         [SPS_TIC_H_RESET] = { 0x2600, 7 },
3374         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
3375         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
3376         [TSIF_H_RESET] = { 0x2700, 7 },
3377         [CE1_H_RESET] = { 0x2720, 7 },
3378         [CE1_CORE_RESET] = { 0x2724, 7 },
3379         [CE1_SLEEP_RESET] = { 0x2728, 7 },
3380         [CE2_H_RESET] = { 0x2740, 7 },
3381         [CE2_CORE_RESET] = { 0x2744, 7 },
3382         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
3383         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
3384         [RPM_PROC_RESET] = { 0x27c0, 7 },
3385         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
3386         [SDC1_RESET] = { 0x2830 },
3387         [SDC2_RESET] = { 0x2850 },
3388         [SDC3_RESET] = { 0x2870 },
3389         [SDC4_RESET] = { 0x2890 },
3390         [USB_HS1_RESET] = { 0x2910 },
3391         [USB_HSIC_RESET] = { 0x2934 },
3392         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
3393         [USB_FS1_RESET] = { 0x2974 },
3394         [GSBI1_RESET] = { 0x29dc },
3395         [GSBI2_RESET] = { 0x29fc },
3396         [GSBI3_RESET] = { 0x2a1c },
3397         [GSBI4_RESET] = { 0x2a3c },
3398         [GSBI5_RESET] = { 0x2a5c },
3399         [GSBI6_RESET] = { 0x2a7c },
3400         [GSBI7_RESET] = { 0x2a9c },
3401         [SPDM_RESET] = { 0x2b6c },
3402         [TLMM_H_RESET] = { 0x2ba0, 7 },
3403         [SATA_SFAB_M_RESET] = { 0x2c18 },
3404         [SATA_RESET] = { 0x2c1c },
3405         [GSS_SLP_RESET] = { 0x2c60, 7 },
3406         [GSS_RESET] = { 0x2c64 },
3407         [TSSC_RESET] = { 0x2ca0, 7 },
3408         [PDM_RESET] = { 0x2cc0, 12 },
3409         [MPM_H_RESET] = { 0x2da0, 7 },
3410         [MPM_RESET] = { 0x2da4 },
3411         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
3412         [PRNG_RESET] = { 0x2e80, 12 },
3413         [RIVA_RESET] = { 0x35e0 },
3414         [CE3_H_RESET] = { 0x36c4, 7 },
3415         [SFAB_CE3_M_RESET] = { 0x36c8, 1 },
3416         [SFAB_CE3_S_RESET] = { 0x36c8 },
3417         [CE3_RESET] = { 0x36cc, 7 },
3418         [CE3_SLEEP_RESET] = { 0x36d0, 7 },
3419         [USB_HS3_RESET] = { 0x3710 },
3420         [USB_HS4_RESET] = { 0x3730 },
3421 };
3422
3423 static const struct regmap_config gcc_msm8960_regmap_config = {
3424         .reg_bits       = 32,
3425         .reg_stride     = 4,
3426         .val_bits       = 32,
3427         .max_register   = 0x3660,
3428         .fast_io        = true,
3429 };
3430
3431 static const struct regmap_config gcc_apq8064_regmap_config = {
3432         .reg_bits       = 32,
3433         .reg_stride     = 4,
3434         .val_bits       = 32,
3435         .max_register   = 0x3880,
3436         .fast_io        = true,
3437 };
3438
3439 static const struct qcom_cc_desc gcc_msm8960_desc = {
3440         .config = &gcc_msm8960_regmap_config,
3441         .clks = gcc_msm8960_clks,
3442         .num_clks = ARRAY_SIZE(gcc_msm8960_clks),
3443         .resets = gcc_msm8960_resets,
3444         .num_resets = ARRAY_SIZE(gcc_msm8960_resets),
3445 };
3446
3447 static const struct qcom_cc_desc gcc_apq8064_desc = {
3448         .config = &gcc_apq8064_regmap_config,
3449         .clks = gcc_apq8064_clks,
3450         .num_clks = ARRAY_SIZE(gcc_apq8064_clks),
3451         .resets = gcc_apq8064_resets,
3452         .num_resets = ARRAY_SIZE(gcc_apq8064_resets),
3453 };
3454
3455 static const struct of_device_id gcc_msm8960_match_table[] = {
3456         { .compatible = "qcom,gcc-msm8960", .data = &gcc_msm8960_desc },
3457         { .compatible = "qcom,gcc-apq8064", .data = &gcc_apq8064_desc },
3458         { }
3459 };
3460 MODULE_DEVICE_TABLE(of, gcc_msm8960_match_table);
3461
3462 static int gcc_msm8960_probe(struct platform_device *pdev)
3463 {
3464         struct device *dev = &pdev->dev;
3465         const struct of_device_id *match;
3466         struct platform_device *tsens;
3467         int ret;
3468
3469         match = of_match_device(gcc_msm8960_match_table, &pdev->dev);
3470         if (!match)
3471                 return -EINVAL;
3472
3473         ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
3474         if (ret)
3475                 return ret;
3476
3477         ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
3478         if (ret)
3479                 return ret;
3480
3481         ret = qcom_cc_probe(pdev, match->data);
3482         if (ret)
3483                 return ret;
3484
3485         tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
3486                                               NULL, 0);
3487         if (IS_ERR(tsens))
3488                 return PTR_ERR(tsens);
3489
3490         platform_set_drvdata(pdev, tsens);
3491
3492         return 0;
3493 }
3494
3495 static int gcc_msm8960_remove(struct platform_device *pdev)
3496 {
3497         struct platform_device *tsens = platform_get_drvdata(pdev);
3498
3499         platform_device_unregister(tsens);
3500
3501         return 0;
3502 }
3503
3504 static struct platform_driver gcc_msm8960_driver = {
3505         .probe          = gcc_msm8960_probe,
3506         .remove         = gcc_msm8960_remove,
3507         .driver         = {
3508                 .name   = "gcc-msm8960",
3509                 .of_match_table = gcc_msm8960_match_table,
3510         },
3511 };
3512
3513 static int __init gcc_msm8960_init(void)
3514 {
3515         return platform_driver_register(&gcc_msm8960_driver);
3516 }
3517 core_initcall(gcc_msm8960_init);
3518
3519 static void __exit gcc_msm8960_exit(void)
3520 {
3521         platform_driver_unregister(&gcc_msm8960_driver);
3522 }
3523 module_exit(gcc_msm8960_exit);
3524
3525 MODULE_DESCRIPTION("QCOM GCC MSM8960 Driver");
3526 MODULE_LICENSE("GPL v2");
3527 MODULE_ALIAS("platform:gcc-msm8960");