drivers/clk/mediatek/clk-mt2701-bdp.c

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Shunli Wang <shunli.wang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk-provider.h>
  16 #include <linux/platform_device.h>
  17
  18 #include "clk-mtk.h"
  19 #include "clk-gate.h"
  20
  21 #include <dt-bindings/clock/mt2701-clk.h>
  22
  23 static const struct mtk_gate_regs bdp0_cg_regs = {
  24         .set_ofs = 0x0104,
  25         .clr_ofs = 0x0108,
  26         .sta_ofs = 0x0100,
  27 };
  28
  29 static const struct mtk_gate_regs bdp1_cg_regs = {
  30         .set_ofs = 0x0114,
  31         .clr_ofs = 0x0118,
  32         .sta_ofs = 0x0110,
  33 };
  34
  35 #define GATE_BDP0(_id, _name, _parent, _shift) {        \
  36                 .id = _id,                              \
  37                 .name = _name,                          \
  38                 .parent_name = _parent,                 \
  39                 .regs = &bdp0_cg_regs,                  \
  40                 .shift = _shift,                        \
  41                 .ops = &mtk_clk_gate_ops_setclr_inv,    \
  42         }
  43
  44 #define GATE_BDP1(_id, _name, _parent, _shift) {        \
  45                 .id = _id,                              \
  46                 .name = _name,                          \
  47                 .parent_name = _parent,                 \
  48                 .regs = &bdp1_cg_regs,                  \
  49                 .shift = _shift,                        \
  50                 .ops = &mtk_clk_gate_ops_setclr_inv,    \
  51         }
  52
  53 static const struct mtk_gate bdp_clks[] = {
  54         GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),
  55         GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1),
  56         GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2),
  57         GATE_BDP0(CLK_BDP_WR_VDI_PXL, "wr_vdi_pxl", "hdmi_0_deep340m", 3),
  58         GATE_BDP0(CLK_BDP_WR_VDI_DRAM, "wr_vdi_dram", "mm_sel", 4),
  59         GATE_BDP0(CLK_BDP_WR_B, "wr_bclk", "mm_sel", 5),
  60         GATE_BDP0(CLK_BDP_DGI_IN, "dgi_in", "dpi1_sel", 6),
  61         GATE_BDP0(CLK_BDP_DGI_OUT, "dgi_out", "dpi1_sel", 7),
  62         GATE_BDP0(CLK_BDP_FMT_MAST_27, "fmt_mast_27", "dpi1_sel", 8),
  63         GATE_BDP0(CLK_BDP_FMT_B, "fmt_bclk", "mm_sel", 9),
  64         GATE_BDP0(CLK_BDP_OSD_B, "osd_bclk", "mm_sel", 10),
  65         GATE_BDP0(CLK_BDP_OSD_DRAM, "osd_dram", "mm_sel", 11),
  66         GATE_BDP0(CLK_BDP_OSD_AGENT, "osd_agent", "osd_sel", 12),
  67         GATE_BDP0(CLK_BDP_OSD_PXL, "osd_pxl", "dpi1_sel", 13),
  68         GATE_BDP0(CLK_BDP_RLE_B, "rle_bclk", "mm_sel", 14),
  69         GATE_BDP0(CLK_BDP_RLE_AGENT, "rle_agent", "mm_sel", 15),
  70         GATE_BDP0(CLK_BDP_RLE_DRAM, "rle_dram", "mm_sel", 16),
  71         GATE_BDP0(CLK_BDP_F27M, "f27m", "di_sel", 17),
  72         GATE_BDP0(CLK_BDP_F27M_VDOUT, "f27m_vdout", "di_sel", 18),
  73         GATE_BDP0(CLK_BDP_F27_74_74, "f27_74_74", "di_sel", 19),
  74         GATE_BDP0(CLK_BDP_F2FS, "f2fs", "di_sel", 20),
  75         GATE_BDP0(CLK_BDP_F2FS74_148, "f2fs74_148", "di_sel", 21),
  76         GATE_BDP0(CLK_BDP_FB, "fbclk", "mm_sel", 22),
  77         GATE_BDP0(CLK_BDP_VDO_DRAM, "vdo_dram", "mm_sel", 23),
  78         GATE_BDP0(CLK_BDP_VDO_2FS, "vdo_2fs", "di_sel", 24),
  79         GATE_BDP0(CLK_BDP_VDO_B, "vdo_bclk", "mm_sel", 25),
  80         GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26),
  81         GATE_BDP0(CLK_BDP_WR_DI_DRAM, "wr_di_dram", "mm_sel", 27),
  82         GATE_BDP0(CLK_BDP_WR_DI_B, "wr_di_bclk", "mm_sel", 28),
  83         GATE_BDP0(CLK_BDP_NR_PXL, "nr_pxl", "nr_sel", 29),
  84         GATE_BDP0(CLK_BDP_NR_DRAM, "nr_dram", "mm_sel", 30),
  85         GATE_BDP0(CLK_BDP_NR_B, "nr_bclk", "mm_sel", 31),
  86         GATE_BDP1(CLK_BDP_RX_F, "rx_fclk", "hadds2_fbclk", 0),
  87         GATE_BDP1(CLK_BDP_RX_X, "rx_xclk", "clk26m", 1),
  88         GATE_BDP1(CLK_BDP_RXPDT, "rxpdtclk", "hdmi_0_pix340m", 2),
  89         GATE_BDP1(CLK_BDP_RX_CSCL_N, "rx_cscl_n", "clk26m", 3),
  90         GATE_BDP1(CLK_BDP_RX_CSCL, "rx_cscl", "clk26m", 4),
  91         GATE_BDP1(CLK_BDP_RX_DDCSCL_N, "rx_ddcscl_n", "hdmi_scl_rx", 5),
  92         GATE_BDP1(CLK_BDP_RX_DDCSCL, "rx_ddcscl", "hdmi_scl_rx", 6),
  93         GATE_BDP1(CLK_BDP_RX_VCO, "rx_vcoclk", "hadds2pll_294m", 7),
  94         GATE_BDP1(CLK_BDP_RX_DP, "rx_dpclk", "hdmi_0_pll340m", 8),
  95         GATE_BDP1(CLK_BDP_RX_P, "rx_pclk", "hdmi_0_pll340m", 9),
  96         GATE_BDP1(CLK_BDP_RX_M, "rx_mclk", "hadds2pll_294m", 10),
  97         GATE_BDP1(CLK_BDP_RX_PLL, "rx_pllclk", "hdmi_0_pix340m", 11),
  98         GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12),
  99         GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13),
 100         GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14),
 101         GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15),
 102         GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16),
 103 };
 104
 105 static const struct of_device_id of_match_clk_mt2701_bdp[] = {
 106         { .compatible = "mediatek,mt2701-bdpsys", },
 107         {}
 108 };
 109
 110 static int clk_mt2701_bdp_probe(struct platform_device *pdev)
 111 {
 112         struct clk_onecell_data *clk_data;
 113         int r;
 114         struct device_node *node = pdev->dev.of_node;
 115
 116         clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
 117
 118         mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
 119                                                 clk_data);
 120
 121         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 122         if (r)
 123                 dev_err(&pdev->dev,
 124                         "could not register clock provider: %s: %d\n",
 125                         pdev->name, r);
 126
 127         return r;
 128 }
 129
 130 static struct platform_driver clk_mt2701_bdp_drv = {
 131         .probe = clk_mt2701_bdp_probe,
 132         .driver = {
 133                 .name = "clk-mt2701-bdp",
 134                 .of_match_table = of_match_clk_mt2701_bdp,
 135         },
 136 };
 137
 138 builtin_platform_driver(clk_mt2701_bdp_drv);