2 * libahci.c - Common AHCI SATA low-level routines
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/nospec.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47 #include <linux/pci.h>
51 static int ahci_skip_host_reset;
53 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
55 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
56 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
58 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
59 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
61 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
63 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
64 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
66 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
71 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
72 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74 static int ahci_port_start(struct ata_port *ap);
75 static void ahci_port_stop(struct ata_port *ap);
76 static void ahci_qc_prep(struct ata_queued_cmd *qc);
77 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78 static void ahci_freeze(struct ata_port *ap);
79 static void ahci_thaw(struct ata_port *ap);
80 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
81 static void ahci_enable_fbs(struct ata_port *ap);
82 static void ahci_disable_fbs(struct ata_port *ap);
83 static void ahci_pmp_attach(struct ata_port *ap);
84 static void ahci_pmp_detach(struct ata_port *ap);
85 static int ahci_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static void ahci_postreset(struct ata_link *link, unsigned int *class);
92 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
93 static void ahci_dev_config(struct ata_device *dev);
95 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
97 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
98 static ssize_t ahci_activity_store(struct ata_device *dev,
99 enum sw_activity val);
100 static void ahci_init_sw_activity(struct ata_link *link);
102 static ssize_t ahci_show_host_caps(struct device *dev,
103 struct device_attribute *attr, char *buf);
104 static ssize_t ahci_show_host_cap2(struct device *dev,
105 struct device_attribute *attr, char *buf);
106 static ssize_t ahci_show_host_version(struct device *dev,
107 struct device_attribute *attr, char *buf);
108 static ssize_t ahci_show_port_cmd(struct device *dev,
109 struct device_attribute *attr, char *buf);
110 static ssize_t ahci_read_em_buffer(struct device *dev,
111 struct device_attribute *attr, char *buf);
112 static ssize_t ahci_store_em_buffer(struct device *dev,
113 struct device_attribute *attr,
114 const char *buf, size_t size);
115 static ssize_t ahci_show_em_supported(struct device *dev,
116 struct device_attribute *attr, char *buf);
117 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance);
119 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
120 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
121 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
122 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
123 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
124 ahci_read_em_buffer, ahci_store_em_buffer);
125 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
127 struct device_attribute *ahci_shost_attrs[] = {
128 &dev_attr_link_power_management_policy,
129 &dev_attr_em_message_type,
130 &dev_attr_em_message,
131 &dev_attr_ahci_host_caps,
132 &dev_attr_ahci_host_cap2,
133 &dev_attr_ahci_host_version,
134 &dev_attr_ahci_port_cmd,
136 &dev_attr_em_message_supported,
139 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
141 struct device_attribute *ahci_sdev_attrs[] = {
142 &dev_attr_sw_activity,
143 &dev_attr_unload_heads,
146 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
148 struct ata_port_operations ahci_ops = {
149 .inherits = &sata_pmp_port_ops,
151 .qc_defer = ahci_pmp_qc_defer,
152 .qc_prep = ahci_qc_prep,
153 .qc_issue = ahci_qc_issue,
154 .qc_fill_rtf = ahci_qc_fill_rtf,
156 .freeze = ahci_freeze,
158 .softreset = ahci_softreset,
159 .hardreset = ahci_hardreset,
160 .postreset = ahci_postreset,
161 .pmp_softreset = ahci_softreset,
162 .error_handler = ahci_error_handler,
163 .post_internal_cmd = ahci_post_internal_cmd,
164 .dev_config = ahci_dev_config,
166 .scr_read = ahci_scr_read,
167 .scr_write = ahci_scr_write,
168 .pmp_attach = ahci_pmp_attach,
169 .pmp_detach = ahci_pmp_detach,
171 .set_lpm = ahci_set_lpm,
172 .em_show = ahci_led_show,
173 .em_store = ahci_led_store,
174 .sw_activity_show = ahci_activity_show,
175 .sw_activity_store = ahci_activity_store,
176 .transmit_led_message = ahci_transmit_led_message,
178 .port_suspend = ahci_port_suspend,
179 .port_resume = ahci_port_resume,
181 .port_start = ahci_port_start,
182 .port_stop = ahci_port_stop,
184 EXPORT_SYMBOL_GPL(ahci_ops);
186 struct ata_port_operations ahci_pmp_retry_srst_ops = {
187 .inherits = &ahci_ops,
188 .softreset = ahci_pmp_retry_softreset,
190 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
192 static bool ahci_em_messages __read_mostly = true;
193 EXPORT_SYMBOL_GPL(ahci_em_messages);
194 module_param(ahci_em_messages, bool, 0444);
195 /* add other LED protocol types when they become supported */
196 MODULE_PARM_DESC(ahci_em_messages,
197 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
199 /* device sleep idle timeout in ms */
200 static int devslp_idle_timeout __read_mostly = 1000;
201 module_param(devslp_idle_timeout, int, 0644);
202 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
204 static void ahci_enable_ahci(void __iomem *mmio)
209 /* turn on AHCI_EN */
210 tmp = readl(mmio + HOST_CTL);
211 if (tmp & HOST_AHCI_EN)
214 /* Some controllers need AHCI_EN to be written multiple times.
215 * Try a few times before giving up.
217 for (i = 0; i < 5; i++) {
219 writel(tmp, mmio + HOST_CTL);
220 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
221 if (tmp & HOST_AHCI_EN)
230 * ahci_rpm_get_port - Make sure the port is powered on
231 * @ap: Port to power on
233 * Whenever there is need to access the AHCI host registers outside of
234 * normal execution paths, call this function to make sure the host is
235 * actually powered on.
237 static int ahci_rpm_get_port(struct ata_port *ap)
239 return pm_runtime_get_sync(ap->dev);
243 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
244 * @ap: Port to power down
246 * Undoes ahci_rpm_get_port() and possibly powers down the AHCI host
247 * if it has no more active users.
249 static void ahci_rpm_put_port(struct ata_port *ap)
251 pm_runtime_put(ap->dev);
254 static ssize_t ahci_show_host_caps(struct device *dev,
255 struct device_attribute *attr, char *buf)
257 struct Scsi_Host *shost = class_to_shost(dev);
258 struct ata_port *ap = ata_shost_to_port(shost);
259 struct ahci_host_priv *hpriv = ap->host->private_data;
261 return sprintf(buf, "%x\n", hpriv->cap);
264 static ssize_t ahci_show_host_cap2(struct device *dev,
265 struct device_attribute *attr, char *buf)
267 struct Scsi_Host *shost = class_to_shost(dev);
268 struct ata_port *ap = ata_shost_to_port(shost);
269 struct ahci_host_priv *hpriv = ap->host->private_data;
271 return sprintf(buf, "%x\n", hpriv->cap2);
274 static ssize_t ahci_show_host_version(struct device *dev,
275 struct device_attribute *attr, char *buf)
277 struct Scsi_Host *shost = class_to_shost(dev);
278 struct ata_port *ap = ata_shost_to_port(shost);
279 struct ahci_host_priv *hpriv = ap->host->private_data;
281 return sprintf(buf, "%x\n", hpriv->version);
284 static ssize_t ahci_show_port_cmd(struct device *dev,
285 struct device_attribute *attr, char *buf)
287 struct Scsi_Host *shost = class_to_shost(dev);
288 struct ata_port *ap = ata_shost_to_port(shost);
289 void __iomem *port_mmio = ahci_port_base(ap);
292 ahci_rpm_get_port(ap);
293 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
294 ahci_rpm_put_port(ap);
299 static ssize_t ahci_read_em_buffer(struct device *dev,
300 struct device_attribute *attr, char *buf)
302 struct Scsi_Host *shost = class_to_shost(dev);
303 struct ata_port *ap = ata_shost_to_port(shost);
304 struct ahci_host_priv *hpriv = ap->host->private_data;
305 void __iomem *mmio = hpriv->mmio;
306 void __iomem *em_mmio = mmio + hpriv->em_loc;
312 ahci_rpm_get_port(ap);
313 spin_lock_irqsave(ap->lock, flags);
315 em_ctl = readl(mmio + HOST_EM_CTL);
316 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
317 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
318 spin_unlock_irqrestore(ap->lock, flags);
319 ahci_rpm_put_port(ap);
323 if (!(em_ctl & EM_CTL_MR)) {
324 spin_unlock_irqrestore(ap->lock, flags);
325 ahci_rpm_put_port(ap);
329 if (!(em_ctl & EM_CTL_SMB))
330 em_mmio += hpriv->em_buf_sz;
332 count = hpriv->em_buf_sz;
334 /* the count should not be larger than PAGE_SIZE */
335 if (count > PAGE_SIZE) {
336 if (printk_ratelimit())
338 "EM read buffer size too large: "
339 "buffer size %u, page size %lu\n",
340 hpriv->em_buf_sz, PAGE_SIZE);
344 for (i = 0; i < count; i += 4) {
345 msg = readl(em_mmio + i);
347 buf[i + 1] = (msg >> 8) & 0xff;
348 buf[i + 2] = (msg >> 16) & 0xff;
349 buf[i + 3] = (msg >> 24) & 0xff;
352 spin_unlock_irqrestore(ap->lock, flags);
353 ahci_rpm_put_port(ap);
358 static ssize_t ahci_store_em_buffer(struct device *dev,
359 struct device_attribute *attr,
360 const char *buf, size_t size)
362 struct Scsi_Host *shost = class_to_shost(dev);
363 struct ata_port *ap = ata_shost_to_port(shost);
364 struct ahci_host_priv *hpriv = ap->host->private_data;
365 void __iomem *mmio = hpriv->mmio;
366 void __iomem *em_mmio = mmio + hpriv->em_loc;
367 const unsigned char *msg_buf = buf;
372 /* check size validity */
373 if (!(ap->flags & ATA_FLAG_EM) ||
374 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
375 size % 4 || size > hpriv->em_buf_sz)
378 ahci_rpm_get_port(ap);
379 spin_lock_irqsave(ap->lock, flags);
381 em_ctl = readl(mmio + HOST_EM_CTL);
382 if (em_ctl & EM_CTL_TM) {
383 spin_unlock_irqrestore(ap->lock, flags);
384 ahci_rpm_put_port(ap);
388 for (i = 0; i < size; i += 4) {
389 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
390 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
391 writel(msg, em_mmio + i);
394 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
396 spin_unlock_irqrestore(ap->lock, flags);
397 ahci_rpm_put_port(ap);
402 static ssize_t ahci_show_em_supported(struct device *dev,
403 struct device_attribute *attr, char *buf)
405 struct Scsi_Host *shost = class_to_shost(dev);
406 struct ata_port *ap = ata_shost_to_port(shost);
407 struct ahci_host_priv *hpriv = ap->host->private_data;
408 void __iomem *mmio = hpriv->mmio;
411 ahci_rpm_get_port(ap);
412 em_ctl = readl(mmio + HOST_EM_CTL);
413 ahci_rpm_put_port(ap);
415 return sprintf(buf, "%s%s%s%s\n",
416 em_ctl & EM_CTL_LED ? "led " : "",
417 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
418 em_ctl & EM_CTL_SES ? "ses-2 " : "",
419 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
423 * ahci_save_initial_config - Save and fixup initial config values
424 * @dev: target AHCI device
425 * @hpriv: host private area to store config values
427 * Some registers containing configuration info might be setup by
428 * BIOS and might be cleared on reset. This function saves the
429 * initial values of those registers into @hpriv such that they
430 * can be restored after controller reset.
432 * If inconsistent, config values are fixed up by this function.
434 * If it is not set already this function sets hpriv->start_engine to
440 void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
442 void __iomem *mmio = hpriv->mmio;
443 u32 cap, cap2, vers, port_map;
446 /* make sure AHCI mode is enabled before accessing CAP */
447 ahci_enable_ahci(mmio);
449 /* Values prefixed with saved_ are written back to host after
450 * reset. Values without are used for driver operation.
452 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
453 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
455 /* CAP2 register is only defined for AHCI 1.2 and later */
456 vers = readl(mmio + HOST_VERSION);
457 if ((vers >> 16) > 1 ||
458 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
459 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
461 hpriv->saved_cap2 = cap2 = 0;
463 /* some chips have errata preventing 64bit use */
464 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
465 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
469 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
470 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
471 cap &= ~HOST_CAP_NCQ;
474 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
475 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
479 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
480 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
481 cap &= ~HOST_CAP_PMP;
484 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
486 "controller can't do SNTF, turning off CAP_SNTF\n");
487 cap &= ~HOST_CAP_SNTF;
490 if ((cap2 & HOST_CAP2_SDS) && (hpriv->flags & AHCI_HFLAG_NO_DEVSLP)) {
492 "controller can't do DEVSLP, turning off\n");
493 cap2 &= ~HOST_CAP2_SDS;
494 cap2 &= ~HOST_CAP2_SADM;
497 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
498 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
502 if ((cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_NO_FBS)) {
503 dev_info(dev, "controller can't do FBS, turning off CAP_FBS\n");
504 cap &= ~HOST_CAP_FBS;
507 if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
508 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
509 port_map, hpriv->force_port_map);
510 port_map = hpriv->force_port_map;
511 hpriv->saved_port_map = port_map;
514 if (hpriv->mask_port_map) {
515 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
517 port_map & hpriv->mask_port_map);
518 port_map &= hpriv->mask_port_map;
521 /* cross check port_map and cap.n_ports */
525 for (i = 0; i < AHCI_MAX_PORTS; i++)
526 if (port_map & (1 << i))
529 /* If PI has more ports than n_ports, whine, clear
530 * port_map and let it be generated from n_ports.
532 if (map_ports > ahci_nr_ports(cap)) {
534 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
535 port_map, ahci_nr_ports(cap));
540 /* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
541 if (!port_map && vers < 0x10300) {
542 port_map = (1 << ahci_nr_ports(cap)) - 1;
543 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
545 /* write the fixed up value to the PI register */
546 hpriv->saved_port_map = port_map;
549 /* record values to use during operation */
552 hpriv->version = readl(mmio + HOST_VERSION);
553 hpriv->port_map = port_map;
555 if (!hpriv->start_engine)
556 hpriv->start_engine = ahci_start_engine;
558 if (!hpriv->irq_handler)
559 hpriv->irq_handler = ahci_single_level_irq_intr;
561 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
564 * ahci_restore_initial_config - Restore initial config
565 * @host: target ATA host
567 * Restore initial config stored by ahci_save_initial_config().
572 static void ahci_restore_initial_config(struct ata_host *host)
574 struct ahci_host_priv *hpriv = host->private_data;
575 void __iomem *mmio = hpriv->mmio;
577 writel(hpriv->saved_cap, mmio + HOST_CAP);
578 if (hpriv->saved_cap2)
579 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
580 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
581 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
584 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
586 static const int offset[] = {
587 [SCR_STATUS] = PORT_SCR_STAT,
588 [SCR_CONTROL] = PORT_SCR_CTL,
589 [SCR_ERROR] = PORT_SCR_ERR,
590 [SCR_ACTIVE] = PORT_SCR_ACT,
591 [SCR_NOTIFICATION] = PORT_SCR_NTF,
593 struct ahci_host_priv *hpriv = ap->host->private_data;
595 if (sc_reg < ARRAY_SIZE(offset) &&
596 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
597 return offset[sc_reg];
601 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
603 void __iomem *port_mmio = ahci_port_base(link->ap);
604 int offset = ahci_scr_offset(link->ap, sc_reg);
607 *val = readl(port_mmio + offset);
613 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
615 void __iomem *port_mmio = ahci_port_base(link->ap);
616 int offset = ahci_scr_offset(link->ap, sc_reg);
619 writel(val, port_mmio + offset);
625 void ahci_start_engine(struct ata_port *ap)
627 void __iomem *port_mmio = ahci_port_base(ap);
631 tmp = readl(port_mmio + PORT_CMD);
632 tmp |= PORT_CMD_START;
633 writel(tmp, port_mmio + PORT_CMD);
634 readl(port_mmio + PORT_CMD); /* flush */
636 EXPORT_SYMBOL_GPL(ahci_start_engine);
638 int ahci_stop_engine(struct ata_port *ap)
640 void __iomem *port_mmio = ahci_port_base(ap);
641 struct ahci_host_priv *hpriv = ap->host->private_data;
645 * On some controllers, stopping a port's DMA engine while the port
646 * is in ALPM state (partial or slumber) results in failures on
647 * subsequent DMA engine starts. For those controllers, put the
648 * port back in active state before stopping its DMA engine.
650 if ((hpriv->flags & AHCI_HFLAG_WAKE_BEFORE_STOP) &&
651 (ap->link.lpm_policy > ATA_LPM_MAX_POWER) &&
652 ahci_set_lpm(&ap->link, ATA_LPM_MAX_POWER, ATA_LPM_WAKE_ONLY)) {
653 dev_err(ap->host->dev, "Failed to wake up port before engine stop\n");
657 tmp = readl(port_mmio + PORT_CMD);
659 /* check if the HBA is idle */
660 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
663 /* setting HBA to idle */
664 tmp &= ~PORT_CMD_START;
665 writel(tmp, port_mmio + PORT_CMD);
667 /* wait for engine to stop. This could be as long as 500 msec */
668 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
669 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
670 if (tmp & PORT_CMD_LIST_ON)
675 EXPORT_SYMBOL_GPL(ahci_stop_engine);
677 void ahci_start_fis_rx(struct ata_port *ap)
679 void __iomem *port_mmio = ahci_port_base(ap);
680 struct ahci_host_priv *hpriv = ap->host->private_data;
681 struct ahci_port_priv *pp = ap->private_data;
684 /* set FIS registers */
685 if (hpriv->cap & HOST_CAP_64)
686 writel((pp->cmd_slot_dma >> 16) >> 16,
687 port_mmio + PORT_LST_ADDR_HI);
688 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
690 if (hpriv->cap & HOST_CAP_64)
691 writel((pp->rx_fis_dma >> 16) >> 16,
692 port_mmio + PORT_FIS_ADDR_HI);
693 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
695 /* enable FIS reception */
696 tmp = readl(port_mmio + PORT_CMD);
697 tmp |= PORT_CMD_FIS_RX;
698 writel(tmp, port_mmio + PORT_CMD);
701 readl(port_mmio + PORT_CMD);
703 EXPORT_SYMBOL_GPL(ahci_start_fis_rx);
705 static int ahci_stop_fis_rx(struct ata_port *ap)
707 void __iomem *port_mmio = ahci_port_base(ap);
710 /* disable FIS reception */
711 tmp = readl(port_mmio + PORT_CMD);
712 tmp &= ~PORT_CMD_FIS_RX;
713 writel(tmp, port_mmio + PORT_CMD);
715 /* wait for completion, spec says 500ms, give it 1000 */
716 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
717 PORT_CMD_FIS_ON, 10, 1000);
718 if (tmp & PORT_CMD_FIS_ON)
724 static void ahci_power_up(struct ata_port *ap)
726 struct ahci_host_priv *hpriv = ap->host->private_data;
727 void __iomem *port_mmio = ahci_port_base(ap);
730 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
733 if (hpriv->cap & HOST_CAP_SSS) {
734 cmd |= PORT_CMD_SPIN_UP;
735 writel(cmd, port_mmio + PORT_CMD);
739 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
742 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
745 struct ata_port *ap = link->ap;
746 struct ahci_host_priv *hpriv = ap->host->private_data;
747 struct ahci_port_priv *pp = ap->private_data;
748 void __iomem *port_mmio = ahci_port_base(ap);
750 if (policy != ATA_LPM_MAX_POWER) {
751 /* wakeup flag only applies to the max power policy */
752 hints &= ~ATA_LPM_WAKE_ONLY;
755 * Disable interrupts on Phy Ready. This keeps us from
756 * getting woken up due to spurious phy ready
759 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
760 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
762 sata_link_scr_lpm(link, policy, false);
765 if (hpriv->cap & HOST_CAP_ALPM) {
766 u32 cmd = readl(port_mmio + PORT_CMD);
768 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
769 if (!(hints & ATA_LPM_WAKE_ONLY))
770 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
771 cmd |= PORT_CMD_ICC_ACTIVE;
773 writel(cmd, port_mmio + PORT_CMD);
774 readl(port_mmio + PORT_CMD);
776 /* wait 10ms to be sure we've come out of LPM state */
779 if (hints & ATA_LPM_WAKE_ONLY)
782 cmd |= PORT_CMD_ALPE;
783 if (policy == ATA_LPM_MIN_POWER)
786 /* write out new cmd value */
787 writel(cmd, port_mmio + PORT_CMD);
791 /* set aggressive device sleep */
792 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
793 (hpriv->cap2 & HOST_CAP2_SADM) &&
794 (link->device->flags & ATA_DFLAG_DEVSLP)) {
795 if (policy == ATA_LPM_MIN_POWER)
796 ahci_set_aggressive_devslp(ap, true);
798 ahci_set_aggressive_devslp(ap, false);
801 if (policy == ATA_LPM_MAX_POWER) {
802 sata_link_scr_lpm(link, policy, false);
804 /* turn PHYRDY IRQ back on */
805 pp->intr_mask |= PORT_IRQ_PHYRDY;
806 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
813 static void ahci_power_down(struct ata_port *ap)
815 struct ahci_host_priv *hpriv = ap->host->private_data;
816 void __iomem *port_mmio = ahci_port_base(ap);
819 if (!(hpriv->cap & HOST_CAP_SSS))
822 /* put device into listen mode, first set PxSCTL.DET to 0 */
823 scontrol = readl(port_mmio + PORT_SCR_CTL);
825 writel(scontrol, port_mmio + PORT_SCR_CTL);
827 /* then set PxCMD.SUD to 0 */
828 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
829 cmd &= ~PORT_CMD_SPIN_UP;
830 writel(cmd, port_mmio + PORT_CMD);
834 static void ahci_start_port(struct ata_port *ap)
836 struct ahci_host_priv *hpriv = ap->host->private_data;
837 struct ahci_port_priv *pp = ap->private_data;
838 struct ata_link *link;
839 struct ahci_em_priv *emp;
843 /* enable FIS reception */
844 ahci_start_fis_rx(ap);
847 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
848 hpriv->start_engine(ap);
851 if (ap->flags & ATA_FLAG_EM) {
852 ata_for_each_link(link, ap, EDGE) {
853 emp = &pp->em_priv[link->pmp];
855 /* EM Transmit bit maybe busy during init */
856 for (i = 0; i < EM_MAX_RETRY; i++) {
857 rc = ap->ops->transmit_led_message(ap,
861 * If busy, give a breather but do not
862 * release EH ownership by using msleep()
863 * instead of ata_msleep(). EM Transmit
864 * bit is busy for the whole host and
865 * releasing ownership will cause other
866 * ports to fail the same way.
876 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
877 ata_for_each_link(link, ap, EDGE)
878 ahci_init_sw_activity(link);
882 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
887 rc = ahci_stop_engine(ap);
889 *emsg = "failed to stop engine";
893 /* disable FIS reception */
894 rc = ahci_stop_fis_rx(ap);
896 *emsg = "failed stop FIS RX";
903 int ahci_reset_controller(struct ata_host *host)
905 struct ahci_host_priv *hpriv = host->private_data;
906 void __iomem *mmio = hpriv->mmio;
909 /* we must be in AHCI mode, before using anything
910 * AHCI-specific, such as HOST_RESET.
912 ahci_enable_ahci(mmio);
914 /* global controller reset */
915 if (!ahci_skip_host_reset) {
916 tmp = readl(mmio + HOST_CTL);
917 if ((tmp & HOST_RESET) == 0) {
918 writel(tmp | HOST_RESET, mmio + HOST_CTL);
919 readl(mmio + HOST_CTL); /* flush */
923 * to perform host reset, OS should set HOST_RESET
924 * and poll until this bit is read to be "0".
925 * reset must complete within 1 second, or
926 * the hardware should be considered fried.
928 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
929 HOST_RESET, 10, 1000);
931 if (tmp & HOST_RESET) {
932 dev_err(host->dev, "controller reset failed (0x%x)\n",
937 /* turn on AHCI mode */
938 ahci_enable_ahci(mmio);
940 /* Some registers might be cleared on reset. Restore
943 ahci_restore_initial_config(host);
945 dev_info(host->dev, "skipping global host reset\n");
949 EXPORT_SYMBOL_GPL(ahci_reset_controller);
951 static void ahci_sw_activity(struct ata_link *link)
953 struct ata_port *ap = link->ap;
954 struct ahci_port_priv *pp = ap->private_data;
955 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
957 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
961 if (!timer_pending(&emp->timer))
962 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
965 static void ahci_sw_activity_blink(unsigned long arg)
967 struct ata_link *link = (struct ata_link *)arg;
968 struct ata_port *ap = link->ap;
969 struct ahci_port_priv *pp = ap->private_data;
970 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
971 unsigned long led_message = emp->led_state;
972 u32 activity_led_state;
975 led_message &= EM_MSG_LED_VALUE;
976 led_message |= ap->port_no | (link->pmp << 8);
978 /* check to see if we've had activity. If so,
979 * toggle state of LED and reset timer. If not,
980 * turn LED to desired idle state.
982 spin_lock_irqsave(ap->lock, flags);
983 if (emp->saved_activity != emp->activity) {
984 emp->saved_activity = emp->activity;
985 /* get the current LED state */
986 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
988 if (activity_led_state)
989 activity_led_state = 0;
991 activity_led_state = 1;
993 /* clear old state */
994 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
997 led_message |= (activity_led_state << 16);
998 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1000 /* switch to idle */
1001 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1002 if (emp->blink_policy == BLINK_OFF)
1003 led_message |= (1 << 16);
1005 spin_unlock_irqrestore(ap->lock, flags);
1006 ap->ops->transmit_led_message(ap, led_message, 4);
1009 static void ahci_init_sw_activity(struct ata_link *link)
1011 struct ata_port *ap = link->ap;
1012 struct ahci_port_priv *pp = ap->private_data;
1013 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1015 /* init activity stats, setup timer */
1016 emp->saved_activity = emp->activity = 0;
1017 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1019 /* check our blink policy and set flag for link if it's enabled */
1020 if (emp->blink_policy)
1021 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1024 int ahci_reset_em(struct ata_host *host)
1026 struct ahci_host_priv *hpriv = host->private_data;
1027 void __iomem *mmio = hpriv->mmio;
1030 em_ctl = readl(mmio + HOST_EM_CTL);
1031 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1034 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1037 EXPORT_SYMBOL_GPL(ahci_reset_em);
1039 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1042 struct ahci_host_priv *hpriv = ap->host->private_data;
1043 struct ahci_port_priv *pp = ap->private_data;
1044 void __iomem *mmio = hpriv->mmio;
1046 u32 message[] = {0, 0};
1047 unsigned long flags;
1049 struct ahci_em_priv *emp;
1051 /* get the slot number from the message */
1052 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1053 if (pmp < EM_MAX_SLOTS)
1054 emp = &pp->em_priv[pmp];
1058 ahci_rpm_get_port(ap);
1059 spin_lock_irqsave(ap->lock, flags);
1062 * if we are still busy transmitting a previous message,
1065 em_ctl = readl(mmio + HOST_EM_CTL);
1066 if (em_ctl & EM_CTL_TM) {
1067 spin_unlock_irqrestore(ap->lock, flags);
1068 ahci_rpm_put_port(ap);
1072 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1074 * create message header - this is all zero except for
1075 * the message size, which is 4 bytes.
1077 message[0] |= (4 << 8);
1079 /* ignore 0:4 of byte zero, fill in port info yourself */
1080 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1082 /* write message to EM_LOC */
1083 writel(message[0], mmio + hpriv->em_loc);
1084 writel(message[1], mmio + hpriv->em_loc+4);
1087 * tell hardware to transmit the message
1089 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1092 /* save off new led state for port/slot */
1093 emp->led_state = state;
1095 spin_unlock_irqrestore(ap->lock, flags);
1096 ahci_rpm_put_port(ap);
1101 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1103 struct ahci_port_priv *pp = ap->private_data;
1104 struct ata_link *link;
1105 struct ahci_em_priv *emp;
1108 ata_for_each_link(link, ap, EDGE) {
1109 emp = &pp->em_priv[link->pmp];
1110 rc += sprintf(buf, "%lx\n", emp->led_state);
1115 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1120 struct ahci_port_priv *pp = ap->private_data;
1121 struct ahci_em_priv *emp;
1123 if (kstrtouint(buf, 0, &state) < 0)
1126 /* get the slot number from the message */
1127 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1128 if (pmp < EM_MAX_SLOTS) {
1129 pmp = array_index_nospec(pmp, EM_MAX_SLOTS);
1130 emp = &pp->em_priv[pmp];
1135 /* mask off the activity bits if we are in sw_activity
1136 * mode, user should turn off sw_activity before setting
1137 * activity led through em_message
1139 if (emp->blink_policy)
1140 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1142 return ap->ops->transmit_led_message(ap, state, size);
1145 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1147 struct ata_link *link = dev->link;
1148 struct ata_port *ap = link->ap;
1149 struct ahci_port_priv *pp = ap->private_data;
1150 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1151 u32 port_led_state = emp->led_state;
1153 /* save the desired Activity LED behavior */
1156 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1158 /* set the LED to OFF */
1159 port_led_state &= EM_MSG_LED_VALUE_OFF;
1160 port_led_state |= (ap->port_no | (link->pmp << 8));
1161 ap->ops->transmit_led_message(ap, port_led_state, 4);
1163 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1164 if (val == BLINK_OFF) {
1165 /* set LED to ON for idle */
1166 port_led_state &= EM_MSG_LED_VALUE_OFF;
1167 port_led_state |= (ap->port_no | (link->pmp << 8));
1168 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1169 ap->ops->transmit_led_message(ap, port_led_state, 4);
1172 emp->blink_policy = val;
1176 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1178 struct ata_link *link = dev->link;
1179 struct ata_port *ap = link->ap;
1180 struct ahci_port_priv *pp = ap->private_data;
1181 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1183 /* display the saved value of activity behavior for this
1186 return sprintf(buf, "%d\n", emp->blink_policy);
1189 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1190 int port_no, void __iomem *mmio,
1191 void __iomem *port_mmio)
1193 struct ahci_host_priv *hpriv = ap->host->private_data;
1194 const char *emsg = NULL;
1198 /* make sure port is not active */
1199 rc = ahci_deinit_port(ap, &emsg);
1201 dev_warn(dev, "%s (%d)\n", emsg, rc);
1204 tmp = readl(port_mmio + PORT_SCR_ERR);
1205 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1206 writel(tmp, port_mmio + PORT_SCR_ERR);
1208 /* clear port IRQ */
1209 tmp = readl(port_mmio + PORT_IRQ_STAT);
1210 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1212 writel(tmp, port_mmio + PORT_IRQ_STAT);
1214 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1216 /* mark esata ports */
1217 tmp = readl(port_mmio + PORT_CMD);
1218 if ((tmp & PORT_CMD_ESP) && (hpriv->cap & HOST_CAP_SXS))
1219 ap->pflags |= ATA_PFLAG_EXTERNAL;
1222 void ahci_init_controller(struct ata_host *host)
1224 struct ahci_host_priv *hpriv = host->private_data;
1225 void __iomem *mmio = hpriv->mmio;
1227 void __iomem *port_mmio;
1230 for (i = 0; i < host->n_ports; i++) {
1231 struct ata_port *ap = host->ports[i];
1233 port_mmio = ahci_port_base(ap);
1234 if (ata_port_is_dummy(ap))
1237 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1240 tmp = readl(mmio + HOST_CTL);
1241 VPRINTK("HOST_CTL 0x%x\n", tmp);
1242 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1243 tmp = readl(mmio + HOST_CTL);
1244 VPRINTK("HOST_CTL 0x%x\n", tmp);
1246 EXPORT_SYMBOL_GPL(ahci_init_controller);
1248 static void ahci_dev_config(struct ata_device *dev)
1250 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1252 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1253 dev->max_sectors = 255;
1255 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1259 unsigned int ahci_dev_classify(struct ata_port *ap)
1261 void __iomem *port_mmio = ahci_port_base(ap);
1262 struct ata_taskfile tf;
1265 tmp = readl(port_mmio + PORT_SIG);
1266 tf.lbah = (tmp >> 24) & 0xff;
1267 tf.lbam = (tmp >> 16) & 0xff;
1268 tf.lbal = (tmp >> 8) & 0xff;
1269 tf.nsect = (tmp) & 0xff;
1271 return ata_dev_classify(&tf);
1273 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1275 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1278 dma_addr_t cmd_tbl_dma;
1280 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1282 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1283 pp->cmd_slot[tag].status = 0;
1284 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1285 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1287 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1289 int ahci_kick_engine(struct ata_port *ap)
1291 void __iomem *port_mmio = ahci_port_base(ap);
1292 struct ahci_host_priv *hpriv = ap->host->private_data;
1293 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1298 rc = ahci_stop_engine(ap);
1303 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1305 busy = status & (ATA_BUSY | ATA_DRQ);
1306 if (!busy && !sata_pmp_attached(ap)) {
1311 if (!(hpriv->cap & HOST_CAP_CLO)) {
1317 tmp = readl(port_mmio + PORT_CMD);
1318 tmp |= PORT_CMD_CLO;
1319 writel(tmp, port_mmio + PORT_CMD);
1322 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1323 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1324 if (tmp & PORT_CMD_CLO)
1327 /* restart engine */
1329 hpriv->start_engine(ap);
1332 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1334 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1335 struct ata_taskfile *tf, int is_cmd, u16 flags,
1336 unsigned long timeout_msec)
1338 const u32 cmd_fis_len = 5; /* five dwords */
1339 struct ahci_port_priv *pp = ap->private_data;
1340 void __iomem *port_mmio = ahci_port_base(ap);
1341 u8 *fis = pp->cmd_tbl;
1344 /* prep the command */
1345 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1346 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1348 /* set port value for softreset of Port Multiplier */
1349 if (pp->fbs_enabled && pp->fbs_last_dev != pmp) {
1350 tmp = readl(port_mmio + PORT_FBS);
1351 tmp &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1352 tmp |= pmp << PORT_FBS_DEV_OFFSET;
1353 writel(tmp, port_mmio + PORT_FBS);
1354 pp->fbs_last_dev = pmp;
1358 writel(1, port_mmio + PORT_CMD_ISSUE);
1361 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1362 0x1, 0x1, 1, timeout_msec);
1364 ahci_kick_engine(ap);
1368 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1373 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1374 int pmp, unsigned long deadline,
1375 int (*check_ready)(struct ata_link *link))
1377 struct ata_port *ap = link->ap;
1378 struct ahci_host_priv *hpriv = ap->host->private_data;
1379 struct ahci_port_priv *pp = ap->private_data;
1380 const char *reason = NULL;
1381 unsigned long now, msecs;
1382 struct ata_taskfile tf;
1383 bool fbs_disabled = false;
1388 /* prepare for SRST (AHCI-1.1 10.4.1) */
1389 rc = ahci_kick_engine(ap);
1390 if (rc && rc != -EOPNOTSUPP)
1391 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1394 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1395 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1396 * that is attached to port multiplier.
1398 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1399 ahci_disable_fbs(ap);
1400 fbs_disabled = true;
1403 ata_tf_init(link->device, &tf);
1405 /* issue the first D2H Register FIS */
1408 if (time_after(deadline, now))
1409 msecs = jiffies_to_msecs(deadline - now);
1412 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1413 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1415 reason = "1st FIS failed";
1419 /* spec says at least 5us, but be generous and sleep for 1ms */
1422 /* issue the second D2H Register FIS */
1423 tf.ctl &= ~ATA_SRST;
1424 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1426 /* wait for link to become ready */
1427 rc = ata_wait_after_reset(link, deadline, check_ready);
1428 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1430 * Workaround for cases where link online status can't
1431 * be trusted. Treat device readiness timeout as link
1434 ata_link_info(link, "device not ready, treating as offline\n");
1435 *class = ATA_DEV_NONE;
1437 /* link occupied, -ENODEV too is an error */
1438 reason = "device not ready";
1441 *class = ahci_dev_classify(ap);
1443 /* re-enable FBS if disabled before */
1445 ahci_enable_fbs(ap);
1447 DPRINTK("EXIT, class=%u\n", *class);
1451 ata_link_err(link, "softreset failed (%s)\n", reason);
1455 int ahci_check_ready(struct ata_link *link)
1457 void __iomem *port_mmio = ahci_port_base(link->ap);
1458 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1460 return ata_check_ready(status);
1462 EXPORT_SYMBOL_GPL(ahci_check_ready);
1464 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1465 unsigned long deadline)
1467 int pmp = sata_srst_pmp(link);
1471 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1473 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1475 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1477 void __iomem *port_mmio = ahci_port_base(link->ap);
1478 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1479 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1482 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1483 * which can save timeout delay.
1485 if (irq_status & PORT_IRQ_BAD_PMP)
1488 return ata_check_ready(status);
1491 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1492 unsigned long deadline)
1494 struct ata_port *ap = link->ap;
1495 void __iomem *port_mmio = ahci_port_base(ap);
1496 int pmp = sata_srst_pmp(link);
1502 rc = ahci_do_softreset(link, class, pmp, deadline,
1503 ahci_bad_pmp_check_ready);
1506 * Soft reset fails with IPMS set when PMP is enabled but
1507 * SATA HDD/ODD is connected to SATA port, do soft reset
1511 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1512 if (irq_sts & PORT_IRQ_BAD_PMP) {
1514 "applying PMP SRST workaround "
1516 rc = ahci_do_softreset(link, class, 0, deadline,
1524 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1525 unsigned long deadline)
1527 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1528 struct ata_port *ap = link->ap;
1529 struct ahci_port_priv *pp = ap->private_data;
1530 struct ahci_host_priv *hpriv = ap->host->private_data;
1531 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1532 struct ata_taskfile tf;
1538 ahci_stop_engine(ap);
1540 /* clear D2H reception area to properly wait for D2H FIS */
1541 ata_tf_init(link->device, &tf);
1542 tf.command = ATA_BUSY;
1543 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1545 rc = sata_link_hardreset(link, timing, deadline, &online,
1548 hpriv->start_engine(ap);
1551 *class = ahci_dev_classify(ap);
1553 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1557 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1559 struct ata_port *ap = link->ap;
1560 void __iomem *port_mmio = ahci_port_base(ap);
1563 ata_std_postreset(link, class);
1565 /* Make sure port's ATAPI bit is set appropriately */
1566 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1567 if (*class == ATA_DEV_ATAPI)
1568 new_tmp |= PORT_CMD_ATAPI;
1570 new_tmp &= ~PORT_CMD_ATAPI;
1571 if (new_tmp != tmp) {
1572 writel(new_tmp, port_mmio + PORT_CMD);
1573 readl(port_mmio + PORT_CMD); /* flush */
1577 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1579 struct scatterlist *sg;
1580 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1586 * Next, the S/G list.
1588 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1589 dma_addr_t addr = sg_dma_address(sg);
1590 u32 sg_len = sg_dma_len(sg);
1592 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1593 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1594 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1600 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1602 struct ata_port *ap = qc->ap;
1603 struct ahci_port_priv *pp = ap->private_data;
1605 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1606 return ata_std_qc_defer(qc);
1608 return sata_pmp_qc_defer_cmd_switch(qc);
1611 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1613 struct ata_port *ap = qc->ap;
1614 struct ahci_port_priv *pp = ap->private_data;
1615 int is_atapi = ata_is_atapi(qc->tf.protocol);
1618 const u32 cmd_fis_len = 5; /* five dwords */
1619 unsigned int n_elem;
1622 * Fill in command table information. First, the header,
1623 * a SATA Register - Host to Device command FIS.
1625 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1627 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1629 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1630 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1634 if (qc->flags & ATA_QCFLAG_DMAMAP)
1635 n_elem = ahci_fill_sg(qc, cmd_tbl);
1638 * Fill in command slot information.
1640 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1641 if (qc->tf.flags & ATA_TFLAG_WRITE)
1642 opts |= AHCI_CMD_WRITE;
1644 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1646 ahci_fill_cmd_slot(pp, qc->tag, opts);
1649 static void ahci_fbs_dec_intr(struct ata_port *ap)
1651 struct ahci_port_priv *pp = ap->private_data;
1652 void __iomem *port_mmio = ahci_port_base(ap);
1653 u32 fbs = readl(port_mmio + PORT_FBS);
1657 BUG_ON(!pp->fbs_enabled);
1659 /* time to wait for DEC is not specified by AHCI spec,
1660 * add a retry loop for safety.
1662 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1663 fbs = readl(port_mmio + PORT_FBS);
1664 while ((fbs & PORT_FBS_DEC) && retries--) {
1666 fbs = readl(port_mmio + PORT_FBS);
1669 if (fbs & PORT_FBS_DEC)
1670 dev_err(ap->host->dev, "failed to clear device error\n");
1673 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1675 struct ahci_host_priv *hpriv = ap->host->private_data;
1676 struct ahci_port_priv *pp = ap->private_data;
1677 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1678 struct ata_link *link = NULL;
1679 struct ata_queued_cmd *active_qc;
1680 struct ata_eh_info *active_ehi;
1681 bool fbs_need_dec = false;
1684 /* determine active link with error */
1685 if (pp->fbs_enabled) {
1686 void __iomem *port_mmio = ahci_port_base(ap);
1687 u32 fbs = readl(port_mmio + PORT_FBS);
1688 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1690 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1691 link = &ap->pmp_link[pmp];
1692 fbs_need_dec = true;
1696 ata_for_each_link(link, ap, EDGE)
1697 if (ata_link_active(link))
1703 active_qc = ata_qc_from_tag(ap, link->active_tag);
1704 active_ehi = &link->eh_info;
1706 /* record irq stat */
1707 ata_ehi_clear_desc(host_ehi);
1708 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1710 /* AHCI needs SError cleared; otherwise, it might lock up */
1711 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1712 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1713 host_ehi->serror |= serror;
1715 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1716 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1717 irq_stat &= ~PORT_IRQ_IF_ERR;
1719 if (irq_stat & PORT_IRQ_TF_ERR) {
1720 /* If qc is active, charge it; otherwise, the active
1721 * link. There's no active qc on NCQ errors. It will
1722 * be determined by EH by reading log page 10h.
1725 active_qc->err_mask |= AC_ERR_DEV;
1727 active_ehi->err_mask |= AC_ERR_DEV;
1729 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1730 host_ehi->serror &= ~SERR_INTERNAL;
1733 if (irq_stat & PORT_IRQ_UNK_FIS) {
1734 u32 *unk = pp->rx_fis + RX_FIS_UNK;
1736 active_ehi->err_mask |= AC_ERR_HSM;
1737 active_ehi->action |= ATA_EH_RESET;
1738 ata_ehi_push_desc(active_ehi,
1739 "unknown FIS %08x %08x %08x %08x" ,
1740 unk[0], unk[1], unk[2], unk[3]);
1743 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1744 active_ehi->err_mask |= AC_ERR_HSM;
1745 active_ehi->action |= ATA_EH_RESET;
1746 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1749 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1750 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1751 host_ehi->action |= ATA_EH_RESET;
1752 ata_ehi_push_desc(host_ehi, "host bus error");
1755 if (irq_stat & PORT_IRQ_IF_ERR) {
1757 active_ehi->err_mask |= AC_ERR_DEV;
1759 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1760 host_ehi->action |= ATA_EH_RESET;
1763 ata_ehi_push_desc(host_ehi, "interface fatal error");
1766 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1767 ata_ehi_hotplugged(host_ehi);
1768 ata_ehi_push_desc(host_ehi, "%s",
1769 irq_stat & PORT_IRQ_CONNECT ?
1770 "connection status changed" : "PHY RDY changed");
1773 /* okay, let's hand over to EH */
1775 if (irq_stat & PORT_IRQ_FREEZE)
1776 ata_port_freeze(ap);
1777 else if (fbs_need_dec) {
1778 ata_link_abort(link);
1779 ahci_fbs_dec_intr(ap);
1784 static void ahci_handle_port_interrupt(struct ata_port *ap,
1785 void __iomem *port_mmio, u32 status)
1787 struct ata_eh_info *ehi = &ap->link.eh_info;
1788 struct ahci_port_priv *pp = ap->private_data;
1789 struct ahci_host_priv *hpriv = ap->host->private_data;
1790 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1794 /* ignore BAD_PMP while resetting */
1795 if (unlikely(resetting))
1796 status &= ~PORT_IRQ_BAD_PMP;
1798 if (sata_lpm_ignore_phy_events(&ap->link)) {
1799 status &= ~PORT_IRQ_PHYRDY;
1800 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1803 if (unlikely(status & PORT_IRQ_ERROR)) {
1804 ahci_error_intr(ap, status);
1808 if (status & PORT_IRQ_SDB_FIS) {
1809 /* If SNotification is available, leave notification
1810 * handling to sata_async_notification(). If not,
1811 * emulate it by snooping SDB FIS RX area.
1813 * Snooping FIS RX area is probably cheaper than
1814 * poking SNotification but some constrollers which
1815 * implement SNotification, ICH9 for example, don't
1816 * store AN SDB FIS into receive area.
1818 if (hpriv->cap & HOST_CAP_SNTF)
1819 sata_async_notification(ap);
1821 /* If the 'N' bit in word 0 of the FIS is set,
1822 * we just received asynchronous notification.
1823 * Tell libata about it.
1825 * Lack of SNotification should not appear in
1826 * ahci 1.2, so the workaround is unnecessary
1827 * when FBS is enabled.
1829 if (pp->fbs_enabled)
1832 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1833 u32 f0 = le32_to_cpu(f[0]);
1835 sata_async_notification(ap);
1840 /* pp->active_link is not reliable once FBS is enabled, both
1841 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1842 * NCQ and non-NCQ commands may be in flight at the same time.
1844 if (pp->fbs_enabled) {
1845 if (ap->qc_active) {
1846 qc_active = readl(port_mmio + PORT_SCR_ACT);
1847 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1850 /* pp->active_link is valid iff any command is in flight */
1851 if (ap->qc_active && pp->active_link->sactive)
1852 qc_active = readl(port_mmio + PORT_SCR_ACT);
1854 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1858 rc = ata_qc_complete_multiple(ap, qc_active);
1860 /* while resetting, invalid completions are expected */
1861 if (unlikely(rc < 0 && !resetting)) {
1862 ehi->err_mask |= AC_ERR_HSM;
1863 ehi->action |= ATA_EH_RESET;
1864 ata_port_freeze(ap);
1868 static void ahci_port_intr(struct ata_port *ap)
1870 void __iomem *port_mmio = ahci_port_base(ap);
1873 status = readl(port_mmio + PORT_IRQ_STAT);
1874 writel(status, port_mmio + PORT_IRQ_STAT);
1876 ahci_handle_port_interrupt(ap, port_mmio, status);
1879 static irqreturn_t ahci_multi_irqs_intr_hard(int irq, void *dev_instance)
1881 struct ata_port *ap = dev_instance;
1882 void __iomem *port_mmio = ahci_port_base(ap);
1887 status = readl(port_mmio + PORT_IRQ_STAT);
1888 writel(status, port_mmio + PORT_IRQ_STAT);
1890 spin_lock(ap->lock);
1891 ahci_handle_port_interrupt(ap, port_mmio, status);
1892 spin_unlock(ap->lock);
1899 u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked)
1901 unsigned int i, handled = 0;
1903 for (i = 0; i < host->n_ports; i++) {
1904 struct ata_port *ap;
1906 if (!(irq_masked & (1 << i)))
1909 ap = host->ports[i];
1912 VPRINTK("port %u\n", i);
1914 VPRINTK("port %u (no irq)\n", i);
1915 if (ata_ratelimit())
1917 "interrupt on disabled port %u\n", i);
1925 EXPORT_SYMBOL_GPL(ahci_handle_port_intr);
1927 static irqreturn_t ahci_single_level_irq_intr(int irq, void *dev_instance)
1929 struct ata_host *host = dev_instance;
1930 struct ahci_host_priv *hpriv;
1931 unsigned int rc = 0;
1933 u32 irq_stat, irq_masked;
1937 hpriv = host->private_data;
1940 /* sigh. 0xffffffff is a valid return from h/w */
1941 irq_stat = readl(mmio + HOST_IRQ_STAT);
1945 irq_masked = irq_stat & hpriv->port_map;
1947 spin_lock(&host->lock);
1949 rc = ahci_handle_port_intr(host, irq_masked);
1951 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1952 * it should be cleared after all the port events are cleared;
1953 * otherwise, it will raise a spurious interrupt after each
1954 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1957 * Also, use the unmasked value to clear interrupt as spurious
1958 * pending event on a dummy port might cause screaming IRQ.
1960 writel(irq_stat, mmio + HOST_IRQ_STAT);
1962 spin_unlock(&host->lock);
1966 return IRQ_RETVAL(rc);
1969 unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1971 struct ata_port *ap = qc->ap;
1972 void __iomem *port_mmio = ahci_port_base(ap);
1973 struct ahci_port_priv *pp = ap->private_data;
1975 /* Keep track of the currently active link. It will be used
1976 * in completion path to determine whether NCQ phase is in
1979 pp->active_link = qc->dev->link;
1981 if (ata_is_ncq(qc->tf.protocol))
1982 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1984 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1985 u32 fbs = readl(port_mmio + PORT_FBS);
1986 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1987 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1988 writel(fbs, port_mmio + PORT_FBS);
1989 pp->fbs_last_dev = qc->dev->link->pmp;
1992 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1994 ahci_sw_activity(qc->dev->link);
1998 EXPORT_SYMBOL_GPL(ahci_qc_issue);
2000 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2002 struct ahci_port_priv *pp = qc->ap->private_data;
2003 u8 *rx_fis = pp->rx_fis;
2005 if (pp->fbs_enabled)
2006 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
2009 * After a successful execution of an ATA PIO data-in command,
2010 * the device doesn't send D2H Reg FIS to update the TF and
2011 * the host should take TF and E_Status from the preceding PIO
2014 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
2015 !(qc->flags & ATA_QCFLAG_FAILED)) {
2016 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
2017 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
2019 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
2024 static void ahci_freeze(struct ata_port *ap)
2026 void __iomem *port_mmio = ahci_port_base(ap);
2029 writel(0, port_mmio + PORT_IRQ_MASK);
2032 static void ahci_thaw(struct ata_port *ap)
2034 struct ahci_host_priv *hpriv = ap->host->private_data;
2035 void __iomem *mmio = hpriv->mmio;
2036 void __iomem *port_mmio = ahci_port_base(ap);
2038 struct ahci_port_priv *pp = ap->private_data;
2041 tmp = readl(port_mmio + PORT_IRQ_STAT);
2042 writel(tmp, port_mmio + PORT_IRQ_STAT);
2043 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2045 /* turn IRQ back on */
2046 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2049 void ahci_error_handler(struct ata_port *ap)
2051 struct ahci_host_priv *hpriv = ap->host->private_data;
2053 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2054 /* restart engine */
2055 ahci_stop_engine(ap);
2056 hpriv->start_engine(ap);
2059 sata_pmp_error_handler(ap);
2061 if (!ata_dev_enabled(ap->link.device))
2062 ahci_stop_engine(ap);
2064 EXPORT_SYMBOL_GPL(ahci_error_handler);
2066 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2068 struct ata_port *ap = qc->ap;
2070 /* make DMA engine forget about the failed command */
2071 if (qc->flags & ATA_QCFLAG_FAILED)
2072 ahci_kick_engine(ap);
2075 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2077 struct ahci_host_priv *hpriv = ap->host->private_data;
2078 void __iomem *port_mmio = ahci_port_base(ap);
2079 struct ata_device *dev = ap->link.device;
2080 u32 devslp, dm, dito, mdat, deto;
2082 unsigned int err_mask;
2084 devslp = readl(port_mmio + PORT_DEVSLP);
2085 if (!(devslp & PORT_DEVSLP_DSP)) {
2086 dev_info(ap->host->dev, "port does not support device sleep\n");
2090 /* disable device sleep */
2092 if (devslp & PORT_DEVSLP_ADSE) {
2093 writel(devslp & ~PORT_DEVSLP_ADSE,
2094 port_mmio + PORT_DEVSLP);
2095 err_mask = ata_dev_set_feature(dev,
2096 SETFEATURES_SATA_DISABLE,
2098 if (err_mask && err_mask != AC_ERR_DEV)
2099 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2104 /* device sleep was already enabled */
2105 if (devslp & PORT_DEVSLP_ADSE)
2108 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2109 rc = ahci_stop_engine(ap);
2113 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2114 dito = devslp_idle_timeout / (dm + 1);
2118 /* Use the nominal value 10 ms if the read MDAT is zero,
2119 * the nominal value of DETO is 20 ms.
2121 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2122 ATA_LOG_DEVSLP_VALID_MASK) {
2123 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2124 ATA_LOG_DEVSLP_MDAT_MASK;
2127 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2135 /* Make dito, mdat, deto bits to 0s */
2136 devslp &= ~GENMASK_ULL(24, 2);
2137 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2138 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2139 (deto << PORT_DEVSLP_DETO_OFFSET) |
2141 writel(devslp, port_mmio + PORT_DEVSLP);
2143 hpriv->start_engine(ap);
2145 /* enable device sleep feature for the drive */
2146 err_mask = ata_dev_set_feature(dev,
2147 SETFEATURES_SATA_ENABLE,
2149 if (err_mask && err_mask != AC_ERR_DEV)
2150 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2153 static void ahci_enable_fbs(struct ata_port *ap)
2155 struct ahci_host_priv *hpriv = ap->host->private_data;
2156 struct ahci_port_priv *pp = ap->private_data;
2157 void __iomem *port_mmio = ahci_port_base(ap);
2161 if (!pp->fbs_supported)
2164 fbs = readl(port_mmio + PORT_FBS);
2165 if (fbs & PORT_FBS_EN) {
2166 pp->fbs_enabled = true;
2167 pp->fbs_last_dev = -1; /* initialization */
2171 rc = ahci_stop_engine(ap);
2175 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2176 fbs = readl(port_mmio + PORT_FBS);
2177 if (fbs & PORT_FBS_EN) {
2178 dev_info(ap->host->dev, "FBS is enabled\n");
2179 pp->fbs_enabled = true;
2180 pp->fbs_last_dev = -1; /* initialization */
2182 dev_err(ap->host->dev, "Failed to enable FBS\n");
2184 hpriv->start_engine(ap);
2187 static void ahci_disable_fbs(struct ata_port *ap)
2189 struct ahci_host_priv *hpriv = ap->host->private_data;
2190 struct ahci_port_priv *pp = ap->private_data;
2191 void __iomem *port_mmio = ahci_port_base(ap);
2195 if (!pp->fbs_supported)
2198 fbs = readl(port_mmio + PORT_FBS);
2199 if ((fbs & PORT_FBS_EN) == 0) {
2200 pp->fbs_enabled = false;
2204 rc = ahci_stop_engine(ap);
2208 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2209 fbs = readl(port_mmio + PORT_FBS);
2210 if (fbs & PORT_FBS_EN)
2211 dev_err(ap->host->dev, "Failed to disable FBS\n");
2213 dev_info(ap->host->dev, "FBS is disabled\n");
2214 pp->fbs_enabled = false;
2217 hpriv->start_engine(ap);
2220 static void ahci_pmp_attach(struct ata_port *ap)
2222 void __iomem *port_mmio = ahci_port_base(ap);
2223 struct ahci_port_priv *pp = ap->private_data;
2226 cmd = readl(port_mmio + PORT_CMD);
2227 cmd |= PORT_CMD_PMP;
2228 writel(cmd, port_mmio + PORT_CMD);
2230 ahci_enable_fbs(ap);
2232 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2235 * We must not change the port interrupt mask register if the
2236 * port is marked frozen, the value in pp->intr_mask will be
2237 * restored later when the port is thawed.
2239 * Note that during initialization, the port is marked as
2240 * frozen since the irq handler is not yet registered.
2242 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2243 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2246 static void ahci_pmp_detach(struct ata_port *ap)
2248 void __iomem *port_mmio = ahci_port_base(ap);
2249 struct ahci_port_priv *pp = ap->private_data;
2252 ahci_disable_fbs(ap);
2254 cmd = readl(port_mmio + PORT_CMD);
2255 cmd &= ~PORT_CMD_PMP;
2256 writel(cmd, port_mmio + PORT_CMD);
2258 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2260 /* see comment above in ahci_pmp_attach() */
2261 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2262 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2265 int ahci_port_resume(struct ata_port *ap)
2267 ahci_rpm_get_port(ap);
2270 ahci_start_port(ap);
2272 if (sata_pmp_attached(ap))
2273 ahci_pmp_attach(ap);
2275 ahci_pmp_detach(ap);
2279 EXPORT_SYMBOL_GPL(ahci_port_resume);
2282 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2284 const char *emsg = NULL;
2287 rc = ahci_deinit_port(ap, &emsg);
2289 ahci_power_down(ap);
2291 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2292 ata_port_freeze(ap);
2295 ahci_rpm_put_port(ap);
2300 static int ahci_port_start(struct ata_port *ap)
2302 struct ahci_host_priv *hpriv = ap->host->private_data;
2303 struct device *dev = ap->host->dev;
2304 struct ahci_port_priv *pp;
2307 size_t dma_sz, rx_fis_sz;
2309 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2313 if (ap->host->n_ports > 1) {
2314 pp->irq_desc = devm_kzalloc(dev, 8, GFP_KERNEL);
2315 if (!pp->irq_desc) {
2316 devm_kfree(dev, pp);
2319 snprintf(pp->irq_desc, 8,
2320 "%s%d", dev_driver_string(dev), ap->port_no);
2323 /* check FBS capability */
2324 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2325 void __iomem *port_mmio = ahci_port_base(ap);
2326 u32 cmd = readl(port_mmio + PORT_CMD);
2327 if (cmd & PORT_CMD_FBSCP)
2328 pp->fbs_supported = true;
2329 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2330 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2332 pp->fbs_supported = true;
2334 dev_warn(dev, "port %d is not capable of FBS\n",
2338 if (pp->fbs_supported) {
2339 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2340 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2342 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2343 rx_fis_sz = AHCI_RX_FIS_SZ;
2346 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2349 memset(mem, 0, dma_sz);
2352 * First item in chunk of DMA memory: 32-slot command table,
2353 * 32 bytes each in size
2356 pp->cmd_slot_dma = mem_dma;
2358 mem += AHCI_CMD_SLOT_SZ;
2359 mem_dma += AHCI_CMD_SLOT_SZ;
2362 * Second item: Received-FIS area
2365 pp->rx_fis_dma = mem_dma;
2368 mem_dma += rx_fis_sz;
2371 * Third item: data area for storing a single command
2372 * and its scatter-gather table
2375 pp->cmd_tbl_dma = mem_dma;
2378 * Save off initial list of interrupts to be enabled.
2379 * This could be changed later
2381 pp->intr_mask = DEF_PORT_IRQ;
2384 * Switch to per-port locking in case each port has its own MSI vector.
2386 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2387 spin_lock_init(&pp->lock);
2388 ap->lock = &pp->lock;
2391 ap->private_data = pp;
2393 /* engage engines, captain */
2394 return ahci_port_resume(ap);
2397 static void ahci_port_stop(struct ata_port *ap)
2399 const char *emsg = NULL;
2400 struct ahci_host_priv *hpriv = ap->host->private_data;
2401 void __iomem *host_mmio = hpriv->mmio;
2404 /* de-initialize port */
2405 rc = ahci_deinit_port(ap, &emsg);
2407 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2410 * Clear GHC.IS to prevent stuck INTx after disabling MSI and
2413 writel(1 << ap->port_no, host_mmio + HOST_IRQ_STAT);
2416 void ahci_print_info(struct ata_host *host, const char *scc_s)
2418 struct ahci_host_priv *hpriv = host->private_data;
2419 u32 vers, cap, cap2, impl, speed;
2420 const char *speed_s;
2422 vers = hpriv->version;
2425 impl = hpriv->port_map;
2427 speed = (cap >> 20) & 0xf;
2430 else if (speed == 2)
2432 else if (speed == 3)
2438 "AHCI %02x%02x.%02x%02x "
2439 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2442 (vers >> 24) & 0xff,
2443 (vers >> 16) & 0xff,
2447 ((cap >> 8) & 0x1f) + 1,
2461 cap & HOST_CAP_64 ? "64bit " : "",
2462 cap & HOST_CAP_NCQ ? "ncq " : "",
2463 cap & HOST_CAP_SNTF ? "sntf " : "",
2464 cap & HOST_CAP_MPS ? "ilck " : "",
2465 cap & HOST_CAP_SSS ? "stag " : "",
2466 cap & HOST_CAP_ALPM ? "pm " : "",
2467 cap & HOST_CAP_LED ? "led " : "",
2468 cap & HOST_CAP_CLO ? "clo " : "",
2469 cap & HOST_CAP_ONLY ? "only " : "",
2470 cap & HOST_CAP_PMP ? "pmp " : "",
2471 cap & HOST_CAP_FBS ? "fbs " : "",
2472 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2473 cap & HOST_CAP_SSC ? "slum " : "",
2474 cap & HOST_CAP_PART ? "part " : "",
2475 cap & HOST_CAP_CCC ? "ccc " : "",
2476 cap & HOST_CAP_EMS ? "ems " : "",
2477 cap & HOST_CAP_SXS ? "sxs " : "",
2478 cap2 & HOST_CAP2_DESO ? "deso " : "",
2479 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2480 cap2 & HOST_CAP2_SDS ? "sds " : "",
2481 cap2 & HOST_CAP2_APST ? "apst " : "",
2482 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2483 cap2 & HOST_CAP2_BOH ? "boh " : ""
2486 EXPORT_SYMBOL_GPL(ahci_print_info);
2488 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2489 struct ata_port_info *pi)
2492 void __iomem *mmio = hpriv->mmio;
2493 u32 em_loc = readl(mmio + HOST_EM_LOC);
2494 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2496 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2499 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2503 hpriv->em_loc = ((em_loc >> 16) * 4);
2504 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2505 hpriv->em_msg_type = messages;
2506 pi->flags |= ATA_FLAG_EM;
2507 if (!(em_ctl & EM_CTL_ALHD))
2508 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2511 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2513 static int ahci_host_activate_multi_irqs(struct ata_host *host,
2514 struct scsi_host_template *sht)
2516 struct ahci_host_priv *hpriv = host->private_data;
2519 rc = ata_host_start(host);
2523 * Requests IRQs according to AHCI-1.1 when multiple MSIs were
2524 * allocated. That is one MSI per port, starting from @irq.
2526 for (i = 0; i < host->n_ports; i++) {
2527 struct ahci_port_priv *pp = host->ports[i]->private_data;
2528 int irq = hpriv->get_irq_vector(host, i);
2530 /* Do not receive interrupts sent by dummy ports */
2536 rc = devm_request_irq(host->dev, irq, ahci_multi_irqs_intr_hard,
2537 0, pp->irq_desc, host->ports[i]);
2541 ata_port_desc(host->ports[i], "irq %d", irq);
2544 return ata_host_register(host, sht);
2548 * ahci_host_activate - start AHCI host, request IRQs and register it
2549 * @host: target ATA host
2550 * @sht: scsi_host_template to use when registering the host
2553 * Inherited from calling layer (may sleep).
2556 * 0 on success, -errno otherwise.
2558 int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht)
2560 struct ahci_host_priv *hpriv = host->private_data;
2561 int irq = hpriv->irq;
2564 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI) {
2565 if (hpriv->irq_handler)
2567 "both AHCI_HFLAG_MULTI_MSI flag set and custom irq handler implemented\n");
2568 if (!hpriv->get_irq_vector) {
2570 "AHCI_HFLAG_MULTI_MSI requires ->get_irq_vector!\n");
2574 rc = ahci_host_activate_multi_irqs(host, sht);
2576 rc = ata_host_activate(host, irq, hpriv->irq_handler,
2583 EXPORT_SYMBOL_GPL(ahci_host_activate);
2585 MODULE_AUTHOR("Jeff Garzik");
2586 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2587 MODULE_LICENSE("GPL");