1 /* Generic MTRR (Memory Type Range Register) driver.
3 Copyright (C) 1997-2000 Richard Gooch
4 Copyright (c) 2002 Patrick Mochel
6 This library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Library General Public
8 License as published by the Free Software Foundation; either
9 version 2 of the License, or (at your option) any later version.
11 This library is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 Library General Public License for more details.
16 You should have received a copy of the GNU Library General Public
17 License along with this library; if not, write to the Free
18 Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 Richard Gooch may be reached by email at rgooch@atnf.csiro.au
21 The postal address is:
22 Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
24 Source: "Pentium Pro Family Developer's Manual, Volume 3:
25 Operating System Writer's Guide" (Intel document number 242692),
28 This was cleaned and made readable by Patrick Mochel <mochel@osdl.org>
30 Source: Intel Architecture Software Developers Manual, Volume 3:
31 System Programming Guide; Section 9.11. (1997 edition - PPro).
36 #include <linux/types.h> /* FIXME: kvm_para.h needs this */
38 #include <linux/kvm_para.h>
39 #include <linux/uaccess.h>
40 #include <linux/module.h>
41 #include <linux/mutex.h>
42 #include <linux/init.h>
43 #include <linux/sort.h>
44 #include <linux/cpu.h>
45 #include <linux/pci.h>
46 #include <linux/smp.h>
48 #include <asm/processor.h>
57 unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES];
58 static DEFINE_MUTEX(mtrr_mutex);
60 u64 size_or_mask, size_and_mask;
61 static bool mtrr_aps_delayed_init;
63 static struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM];
65 struct mtrr_ops *mtrr_if;
67 static void set_mtrr(unsigned int reg, unsigned long base,
68 unsigned long size, mtrr_type type);
70 void set_mtrr_ops(struct mtrr_ops *ops)
72 if (ops->vendor && ops->vendor < X86_VENDOR_NUM)
73 mtrr_ops[ops->vendor] = ops;
76 /* Returns non-zero if we have the write-combining memory type */
77 static int have_wrcomb(void)
82 dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL);
85 * ServerWorks LE chipsets < rev 6 have problems with
86 * write-combining. Don't allow it and leave room for other
87 * chipsets to be tagged
89 if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
90 dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) {
91 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
93 pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
99 * Intel 450NX errata # 23. Non ascending cacheline evictions to
100 * write combining memory may resulting in data corruption
102 if (dev->vendor == PCI_VENDOR_ID_INTEL &&
103 dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
104 pr_info("mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
110 return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0;
113 /* This function returns the number of variable MTRRs */
114 static void __init set_num_var_ranges(void)
116 unsigned long config = 0, dummy;
119 rdmsr(MSR_MTRRcap, config, dummy);
120 else if (is_cpu(AMD))
122 else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
125 num_var_ranges = config & 0xff;
128 static void __init init_table(void)
132 max = num_var_ranges;
133 for (i = 0; i < max; i++)
134 mtrr_usage_table[i] = 1;
137 struct set_mtrr_data {
140 unsigned long smp_base;
141 unsigned long smp_size;
142 unsigned int smp_reg;
147 * ipi_handler - Synchronisation handler. Executed by "other" CPUs.
151 static void ipi_handler(void *info)
154 struct set_mtrr_data *data = info;
157 local_irq_save(flags);
159 atomic_dec(&data->count);
160 while (!atomic_read(&data->gate))
163 /* The master has cleared me to execute */
164 if (data->smp_reg != ~0U) {
165 mtrr_if->set(data->smp_reg, data->smp_base,
166 data->smp_size, data->smp_type);
167 } else if (mtrr_aps_delayed_init) {
169 * Initialize the MTRRs inaddition to the synchronisation.
174 atomic_dec(&data->count);
175 while (atomic_read(&data->gate))
178 atomic_dec(&data->count);
179 local_irq_restore(flags);
183 static inline int types_compatible(mtrr_type type1, mtrr_type type2)
185 return type1 == MTRR_TYPE_UNCACHABLE ||
186 type2 == MTRR_TYPE_UNCACHABLE ||
187 (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) ||
188 (type1 == MTRR_TYPE_WRBACK && type2 == MTRR_TYPE_WRTHROUGH);
192 * set_mtrr - update mtrrs on all processors
193 * @reg: mtrr in question
198 * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly:
200 * 1. Send IPI to do the following:
201 * 2. Disable Interrupts
202 * 3. Wait for all procs to do so
203 * 4. Enter no-fill cache mode
207 * 8. Disable all range registers
208 * 9. Update the MTRRs
209 * 10. Enable all range registers
210 * 11. Flush all TLBs and caches again
211 * 12. Enter normal cache mode and reenable caching
213 * 14. Wait for buddies to catch up
214 * 15. Enable interrupts.
216 * What does that mean for us? Well, first we set data.count to the number
217 * of CPUs. As each CPU disables interrupts, it'll decrement it once. We wait
218 * until it hits 0 and proceed. We set the data.gate flag and reset data.count.
219 * Meanwhile, they are waiting for that flag to be set. Once it's set, each
220 * CPU goes through the transition of updating MTRRs.
221 * The CPU vendors may each do it differently,
222 * so we call mtrr_if->set() callback and let them take care of it.
223 * When they're done, they again decrement data->count and wait for data.gate
225 * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag
226 * Everyone then enables interrupts and we all continue on.
228 * Note that the mechanism is the same for UP systems, too; all the SMP stuff
232 set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
234 struct set_mtrr_data data;
238 data.smp_base = base;
239 data.smp_size = size;
240 data.smp_type = type;
241 atomic_set(&data.count, num_booting_cpus() - 1);
243 /* Make sure data.count is visible before unleashing other CPUs */
245 atomic_set(&data.gate, 0);
247 /* Start the ball rolling on other CPUs */
248 if (smp_call_function(ipi_handler, &data, 0) != 0)
249 panic("mtrr: timed out waiting for other CPUs\n");
251 local_irq_save(flags);
253 while (atomic_read(&data.count))
256 /* Ok, reset count and toggle gate */
257 atomic_set(&data.count, num_booting_cpus() - 1);
259 atomic_set(&data.gate, 1);
261 /* Do our MTRR business */
266 * We use this same function to initialize the mtrrs during boot,
267 * resume, runtime cpu online and on an explicit request to set a
270 * During boot or suspend, the state of the boot cpu's mtrrs has been
271 * saved, and we want to replicate that across all the cpus that come
272 * online (either at the end of boot or resume or during a runtime cpu
273 * online). If we're doing that, @reg is set to something special and on
274 * this cpu we still do mtrr_if->set_all(). During boot/resume, this
275 * is unnecessary if at this point we are still on the cpu that started
276 * the boot/resume sequence. But there is no guarantee that we are still
277 * on the same cpu. So we do mtrr_if->set_all() on this cpu aswell to be
278 * sure that we are in sync with everyone else.
281 mtrr_if->set(reg, base, size, type);
285 /* Wait for the others */
286 while (atomic_read(&data.count))
289 atomic_set(&data.count, num_booting_cpus() - 1);
291 atomic_set(&data.gate, 0);
294 * Wait here for everyone to have seen the gate change
295 * So we're the last ones to touch 'data'
297 while (atomic_read(&data.count))
300 local_irq_restore(flags);
304 * mtrr_add_page - Add a memory type region
305 * @base: Physical base address of region in pages (in units of 4 kB!)
306 * @size: Physical size of region in pages (4 kB)
307 * @type: Type of MTRR desired
308 * @increment: If this is true do usage counting on the region
310 * Memory type region registers control the caching on newer Intel and
311 * non Intel processors. This function allows drivers to request an
312 * MTRR is added. The details and hardware specifics of each processor's
313 * implementation are hidden from the caller, but nevertheless the
314 * caller should expect to need to provide a power of two size on an
315 * equivalent power of two boundary.
317 * If the region cannot be added either because all regions are in use
318 * or the CPU cannot support it a negative value is returned. On success
319 * the register number for this entry is returned, but should be treated
322 * On a multiprocessor machine the changes are made to all processors.
323 * This is required on x86 by the Intel processors.
325 * The available types are
327 * %MTRR_TYPE_UNCACHABLE - No caching
329 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
331 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
333 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
335 * BUGS: Needs a quiet flag for the cases where drivers do not mind
336 * failures and do not wish system log messages to be sent.
338 int mtrr_add_page(unsigned long base, unsigned long size,
339 unsigned int type, bool increment)
341 unsigned long lbase, lsize;
342 int i, replace, error;
348 error = mtrr_if->validate_add_page(base, size, type);
352 if (type >= MTRR_NUM_TYPES) {
353 pr_warning("mtrr: type: %u invalid\n", type);
357 /* If the type is WC, check that this processor supports it */
358 if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
359 pr_warning("mtrr: your processor doesn't support write-combining\n");
364 pr_warning("mtrr: zero sized request\n");
368 if (base & size_or_mask || size & size_or_mask) {
369 pr_warning("mtrr: base or size exceeds the MTRR width\n");
376 /* No CPU hotplug when we change MTRR entries */
379 /* Search for existing MTRR */
380 mutex_lock(&mtrr_mutex);
381 for (i = 0; i < num_var_ranges; ++i) {
382 mtrr_if->get(i, &lbase, &lsize, <ype);
383 if (!lsize || base > lbase + lsize - 1 ||
384 base + size - 1 < lbase)
387 * At this point we know there is some kind of
390 if (base < lbase || base + size - 1 > lbase + lsize - 1) {
392 base + size - 1 >= lbase + lsize - 1) {
393 /* New region encloses an existing region */
395 replace = replace == -1 ? i : -2;
397 } else if (types_compatible(type, ltype))
400 pr_warning("mtrr: 0x%lx000,0x%lx000 overlaps existing"
401 " 0x%lx000,0x%lx000\n", base, size, lbase,
405 /* New region is enclosed by an existing region */
407 if (types_compatible(type, ltype))
409 pr_warning("mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n",
410 base, size, mtrr_attrib_to_str(ltype),
411 mtrr_attrib_to_str(type));
415 ++mtrr_usage_table[i];
419 /* Search for an empty MTRR */
420 i = mtrr_if->get_free_region(base, size, replace);
422 set_mtrr(i, base, size, type);
423 if (likely(replace < 0)) {
424 mtrr_usage_table[i] = 1;
426 mtrr_usage_table[i] = mtrr_usage_table[replace];
428 mtrr_usage_table[i]++;
429 if (unlikely(replace != i)) {
430 set_mtrr(replace, 0, 0, 0);
431 mtrr_usage_table[replace] = 0;
435 pr_info("mtrr: no more MTRRs available\n");
439 mutex_unlock(&mtrr_mutex);
444 static int mtrr_check(unsigned long base, unsigned long size)
446 if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
447 pr_warning("mtrr: size and base must be multiples of 4 kiB\n");
448 pr_debug("mtrr: size: 0x%lx base: 0x%lx\n", size, base);
456 * mtrr_add - Add a memory type region
457 * @base: Physical base address of region
458 * @size: Physical size of region
459 * @type: Type of MTRR desired
460 * @increment: If this is true do usage counting on the region
462 * Memory type region registers control the caching on newer Intel and
463 * non Intel processors. This function allows drivers to request an
464 * MTRR is added. The details and hardware specifics of each processor's
465 * implementation are hidden from the caller, but nevertheless the
466 * caller should expect to need to provide a power of two size on an
467 * equivalent power of two boundary.
469 * If the region cannot be added either because all regions are in use
470 * or the CPU cannot support it a negative value is returned. On success
471 * the register number for this entry is returned, but should be treated
474 * On a multiprocessor machine the changes are made to all processors.
475 * This is required on x86 by the Intel processors.
477 * The available types are
479 * %MTRR_TYPE_UNCACHABLE - No caching
481 * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
483 * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
485 * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
487 * BUGS: Needs a quiet flag for the cases where drivers do not mind
488 * failures and do not wish system log messages to be sent.
490 int mtrr_add(unsigned long base, unsigned long size, unsigned int type,
493 if (mtrr_check(base, size))
495 return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
498 EXPORT_SYMBOL(mtrr_add);
501 * mtrr_del_page - delete a memory type region
502 * @reg: Register returned by mtrr_add
503 * @base: Physical base address
504 * @size: Size of region
506 * If register is supplied then base and size are ignored. This is
507 * how drivers should call it.
509 * Releases an MTRR region. If the usage count drops to zero the
510 * register is freed and the region returns to default state.
511 * On success the register is returned, on failure a negative error
514 int mtrr_del_page(int reg, unsigned long base, unsigned long size)
518 unsigned long lbase, lsize;
524 max = num_var_ranges;
525 /* No CPU hotplug when we change MTRR entries */
527 mutex_lock(&mtrr_mutex);
529 /* Search for existing MTRR */
530 for (i = 0; i < max; ++i) {
531 mtrr_if->get(i, &lbase, &lsize, <ype);
532 if (lbase == base && lsize == size) {
538 pr_debug("mtrr: no MTRR for %lx000,%lx000 found\n",
544 pr_warning("mtrr: register: %d too big\n", reg);
547 mtrr_if->get(reg, &lbase, &lsize, <ype);
549 pr_warning("mtrr: MTRR %d not used\n", reg);
552 if (mtrr_usage_table[reg] < 1) {
553 pr_warning("mtrr: reg: %d has count=0\n", reg);
556 if (--mtrr_usage_table[reg] < 1)
557 set_mtrr(reg, 0, 0, 0);
560 mutex_unlock(&mtrr_mutex);
566 * mtrr_del - delete a memory type region
567 * @reg: Register returned by mtrr_add
568 * @base: Physical base address
569 * @size: Size of region
571 * If register is supplied then base and size are ignored. This is
572 * how drivers should call it.
574 * Releases an MTRR region. If the usage count drops to zero the
575 * register is freed and the region returns to default state.
576 * On success the register is returned, on failure a negative error
579 int mtrr_del(int reg, unsigned long base, unsigned long size)
581 if (mtrr_check(base, size))
583 return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
585 EXPORT_SYMBOL(mtrr_del);
589 * These should be called implicitly, but we can't yet until all the initcall
592 static void __init init_ifs(void)
594 #ifndef CONFIG_X86_64
601 /* The suspend/resume methods are only for CPU without MTRR. CPU using generic
602 * MTRR driver doesn't require this
610 static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES];
612 static int mtrr_save(struct sys_device *sysdev, pm_message_t state)
616 for (i = 0; i < num_var_ranges; i++) {
617 mtrr_if->get(i, &mtrr_value[i].lbase,
618 &mtrr_value[i].lsize,
619 &mtrr_value[i].ltype);
624 static int mtrr_restore(struct sys_device *sysdev)
628 for (i = 0; i < num_var_ranges; i++) {
629 if (mtrr_value[i].lsize) {
630 set_mtrr(i, mtrr_value[i].lbase,
632 mtrr_value[i].ltype);
640 static struct sysdev_driver mtrr_sysdev_driver = {
641 .suspend = mtrr_save,
642 .resume = mtrr_restore,
645 int __initdata changed_by_mtrr_cleanup;
648 * mtrr_bp_init - initialize mtrrs on the boot CPU
650 * This needs to be called early; before any of the other CPUs are
651 * initialized (i.e. before smp_init()).
654 void __init mtrr_bp_init(void)
663 mtrr_if = &generic_mtrr_ops;
664 size_or_mask = 0xff000000; /* 36 bits */
665 size_and_mask = 0x00f00000;
669 * This is an AMD specific MSR, but we assume(hope?) that
670 * Intel will implement it to when they extend the address
673 if (cpuid_eax(0x80000000) >= 0x80000008) {
674 phys_addr = cpuid_eax(0x80000008) & 0xff;
675 /* CPUID workaround for Intel 0F33/0F34 CPU */
676 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
677 boot_cpu_data.x86 == 0xF &&
678 boot_cpu_data.x86_model == 0x3 &&
679 (boot_cpu_data.x86_mask == 0x3 ||
680 boot_cpu_data.x86_mask == 0x4))
683 size_or_mask = ~((1ULL << (phys_addr - PAGE_SHIFT)) - 1);
684 size_and_mask = ~size_or_mask & 0xfffff00000ULL;
685 } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
686 boot_cpu_data.x86 == 6) {
688 * VIA C* family have Intel style MTRRs,
689 * but don't support PAE
691 size_or_mask = 0xfff00000; /* 32 bits */
696 switch (boot_cpu_data.x86_vendor) {
698 if (cpu_has_k6_mtrr) {
699 /* Pre-Athlon (K6) AMD CPU MTRRs */
700 mtrr_if = mtrr_ops[X86_VENDOR_AMD];
701 size_or_mask = 0xfff00000; /* 32 bits */
705 case X86_VENDOR_CENTAUR:
706 if (cpu_has_centaur_mcr) {
707 mtrr_if = mtrr_ops[X86_VENDOR_CENTAUR];
708 size_or_mask = 0xfff00000; /* 32 bits */
712 case X86_VENDOR_CYRIX:
713 if (cpu_has_cyrix_arr) {
714 mtrr_if = mtrr_ops[X86_VENDOR_CYRIX];
715 size_or_mask = 0xfff00000; /* 32 bits */
725 set_num_var_ranges();
730 if (mtrr_cleanup(phys_addr)) {
731 changed_by_mtrr_cleanup = 1;
738 void mtrr_ap_init(void)
740 if (!use_intel() || mtrr_aps_delayed_init)
743 * Ideally we should hold mtrr_mutex here to avoid mtrr entries
744 * changed, but this routine will be called in cpu boot time,
745 * holding the lock breaks it.
747 * This routine is called in two cases:
749 * 1. very earily time of software resume, when there absolutely
750 * isn't mtrr entry changes;
752 * 2. cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug
753 * lock to prevent mtrr entry changes
755 set_mtrr(~0U, 0, 0, 0);
759 * Save current fixed-range MTRR state of the BSP
761 void mtrr_save_state(void)
763 smp_call_function_single(0, mtrr_save_fixed_ranges, NULL, 1);
766 void set_mtrr_aps_delayed_init(void)
771 mtrr_aps_delayed_init = true;
775 * Delayed MTRR initialization for all AP's
777 void mtrr_aps_init(void)
783 * Check if someone has requested the delay of AP MTRR initialization,
784 * by doing set_mtrr_aps_delayed_init(), prior to this point. If not,
787 if (!mtrr_aps_delayed_init)
790 set_mtrr(~0U, 0, 0, 0);
791 mtrr_aps_delayed_init = false;
794 void mtrr_bp_restore(void)
802 static int __init mtrr_init_finialize(void)
808 if (!changed_by_mtrr_cleanup)
814 * The CPU has no MTRR and seems to not support SMP. They have
815 * specific drivers, we use a tricky method to support
816 * suspend/resume for them.
818 * TBD: is there any system with such CPU which supports
819 * suspend/resume? If no, we should remove the code.
821 sysdev_driver_register(&cpu_sysdev_class, &mtrr_sysdev_driver);
825 subsys_initcall(mtrr_init_finialize);