2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_proto.h>
29 #include <asm/amd_iommu_types.h>
30 #include <asm/amd_iommu.h>
31 #include <asm/iommu.h>
33 #include <asm/x86_init.h>
36 * definitions for the ACPI scanning code
38 #define IVRS_HEADER_LENGTH 48
40 #define ACPI_IVHD_TYPE 0x10
41 #define ACPI_IVMD_TYPE_ALL 0x20
42 #define ACPI_IVMD_TYPE 0x21
43 #define ACPI_IVMD_TYPE_RANGE 0x22
45 #define IVHD_DEV_ALL 0x01
46 #define IVHD_DEV_SELECT 0x02
47 #define IVHD_DEV_SELECT_RANGE_START 0x03
48 #define IVHD_DEV_RANGE_END 0x04
49 #define IVHD_DEV_ALIAS 0x42
50 #define IVHD_DEV_ALIAS_RANGE 0x43
51 #define IVHD_DEV_EXT_SELECT 0x46
52 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
54 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
55 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
56 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
57 #define IVHD_FLAG_ISOC_EN_MASK 0x08
59 #define IVMD_FLAG_EXCL_RANGE 0x08
60 #define IVMD_FLAG_UNITY_MAP 0x01
62 #define ACPI_DEVFLAG_INITPASS 0x01
63 #define ACPI_DEVFLAG_EXTINT 0x02
64 #define ACPI_DEVFLAG_NMI 0x04
65 #define ACPI_DEVFLAG_SYSMGT1 0x10
66 #define ACPI_DEVFLAG_SYSMGT2 0x20
67 #define ACPI_DEVFLAG_LINT0 0x40
68 #define ACPI_DEVFLAG_LINT1 0x80
69 #define ACPI_DEVFLAG_ATSDIS 0x10000000
72 * ACPI table definitions
74 * These data structures are laid over the table to parse the important values
79 * structure describing one IOMMU in the ACPI table. Typically followed by one
80 * or more ivhd_entrys.
92 } __attribute__((packed));
95 * A device entry describing which devices a specific IOMMU translates and
96 * which requestor ids they use.
103 } __attribute__((packed));
106 * An AMD IOMMU memory definition structure. It defines things like exclusion
107 * ranges for devices and regions that should be unity mapped.
118 } __attribute__((packed));
122 static int __initdata amd_iommu_detected;
124 u16 amd_iommu_last_bdf; /* largest PCI device id we have
126 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
128 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
130 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
133 /* Array to assign indices to IOMMUs*/
134 struct amd_iommu *amd_iommus[MAX_IOMMUS];
135 int amd_iommus_present;
137 /* IOMMUs have a non-present cache? */
138 bool amd_iommu_np_cache __read_mostly;
141 * The ACPI table parsing functions set this variable on an error
143 static int __initdata amd_iommu_init_err;
146 * List of protection domains - used during resume
148 LIST_HEAD(amd_iommu_pd_list);
149 spinlock_t amd_iommu_pd_lock;
152 * Pointer to the device table which is shared by all AMD IOMMUs
153 * it is indexed by the PCI device id or the HT unit id and contains
154 * information about the domain the device belongs to as well as the
155 * page table root pointer.
157 struct dev_table_entry *amd_iommu_dev_table;
160 * The alias table is a driver specific data structure which contains the
161 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
162 * More than one device can share the same requestor id.
164 u16 *amd_iommu_alias_table;
167 * The rlookup table is used to find the IOMMU which is responsible
168 * for a specific device. It is also indexed by the PCI device id.
170 struct amd_iommu **amd_iommu_rlookup_table;
173 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
174 * to know which ones are already in use.
176 unsigned long *amd_iommu_pd_alloc_bitmap;
178 static u32 dev_table_size; /* size of the device table */
179 static u32 alias_table_size; /* size of the alias table */
180 static u32 rlookup_table_size; /* size if the rlookup table */
182 static inline void update_last_devid(u16 devid)
184 if (devid > amd_iommu_last_bdf)
185 amd_iommu_last_bdf = devid;
188 static inline unsigned long tbl_size(int entry_size)
190 unsigned shift = PAGE_SHIFT +
191 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
196 /****************************************************************************
198 * AMD IOMMU MMIO register space handling functions
200 * These functions are used to program the IOMMU device registers in
201 * MMIO space required for that driver.
203 ****************************************************************************/
206 * This function set the exclusion range in the IOMMU. DMA accesses to the
207 * exclusion range are passed through untranslated
209 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
211 u64 start = iommu->exclusion_start & PAGE_MASK;
212 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
215 if (!iommu->exclusion_start)
218 entry = start | MMIO_EXCL_ENABLE_MASK;
219 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
220 &entry, sizeof(entry));
223 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
224 &entry, sizeof(entry));
227 /* Programs the physical address of the device table into the IOMMU hardware */
228 static void __init iommu_set_device_table(struct amd_iommu *iommu)
232 BUG_ON(iommu->mmio_base == NULL);
234 entry = virt_to_phys(amd_iommu_dev_table);
235 entry |= (dev_table_size >> 12) - 1;
236 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
237 &entry, sizeof(entry));
240 /* Generic functions to enable/disable certain features of the IOMMU. */
241 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
245 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
247 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
250 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
254 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
256 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
259 /* Function to enable the hardware */
260 static void iommu_enable(struct amd_iommu *iommu)
262 printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n",
263 dev_name(&iommu->dev->dev), iommu->cap_ptr);
265 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
268 static void iommu_disable(struct amd_iommu *iommu)
270 /* Disable command buffer */
271 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
273 /* Disable event logging and event interrupts */
274 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
275 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
277 /* Disable IOMMU hardware itself */
278 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
282 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
283 * the system has one.
285 static u8 * __init iommu_map_mmio_space(u64 address)
289 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
290 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
292 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
296 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
300 release_mem_region(address, MMIO_REGION_LENGTH);
305 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
307 if (iommu->mmio_base)
308 iounmap(iommu->mmio_base);
309 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
312 /****************************************************************************
314 * The functions below belong to the first pass of AMD IOMMU ACPI table
315 * parsing. In this pass we try to find out the highest device id this
316 * code has to handle. Upon this information the size of the shared data
317 * structures is determined later.
319 ****************************************************************************/
322 * This function calculates the length of a given IVHD entry
324 static inline int ivhd_entry_length(u8 *ivhd)
326 return 0x04 << (*ivhd >> 6);
330 * This function reads the last device id the IOMMU has to handle from the PCI
331 * capability header for this IOMMU
333 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
337 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
338 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
344 * After reading the highest device id from the IOMMU PCI capability header
345 * this function looks if there is a higher device id defined in the ACPI table
347 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
349 u8 *p = (void *)h, *end = (void *)h;
350 struct ivhd_entry *dev;
355 find_last_devid_on_pci(PCI_BUS(h->devid),
361 dev = (struct ivhd_entry *)p;
363 case IVHD_DEV_SELECT:
364 case IVHD_DEV_RANGE_END:
366 case IVHD_DEV_EXT_SELECT:
367 /* all the above subfield types refer to device ids */
368 update_last_devid(dev->devid);
373 p += ivhd_entry_length(p);
382 * Iterate over all IVHD entries in the ACPI table and find the highest device
383 * id which we need to handle. This is the first of three functions which parse
384 * the ACPI table. So we check the checksum here.
386 static int __init find_last_devid_acpi(struct acpi_table_header *table)
389 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
390 struct ivhd_header *h;
393 * Validate checksum here so we don't need to do it when
394 * we actually parse the table
396 for (i = 0; i < table->length; ++i)
399 /* ACPI table corrupt */
400 amd_iommu_init_err = -ENODEV;
404 p += IVRS_HEADER_LENGTH;
406 end += table->length;
408 h = (struct ivhd_header *)p;
411 find_last_devid_from_ivhd(h);
423 /****************************************************************************
425 * The following functions belong the the code path which parses the ACPI table
426 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
427 * data structures, initialize the device/alias/rlookup table and also
428 * basically initialize the hardware.
430 ****************************************************************************/
433 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
434 * write commands to that buffer later and the IOMMU will execute them
437 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
439 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
440 get_order(CMD_BUFFER_SIZE));
445 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
451 * This function resets the command buffer if the IOMMU stopped fetching
454 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
456 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
458 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
459 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
461 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
465 * This function writes the command buffer address to the hardware and
468 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
472 BUG_ON(iommu->cmd_buf == NULL);
474 entry = (u64)virt_to_phys(iommu->cmd_buf);
475 entry |= MMIO_CMD_SIZE_512;
477 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
478 &entry, sizeof(entry));
480 amd_iommu_reset_cmd_buffer(iommu);
481 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
484 static void __init free_command_buffer(struct amd_iommu *iommu)
486 free_pages((unsigned long)iommu->cmd_buf,
487 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
490 /* allocates the memory where the IOMMU will log its events to */
491 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
493 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
494 get_order(EVT_BUFFER_SIZE));
496 if (iommu->evt_buf == NULL)
499 iommu->evt_buf_size = EVT_BUFFER_SIZE;
501 return iommu->evt_buf;
504 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
508 BUG_ON(iommu->evt_buf == NULL);
510 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
512 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
513 &entry, sizeof(entry));
515 /* set head and tail to zero manually */
516 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
517 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
519 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
522 static void __init free_event_buffer(struct amd_iommu *iommu)
524 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
527 /* sets a specific bit in the device table entry. */
528 static void set_dev_entry_bit(u16 devid, u8 bit)
530 int i = (bit >> 5) & 0x07;
531 int _bit = bit & 0x1f;
533 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
536 static int get_dev_entry_bit(u16 devid, u8 bit)
538 int i = (bit >> 5) & 0x07;
539 int _bit = bit & 0x1f;
541 return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
545 void amd_iommu_apply_erratum_63(u16 devid)
549 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
550 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
553 set_dev_entry_bit(devid, DEV_ENTRY_IW);
556 /* Writes the specific IOMMU for a device into the rlookup table */
557 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
559 amd_iommu_rlookup_table[devid] = iommu;
563 * This function takes the device specific flags read from the ACPI
564 * table and sets up the device table entry with that information
566 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
567 u16 devid, u32 flags, u32 ext_flags)
569 if (flags & ACPI_DEVFLAG_INITPASS)
570 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
571 if (flags & ACPI_DEVFLAG_EXTINT)
572 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
573 if (flags & ACPI_DEVFLAG_NMI)
574 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
575 if (flags & ACPI_DEVFLAG_SYSMGT1)
576 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
577 if (flags & ACPI_DEVFLAG_SYSMGT2)
578 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
579 if (flags & ACPI_DEVFLAG_LINT0)
580 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
581 if (flags & ACPI_DEVFLAG_LINT1)
582 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
584 amd_iommu_apply_erratum_63(devid);
586 set_iommu_for_device(iommu, devid);
590 * Reads the device exclusion range from ACPI and initialize IOMMU with
593 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
595 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
597 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
602 * We only can configure exclusion ranges per IOMMU, not
603 * per device. But we can enable the exclusion range per
604 * device. This is done here
606 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
607 iommu->exclusion_start = m->range_start;
608 iommu->exclusion_length = m->range_length;
613 * This function reads some important data from the IOMMU PCI space and
614 * initializes the driver data structure with it. It reads the hardware
615 * capabilities and the first/last device entries
617 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
619 int cap_ptr = iommu->cap_ptr;
622 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
624 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
626 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
629 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
631 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
633 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
637 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
638 * initializes the hardware and our data structures with it.
640 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
641 struct ivhd_header *h)
644 u8 *end = p, flags = 0;
645 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
648 struct ivhd_entry *e;
651 * First set the recommended feature enable bits from ACPI
652 * into the IOMMU control registers
654 h->flags & IVHD_FLAG_HT_TUN_EN_MASK ?
655 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
656 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
658 h->flags & IVHD_FLAG_PASSPW_EN_MASK ?
659 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
660 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
662 h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
663 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
664 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
666 h->flags & IVHD_FLAG_ISOC_EN_MASK ?
667 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
668 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
671 * make IOMMU memory accesses cache coherent
673 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
676 * Done. Now parse the device entries
678 p += sizeof(struct ivhd_header);
683 e = (struct ivhd_entry *)p;
687 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
688 " last device %02x:%02x.%x flags: %02x\n",
689 PCI_BUS(iommu->first_device),
690 PCI_SLOT(iommu->first_device),
691 PCI_FUNC(iommu->first_device),
692 PCI_BUS(iommu->last_device),
693 PCI_SLOT(iommu->last_device),
694 PCI_FUNC(iommu->last_device),
697 for (dev_i = iommu->first_device;
698 dev_i <= iommu->last_device; ++dev_i)
699 set_dev_entry_from_acpi(iommu, dev_i,
702 case IVHD_DEV_SELECT:
704 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
712 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
714 case IVHD_DEV_SELECT_RANGE_START:
716 DUMP_printk(" DEV_SELECT_RANGE_START\t "
717 "devid: %02x:%02x.%x flags: %02x\n",
723 devid_start = e->devid;
730 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
731 "flags: %02x devid_to: %02x:%02x.%x\n",
736 PCI_BUS(e->ext >> 8),
737 PCI_SLOT(e->ext >> 8),
738 PCI_FUNC(e->ext >> 8));
741 devid_to = e->ext >> 8;
742 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
743 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
744 amd_iommu_alias_table[devid] = devid_to;
746 case IVHD_DEV_ALIAS_RANGE:
748 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
749 "devid: %02x:%02x.%x flags: %02x "
750 "devid_to: %02x:%02x.%x\n",
755 PCI_BUS(e->ext >> 8),
756 PCI_SLOT(e->ext >> 8),
757 PCI_FUNC(e->ext >> 8));
759 devid_start = e->devid;
761 devid_to = e->ext >> 8;
765 case IVHD_DEV_EXT_SELECT:
767 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
768 "flags: %02x ext: %08x\n",
775 set_dev_entry_from_acpi(iommu, devid, e->flags,
778 case IVHD_DEV_EXT_SELECT_RANGE:
780 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
781 "%02x:%02x.%x flags: %02x ext: %08x\n",
787 devid_start = e->devid;
792 case IVHD_DEV_RANGE_END:
794 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
800 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
802 amd_iommu_alias_table[dev_i] = devid_to;
803 set_dev_entry_from_acpi(iommu,
804 devid_to, flags, ext_flags);
806 set_dev_entry_from_acpi(iommu, dev_i,
814 p += ivhd_entry_length(p);
818 /* Initializes the device->iommu mapping for the driver */
819 static int __init init_iommu_devices(struct amd_iommu *iommu)
823 for (i = iommu->first_device; i <= iommu->last_device; ++i)
824 set_iommu_for_device(iommu, i);
829 static void __init free_iommu_one(struct amd_iommu *iommu)
831 free_command_buffer(iommu);
832 free_event_buffer(iommu);
833 iommu_unmap_mmio_space(iommu);
836 static void __init free_iommu_all(void)
838 struct amd_iommu *iommu, *next;
840 for_each_iommu_safe(iommu, next) {
841 list_del(&iommu->list);
842 free_iommu_one(iommu);
848 * This function clues the initialization function for one IOMMU
849 * together and also allocates the command buffer and programs the
850 * hardware. It does NOT enable the IOMMU. This is done afterwards.
852 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
854 spin_lock_init(&iommu->lock);
856 /* Add IOMMU to internal data structures */
857 list_add_tail(&iommu->list, &amd_iommu_list);
858 iommu->index = amd_iommus_present++;
860 if (unlikely(iommu->index >= MAX_IOMMUS)) {
861 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
865 /* Index is fine - add IOMMU to the array */
866 amd_iommus[iommu->index] = iommu;
869 * Copy data from ACPI table entry to the iommu struct
871 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
875 iommu->cap_ptr = h->cap_ptr;
876 iommu->pci_seg = h->pci_seg;
877 iommu->mmio_phys = h->mmio_phys;
878 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
879 if (!iommu->mmio_base)
882 iommu->cmd_buf = alloc_command_buffer(iommu);
886 iommu->evt_buf = alloc_event_buffer(iommu);
890 iommu->int_enabled = false;
892 init_iommu_from_pci(iommu);
893 init_iommu_from_acpi(iommu, h);
894 init_iommu_devices(iommu);
896 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
897 amd_iommu_np_cache = true;
899 return pci_enable_device(iommu->dev);
903 * Iterates over all IOMMU entries in the ACPI table, allocates the
904 * IOMMU structure and initializes it with init_iommu_one()
906 static int __init init_iommu_all(struct acpi_table_header *table)
908 u8 *p = (u8 *)table, *end = (u8 *)table;
909 struct ivhd_header *h;
910 struct amd_iommu *iommu;
913 end += table->length;
914 p += IVRS_HEADER_LENGTH;
917 h = (struct ivhd_header *)p;
921 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
922 "seg: %d flags: %01x info %04x\n",
923 PCI_BUS(h->devid), PCI_SLOT(h->devid),
924 PCI_FUNC(h->devid), h->cap_ptr,
925 h->pci_seg, h->flags, h->info);
926 DUMP_printk(" mmio-addr: %016llx\n",
929 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
931 amd_iommu_init_err = -ENOMEM;
935 ret = init_iommu_one(iommu, h);
937 amd_iommu_init_err = ret;
952 /****************************************************************************
954 * The following functions initialize the MSI interrupts for all IOMMUs
955 * in the system. Its a bit challenging because there could be multiple
956 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
959 ****************************************************************************/
961 static int iommu_setup_msi(struct amd_iommu *iommu)
965 if (pci_enable_msi(iommu->dev))
968 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
974 pci_disable_msi(iommu->dev);
978 iommu->int_enabled = true;
979 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
984 static int iommu_init_msi(struct amd_iommu *iommu)
986 if (iommu->int_enabled)
989 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
990 return iommu_setup_msi(iommu);
995 /****************************************************************************
997 * The next functions belong to the third pass of parsing the ACPI
998 * table. In this last pass the memory mapping requirements are
999 * gathered (like exclusion and unity mapping reanges).
1001 ****************************************************************************/
1003 static void __init free_unity_maps(void)
1005 struct unity_map_entry *entry, *next;
1007 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1008 list_del(&entry->list);
1013 /* called when we find an exclusion range definition in ACPI */
1014 static int __init init_exclusion_range(struct ivmd_header *m)
1019 case ACPI_IVMD_TYPE:
1020 set_device_exclusion_range(m->devid, m);
1022 case ACPI_IVMD_TYPE_ALL:
1023 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1024 set_device_exclusion_range(i, m);
1026 case ACPI_IVMD_TYPE_RANGE:
1027 for (i = m->devid; i <= m->aux; ++i)
1028 set_device_exclusion_range(i, m);
1037 /* called for unity map ACPI definition */
1038 static int __init init_unity_map_range(struct ivmd_header *m)
1040 struct unity_map_entry *e = 0;
1043 e = kzalloc(sizeof(*e), GFP_KERNEL);
1051 case ACPI_IVMD_TYPE:
1052 s = "IVMD_TYPEi\t\t\t";
1053 e->devid_start = e->devid_end = m->devid;
1055 case ACPI_IVMD_TYPE_ALL:
1056 s = "IVMD_TYPE_ALL\t\t";
1058 e->devid_end = amd_iommu_last_bdf;
1060 case ACPI_IVMD_TYPE_RANGE:
1061 s = "IVMD_TYPE_RANGE\t\t";
1062 e->devid_start = m->devid;
1063 e->devid_end = m->aux;
1066 e->address_start = PAGE_ALIGN(m->range_start);
1067 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1068 e->prot = m->flags >> 1;
1070 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1071 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1072 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1073 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1074 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1075 e->address_start, e->address_end, m->flags);
1077 list_add_tail(&e->list, &amd_iommu_unity_map);
1082 /* iterates over all memory definitions we find in the ACPI table */
1083 static int __init init_memory_definitions(struct acpi_table_header *table)
1085 u8 *p = (u8 *)table, *end = (u8 *)table;
1086 struct ivmd_header *m;
1088 end += table->length;
1089 p += IVRS_HEADER_LENGTH;
1092 m = (struct ivmd_header *)p;
1093 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1094 init_exclusion_range(m);
1095 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1096 init_unity_map_range(m);
1105 * Init the device table to not allow DMA access for devices and
1106 * suppress all page faults
1108 static void init_device_table(void)
1112 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1113 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1114 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1119 * This function finally enables all IOMMUs found in the system after
1120 * they have been initialized
1122 static void enable_iommus(void)
1124 struct amd_iommu *iommu;
1126 for_each_iommu(iommu) {
1127 iommu_disable(iommu);
1128 iommu_set_device_table(iommu);
1129 iommu_enable_command_buffer(iommu);
1130 iommu_enable_event_buffer(iommu);
1131 iommu_set_exclusion_range(iommu);
1132 iommu_init_msi(iommu);
1133 iommu_enable(iommu);
1137 static void disable_iommus(void)
1139 struct amd_iommu *iommu;
1141 for_each_iommu(iommu)
1142 iommu_disable(iommu);
1146 * Suspend/Resume support
1147 * disable suspend until real resume implemented
1150 static int amd_iommu_resume(struct sys_device *dev)
1152 /* re-load the hardware */
1156 * we have to flush after the IOMMUs are enabled because a
1157 * disabled IOMMU will never execute the commands we send
1159 amd_iommu_flush_all_devices();
1160 amd_iommu_flush_all_domains();
1165 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
1167 /* disable IOMMUs to go out of the way for BIOS */
1173 static struct sysdev_class amd_iommu_sysdev_class = {
1174 .name = "amd_iommu",
1175 .suspend = amd_iommu_suspend,
1176 .resume = amd_iommu_resume,
1179 static struct sys_device device_amd_iommu = {
1181 .cls = &amd_iommu_sysdev_class,
1185 * This is the core init function for AMD IOMMU hardware in the system.
1186 * This function is called from the generic x86 DMA layer initialization
1189 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1192 * 1 pass) Find the highest PCI device id the driver has to handle.
1193 * Upon this information the size of the data structures is
1194 * determined that needs to be allocated.
1196 * 2 pass) Initialize the data structures just allocated with the
1197 * information in the ACPI table about available AMD IOMMUs
1198 * in the system. It also maps the PCI devices in the
1199 * system to specific IOMMUs
1201 * 3 pass) After the basic data structures are allocated and
1202 * initialized we update them with information about memory
1203 * remapping requirements parsed out of the ACPI table in
1206 * After that the hardware is initialized and ready to go. In the last
1207 * step we do some Linux specific things like registering the driver in
1208 * the dma_ops interface and initializing the suspend/resume support
1209 * functions. Finally it prints some information about AMD IOMMUs and
1210 * the driver state and enables the hardware.
1212 static int __init amd_iommu_init(void)
1217 * First parse ACPI tables to find the largest Bus/Dev/Func
1218 * we need to handle. Upon this information the shared data
1219 * structures for the IOMMUs in the system will be allocated
1221 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1224 ret = amd_iommu_init_err;
1228 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1229 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1230 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1234 /* Device table - directly used by all IOMMUs */
1235 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1236 get_order(dev_table_size));
1237 if (amd_iommu_dev_table == NULL)
1241 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1242 * IOMMU see for that device
1244 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1245 get_order(alias_table_size));
1246 if (amd_iommu_alias_table == NULL)
1249 /* IOMMU rlookup table - find the IOMMU for a specific device */
1250 amd_iommu_rlookup_table = (void *)__get_free_pages(
1251 GFP_KERNEL | __GFP_ZERO,
1252 get_order(rlookup_table_size));
1253 if (amd_iommu_rlookup_table == NULL)
1256 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1257 GFP_KERNEL | __GFP_ZERO,
1258 get_order(MAX_DOMAIN_ID/8));
1259 if (amd_iommu_pd_alloc_bitmap == NULL)
1262 /* init the device table */
1263 init_device_table();
1266 * let all alias entries point to itself
1268 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1269 amd_iommu_alias_table[i] = i;
1272 * never allocate domain 0 because its used as the non-allocated and
1273 * error value placeholder
1275 amd_iommu_pd_alloc_bitmap[0] = 1;
1277 spin_lock_init(&amd_iommu_pd_lock);
1280 * now the data structures are allocated and basically initialized
1281 * start the real acpi table scan
1284 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1287 if (amd_iommu_init_err) {
1288 ret = amd_iommu_init_err;
1292 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1295 if (amd_iommu_init_err) {
1296 ret = amd_iommu_init_err;
1300 ret = sysdev_class_register(&amd_iommu_sysdev_class);
1304 ret = sysdev_register(&device_amd_iommu);
1308 ret = amd_iommu_init_devices();
1314 if (iommu_pass_through)
1315 ret = amd_iommu_init_passthrough();
1317 ret = amd_iommu_init_dma_ops();
1322 amd_iommu_init_api();
1324 amd_iommu_init_notifier();
1326 if (iommu_pass_through)
1329 if (amd_iommu_unmap_flush)
1330 printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
1332 printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
1334 x86_platform.iommu_shutdown = disable_iommus;
1342 amd_iommu_uninit_devices();
1344 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1345 get_order(MAX_DOMAIN_ID/8));
1347 free_pages((unsigned long)amd_iommu_rlookup_table,
1348 get_order(rlookup_table_size));
1350 free_pages((unsigned long)amd_iommu_alias_table,
1351 get_order(alias_table_size));
1353 free_pages((unsigned long)amd_iommu_dev_table,
1354 get_order(dev_table_size));
1360 #ifdef CONFIG_GART_IOMMU
1362 * We failed to initialize the AMD IOMMU - try fallback to GART
1372 /****************************************************************************
1374 * Early detect code. This code runs at IOMMU detection time in the DMA
1375 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1378 ****************************************************************************/
1379 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1384 void __init amd_iommu_detect(void)
1386 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1389 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1391 amd_iommu_detected = 1;
1392 x86_init.iommu.iommu_init = amd_iommu_init;
1394 /* Make sure ACS will be enabled */
1399 /****************************************************************************
1401 * Parsing functions for the AMD IOMMU specific kernel command line
1404 ****************************************************************************/
1406 static int __init parse_amd_iommu_dump(char *str)
1408 amd_iommu_dump = true;
1413 static int __init parse_amd_iommu_options(char *str)
1415 for (; *str; ++str) {
1416 if (strncmp(str, "fullflush", 9) == 0)
1417 amd_iommu_unmap_flush = true;
1423 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1424 __setup("amd_iommu=", parse_amd_iommu_options);