Linux-libre 5.4.48-gnu
[librecmc/linux-libre.git] / arch / x86 / include / asm / io.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_IO_H
3 #define _ASM_X86_IO_H
4
5 /*
6  * This file contains the definitions for the x86 IO instructions
7  * inb/inw/inl/outb/outw/outl and the "string versions" of the same
8  * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
9  * versions of the single-IO instructions (inb_p/inw_p/..).
10  *
11  * This file is not meant to be obfuscating: it's just complicated
12  * to (a) handle it all in a way that makes gcc able to optimize it
13  * as well as possible and (b) trying to avoid writing the same thing
14  * over and over again with slight variations and possibly making a
15  * mistake somewhere.
16  */
17
18 /*
19  * Thanks to James van Artsdalen for a better timing-fix than
20  * the two short jumps: using outb's to a nonexistent port seems
21  * to guarantee better timings even on fast machines.
22  *
23  * On the other hand, I'd like to be sure of a non-existent port:
24  * I feel a bit unsafe about using 0x80 (should be safe, though)
25  *
26  *              Linus
27  */
28
29  /*
30   *  Bit simplified and optimized by Jan Hubicka
31   *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
32   *
33   *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
34   *  isa_read[wl] and isa_write[wl] fixed
35   *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
36   */
37
38 #define ARCH_HAS_IOREMAP_WC
39 #define ARCH_HAS_IOREMAP_WT
40
41 #include <linux/string.h>
42 #include <linux/compiler.h>
43 #include <asm/page.h>
44 #include <asm/early_ioremap.h>
45 #include <asm/pgtable_types.h>
46
47 #define build_mmio_read(name, size, type, reg, barrier) \
48 static inline type name(const volatile void __iomem *addr) \
49 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \
50 :"m" (*(volatile type __force *)addr) barrier); return ret; }
51
52 #define build_mmio_write(name, size, type, reg, barrier) \
53 static inline void name(type val, volatile void __iomem *addr) \
54 { asm volatile("mov" size " %0,%1": :reg (val), \
55 "m" (*(volatile type __force *)addr) barrier); }
56
57 build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
58 build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
59 build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
60
61 build_mmio_read(__readb, "b", unsigned char, "=q", )
62 build_mmio_read(__readw, "w", unsigned short, "=r", )
63 build_mmio_read(__readl, "l", unsigned int, "=r", )
64
65 build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
66 build_mmio_write(writew, "w", unsigned short, "r", :"memory")
67 build_mmio_write(writel, "l", unsigned int, "r", :"memory")
68
69 build_mmio_write(__writeb, "b", unsigned char, "q", )
70 build_mmio_write(__writew, "w", unsigned short, "r", )
71 build_mmio_write(__writel, "l", unsigned int, "r", )
72
73 #define readb readb
74 #define readw readw
75 #define readl readl
76 #define readb_relaxed(a) __readb(a)
77 #define readw_relaxed(a) __readw(a)
78 #define readl_relaxed(a) __readl(a)
79 #define __raw_readb __readb
80 #define __raw_readw __readw
81 #define __raw_readl __readl
82
83 #define writeb writeb
84 #define writew writew
85 #define writel writel
86 #define writeb_relaxed(v, a) __writeb(v, a)
87 #define writew_relaxed(v, a) __writew(v, a)
88 #define writel_relaxed(v, a) __writel(v, a)
89 #define __raw_writeb __writeb
90 #define __raw_writew __writew
91 #define __raw_writel __writel
92
93 #ifdef CONFIG_X86_64
94
95 build_mmio_read(readq, "q", u64, "=r", :"memory")
96 build_mmio_read(__readq, "q", u64, "=r", )
97 build_mmio_write(writeq, "q", u64, "r", :"memory")
98 build_mmio_write(__writeq, "q", u64, "r", )
99
100 #define readq_relaxed(a)        __readq(a)
101 #define writeq_relaxed(v, a)    __writeq(v, a)
102
103 #define __raw_readq             __readq
104 #define __raw_writeq            __writeq
105
106 /* Let people know that we have them */
107 #define readq                   readq
108 #define writeq                  writeq
109
110 #endif
111
112 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
113 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
114 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
115
116 /**
117  *      virt_to_phys    -       map virtual addresses to physical
118  *      @address: address to remap
119  *
120  *      The returned physical address is the physical (CPU) mapping for
121  *      the memory address given. It is only valid to use this function on
122  *      addresses directly mapped or allocated via kmalloc.
123  *
124  *      This function does not give bus mappings for DMA transfers. In
125  *      almost all conceivable cases a device driver should not be using
126  *      this function
127  */
128
129 static inline phys_addr_t virt_to_phys(volatile void *address)
130 {
131         return __pa(address);
132 }
133 #define virt_to_phys virt_to_phys
134
135 /**
136  *      phys_to_virt    -       map physical address to virtual
137  *      @address: address to remap
138  *
139  *      The returned virtual address is a current CPU mapping for
140  *      the memory address given. It is only valid to use this function on
141  *      addresses that have a kernel mapping
142  *
143  *      This function does not handle bus mappings for DMA transfers. In
144  *      almost all conceivable cases a device driver should not be using
145  *      this function
146  */
147
148 static inline void *phys_to_virt(phys_addr_t address)
149 {
150         return __va(address);
151 }
152 #define phys_to_virt phys_to_virt
153
154 /*
155  * Change "struct page" to physical address.
156  */
157 #define page_to_phys(page)    ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
158
159 /*
160  * ISA I/O bus memory addresses are 1:1 with the physical address.
161  * However, we truncate the address to unsigned int to avoid undesirable
162  * promitions in legacy drivers.
163  */
164 static inline unsigned int isa_virt_to_bus(volatile void *address)
165 {
166         return (unsigned int)virt_to_phys(address);
167 }
168 #define isa_bus_to_virt         phys_to_virt
169
170 /*
171  * However PCI ones are not necessarily 1:1 and therefore these interfaces
172  * are forbidden in portable PCI drivers.
173  *
174  * Allow them on x86 for legacy drivers, though.
175  */
176 #define virt_to_bus virt_to_phys
177 #define bus_to_virt phys_to_virt
178
179 /*
180  * The default ioremap() behavior is non-cached; if you need something
181  * else, you probably want one of the following.
182  */
183 extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
184 #define ioremap_nocache ioremap_nocache
185 extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size);
186 #define ioremap_uc ioremap_uc
187 extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
188 #define ioremap_cache ioremap_cache
189 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, unsigned long prot_val);
190 #define ioremap_prot ioremap_prot
191 extern void __iomem *ioremap_encrypted(resource_size_t phys_addr, unsigned long size);
192 #define ioremap_encrypted ioremap_encrypted
193
194 /**
195  * ioremap     -   map bus memory into CPU space
196  * @offset:    bus address of the memory
197  * @size:      size of the resource to map
198  *
199  * ioremap performs a platform specific sequence of operations to
200  * make bus memory CPU accessible via the readb/readw/readl/writeb/
201  * writew/writel functions and the other mmio helpers. The returned
202  * address is not guaranteed to be usable directly as a virtual
203  * address.
204  *
205  * If the area you are trying to map is a PCI BAR you should have a
206  * look at pci_iomap().
207  */
208 static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
209 {
210         return ioremap_nocache(offset, size);
211 }
212 #define ioremap ioremap
213
214 extern void iounmap(volatile void __iomem *addr);
215 #define iounmap iounmap
216
217 extern void set_iounmap_nonlazy(void);
218
219 #ifdef __KERNEL__
220
221 void memcpy_fromio(void *, const volatile void __iomem *, size_t);
222 void memcpy_toio(volatile void __iomem *, const void *, size_t);
223 void memset_io(volatile void __iomem *, int, size_t);
224
225 #define memcpy_fromio memcpy_fromio
226 #define memcpy_toio memcpy_toio
227 #define memset_io memset_io
228
229 #include <asm-generic/iomap.h>
230
231 /*
232  * ISA space is 'always mapped' on a typical x86 system, no need to
233  * explicitly ioremap() it. The fact that the ISA IO space is mapped
234  * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
235  * are physical addresses. The following constant pointer can be
236  * used as the IO-area pointer (it can be iounmapped as well, so the
237  * analogy with PCI is quite large):
238  */
239 #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
240
241 #endif /* __KERNEL__ */
242
243 extern void native_io_delay(void);
244
245 extern int io_delay_type;
246 extern void io_delay_init(void);
247
248 #if defined(CONFIG_PARAVIRT)
249 #include <asm/paravirt.h>
250 #else
251
252 static inline void slow_down_io(void)
253 {
254         native_io_delay();
255 #ifdef REALLY_SLOW_IO
256         native_io_delay();
257         native_io_delay();
258         native_io_delay();
259 #endif
260 }
261
262 #endif
263
264 #ifdef CONFIG_AMD_MEM_ENCRYPT
265 #include <linux/jump_label.h>
266
267 extern struct static_key_false sev_enable_key;
268 static inline bool sev_key_active(void)
269 {
270         return static_branch_unlikely(&sev_enable_key);
271 }
272
273 #else /* !CONFIG_AMD_MEM_ENCRYPT */
274
275 static inline bool sev_key_active(void) { return false; }
276
277 #endif /* CONFIG_AMD_MEM_ENCRYPT */
278
279 #define BUILDIO(bwl, bw, type)                                          \
280 static inline void out##bwl(unsigned type value, int port)              \
281 {                                                                       \
282         asm volatile("out" #bwl " %" #bw "0, %w1"                       \
283                      : : "a"(value), "Nd"(port));                       \
284 }                                                                       \
285                                                                         \
286 static inline unsigned type in##bwl(int port)                           \
287 {                                                                       \
288         unsigned type value;                                            \
289         asm volatile("in" #bwl " %w1, %" #bw "0"                        \
290                      : "=a"(value) : "Nd"(port));                       \
291         return value;                                                   \
292 }                                                                       \
293                                                                         \
294 static inline void out##bwl##_p(unsigned type value, int port)          \
295 {                                                                       \
296         out##bwl(value, port);                                          \
297         slow_down_io();                                                 \
298 }                                                                       \
299                                                                         \
300 static inline unsigned type in##bwl##_p(int port)                       \
301 {                                                                       \
302         unsigned type value = in##bwl(port);                            \
303         slow_down_io();                                                 \
304         return value;                                                   \
305 }                                                                       \
306                                                                         \
307 static inline void outs##bwl(int port, const void *addr, unsigned long count) \
308 {                                                                       \
309         if (sev_key_active()) {                                         \
310                 unsigned type *value = (unsigned type *)addr;           \
311                 while (count) {                                         \
312                         out##bwl(*value, port);                         \
313                         value++;                                        \
314                         count--;                                        \
315                 }                                                       \
316         } else {                                                        \
317                 asm volatile("rep; outs" #bwl                           \
318                              : "+S"(addr), "+c"(count)                  \
319                              : "d"(port) : "memory");                   \
320         }                                                               \
321 }                                                                       \
322                                                                         \
323 static inline void ins##bwl(int port, void *addr, unsigned long count)  \
324 {                                                                       \
325         if (sev_key_active()) {                                         \
326                 unsigned type *value = (unsigned type *)addr;           \
327                 while (count) {                                         \
328                         *value = in##bwl(port);                         \
329                         value++;                                        \
330                         count--;                                        \
331                 }                                                       \
332         } else {                                                        \
333                 asm volatile("rep; ins" #bwl                            \
334                              : "+D"(addr), "+c"(count)                  \
335                              : "d"(port) : "memory");                   \
336         }                                                               \
337 }
338
339 BUILDIO(b, b, char)
340 BUILDIO(w, w, short)
341 BUILDIO(l, , int)
342
343 #define inb inb
344 #define inw inw
345 #define inl inl
346 #define inb_p inb_p
347 #define inw_p inw_p
348 #define inl_p inl_p
349 #define insb insb
350 #define insw insw
351 #define insl insl
352
353 #define outb outb
354 #define outw outw
355 #define outl outl
356 #define outb_p outb_p
357 #define outw_p outw_p
358 #define outl_p outl_p
359 #define outsb outsb
360 #define outsw outsw
361 #define outsl outsl
362
363 extern void *xlate_dev_mem_ptr(phys_addr_t phys);
364 extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
365
366 #define xlate_dev_mem_ptr xlate_dev_mem_ptr
367 #define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
368
369 extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
370                                 enum page_cache_mode pcm);
371 extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
372 #define ioremap_wc ioremap_wc
373 extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size);
374 #define ioremap_wt ioremap_wt
375
376 extern bool is_early_ioremap_ptep(pte_t *ptep);
377
378 #define IO_SPACE_LIMIT 0xffff
379
380 #include <asm-generic/io.h>
381 #undef PCI_IOBASE
382
383 #ifdef CONFIG_MTRR
384 extern int __must_check arch_phys_wc_index(int handle);
385 #define arch_phys_wc_index arch_phys_wc_index
386
387 extern int __must_check arch_phys_wc_add(unsigned long base,
388                                          unsigned long size);
389 extern void arch_phys_wc_del(int handle);
390 #define arch_phys_wc_add arch_phys_wc_add
391 #endif
392
393 #ifdef CONFIG_X86_PAT
394 extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size);
395 extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size);
396 #define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc
397 #endif
398
399 extern bool arch_memremap_can_ram_remap(resource_size_t offset,
400                                         unsigned long size,
401                                         unsigned long flags);
402 #define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
403
404 extern bool phys_mem_access_encrypted(unsigned long phys_addr,
405                                       unsigned long size);
406
407 #endif /* _ASM_X86_IO_H */