1 #ifndef _ASM_X86_APIC_H
2 #define _ASM_X86_APIC_H
4 #include <linux/cpumask.h>
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/apicdef.h>
10 #include <linux/atomic.h>
11 #include <asm/fixmap.h>
12 #include <asm/mpspec.h>
16 #define ARCH_APICTIMER_STOPS_ON_C3 1
22 #define APIC_VERBOSE 1
26 * Define the default level of output to be very little
27 * This can be turned up by using apic=verbose for more
28 * information and apic=debug for _lots_ of information.
29 * apic_verbosity is defined in apic.c
31 #define apic_printk(v, s, a...) do { \
32 if ((v) <= apic_verbosity) \
37 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
38 extern void generic_apic_probe(void);
40 static inline void generic_apic_probe(void)
45 #ifdef CONFIG_X86_LOCAL_APIC
47 extern unsigned int apic_verbosity;
48 extern int local_apic_timer_c2_ok;
50 extern int disable_apic;
51 extern unsigned int lapic_timer_frequency;
54 extern void __inquire_remote_apic(int apicid);
55 #else /* CONFIG_SMP */
56 static inline void __inquire_remote_apic(int apicid)
59 #endif /* CONFIG_SMP */
61 static inline void default_inquire_remote_apic(int apicid)
63 if (apic_verbosity >= APIC_DEBUG)
64 __inquire_remote_apic(apicid);
68 * With 82489DX we can't rely on apic feature bit
69 * retrieved via cpuid but still have to deal with
70 * such an apic chip so we assume that SMP configuration
71 * is found from MP table (64bit case uses ACPI mostly
72 * which set smp presence flag as well so we are safe
73 * to use this helper too).
75 static inline bool apic_from_smp_config(void)
77 return smp_found_config && !disable_apic;
81 * Basic functions accessing APICs.
83 #ifdef CONFIG_PARAVIRT
84 #include <asm/paravirt.h>
87 extern int setup_profiling_timer(unsigned int);
89 static inline void native_apic_mem_write(u32 reg, u32 v)
91 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
93 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
94 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
95 ASM_OUTPUT2("0" (v), "m" (*addr)));
98 static inline u32 native_apic_mem_read(u32 reg)
100 return *((volatile u32 *)(APIC_BASE + reg));
103 extern void native_apic_wait_icr_idle(void);
104 extern u32 native_safe_apic_wait_icr_idle(void);
105 extern void native_apic_icr_write(u32 low, u32 id);
106 extern u64 native_apic_icr_read(void);
108 static inline bool apic_is_x2apic_enabled(void)
112 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
114 return msr & X2APIC_ENABLE;
117 extern void enable_IR_x2apic(void);
119 extern int get_physical_broadcast(void);
121 extern int lapic_get_maxlvt(void);
122 extern void clear_local_APIC(void);
123 extern void disconnect_bsp_APIC(int virt_wire_setup);
124 extern void disable_local_APIC(void);
125 extern void lapic_shutdown(void);
126 extern void sync_Arb_IDs(void);
127 extern void init_bsp_APIC(void);
128 extern void setup_local_APIC(void);
129 extern void init_apic_mappings(void);
130 void register_lapic_address(unsigned long address);
131 extern void setup_boot_APIC_clock(void);
132 extern void setup_secondary_APIC_clock(void);
133 extern int APIC_init_uniprocessor(void);
136 static inline int apic_force_enable(unsigned long addr)
141 extern int apic_force_enable(unsigned long addr);
144 extern int apic_bsp_setup(bool upmode);
145 extern void apic_ap_setup(void);
148 * On 32bit this is mach-xxx local
151 extern int apic_is_clustered_box(void);
153 static inline int apic_is_clustered_box(void)
159 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
161 #else /* !CONFIG_X86_LOCAL_APIC */
162 static inline void lapic_shutdown(void) { }
163 #define local_apic_timer_c2_ok 1
164 static inline void init_apic_mappings(void) { }
165 static inline void disable_local_APIC(void) { }
166 # define setup_boot_APIC_clock x86_init_noop
167 # define setup_secondary_APIC_clock x86_init_noop
168 #endif /* !CONFIG_X86_LOCAL_APIC */
170 #ifdef CONFIG_X86_X2APIC
172 * Make previous memory operations globally visible before
173 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
176 static inline void x2apic_wrmsr_fence(void)
178 asm volatile("mfence" : : : "memory");
181 static inline void native_apic_msr_write(u32 reg, u32 v)
183 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
187 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
190 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
192 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
195 static inline u32 native_apic_msr_read(u32 reg)
202 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
206 static inline void native_x2apic_wait_icr_idle(void)
208 /* no need to wait for icr idle in x2apic */
212 static inline u32 native_safe_x2apic_wait_icr_idle(void)
214 /* no need to wait for icr idle in x2apic */
218 static inline void native_x2apic_icr_write(u32 low, u32 id)
220 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
223 static inline u64 native_x2apic_icr_read(void)
227 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
231 extern int x2apic_mode;
232 extern int x2apic_phys;
233 extern void __init check_x2apic(void);
234 extern void x2apic_setup(void);
235 static inline int x2apic_enabled(void)
237 return cpu_has_x2apic && apic_is_x2apic_enabled();
240 #define x2apic_supported() (cpu_has_x2apic)
241 #else /* !CONFIG_X86_X2APIC */
242 static inline void check_x2apic(void) { }
243 static inline void x2apic_setup(void) { }
244 static inline int x2apic_enabled(void) { return 0; }
246 #define x2apic_mode (0)
247 #define x2apic_supported() (0)
248 #endif /* !CONFIG_X86_X2APIC */
251 #define SET_APIC_ID(x) (apic->set_apic_id(x))
257 * Copyright 2004 James Cleverdon, IBM.
258 * Subject to the GNU Public License, v.2
260 * Generic APIC sub-arch data struct.
262 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
263 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
270 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
271 int (*apic_id_valid)(int apicid);
272 int (*apic_id_registered)(void);
274 u32 irq_delivery_mode;
277 const struct cpumask *(*target_cpus)(void);
282 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
284 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
285 const struct cpumask *mask);
286 void (*init_apic_ldr)(void);
288 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
290 void (*setup_apic_routing)(void);
291 int (*cpu_present_to_apicid)(int mps_cpu);
292 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
293 int (*check_phys_apicid_present)(int phys_apicid);
294 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
296 unsigned int (*get_apic_id)(unsigned long x);
297 unsigned long (*set_apic_id)(unsigned int id);
298 unsigned long apic_id_mask;
300 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
301 const struct cpumask *andmask,
302 unsigned int *apicid);
305 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
306 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
308 void (*send_IPI_allbutself)(int vector);
309 void (*send_IPI_all)(int vector);
310 void (*send_IPI_self)(int vector);
312 /* wakeup_secondary_cpu */
313 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
315 void (*inquire_remote_apic)(int apicid);
318 u32 (*read)(u32 reg);
319 void (*write)(u32 reg, u32 v);
321 * ->eoi_write() has the same signature as ->write().
323 * Drivers can support both ->eoi_write() and ->write() by passing the same
324 * callback value. Kernel can override ->eoi_write() and fall back
327 void (*eoi_write)(u32 reg, u32 v);
328 u64 (*icr_read)(void);
329 void (*icr_write)(u32 low, u32 high);
330 void (*wait_icr_idle)(void);
331 u32 (*safe_wait_icr_idle)(void);
335 * Called very early during boot from get_smp_config(). It should
336 * return the logical apicid. x86_[bios]_cpu_to_apicid is
337 * initialized before this function is called.
339 * If logical apicid can't be determined that early, the function
340 * may return BAD_APICID. Logical apicid will be configured after
341 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
342 * won't be applied properly during early boot in this case.
344 int (*x86_32_early_logical_apicid)(int cpu);
349 * Pointer to the local APIC driver in use on this system (there's
350 * always just one such driver in use - the kernel decides via an
351 * early probing process which one it picks - and then sticks to it):
353 extern struct apic *apic;
356 * APIC drivers are probed based on how they are listed in the .apicdrivers
357 * section. So the order is important and enforced by the ordering
358 * of different apic driver files in the Makefile.
360 * For the files having two apic drivers, we use apic_drivers()
361 * to enforce the order with in them.
363 #define apic_driver(sym) \
364 static const struct apic *__apicdrivers_##sym __used \
365 __aligned(sizeof(struct apic *)) \
366 __section(.apicdrivers) = { &sym }
368 #define apic_drivers(sym1, sym2) \
369 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
370 __aligned(sizeof(struct apic *)) \
371 __section(.apicdrivers) = { &sym1, &sym2 }
373 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
376 * APIC functionality to boot other CPUs - only used on SMP:
379 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
382 #ifdef CONFIG_X86_LOCAL_APIC
384 static inline u32 apic_read(u32 reg)
386 return apic->read(reg);
389 static inline void apic_write(u32 reg, u32 val)
391 apic->write(reg, val);
394 static inline void apic_eoi(void)
396 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
399 static inline u64 apic_icr_read(void)
401 return apic->icr_read();
404 static inline void apic_icr_write(u32 low, u32 high)
406 apic->icr_write(low, high);
409 static inline void apic_wait_icr_idle(void)
411 apic->wait_icr_idle();
414 static inline u32 safe_apic_wait_icr_idle(void)
416 return apic->safe_wait_icr_idle();
419 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
421 #else /* CONFIG_X86_LOCAL_APIC */
423 static inline u32 apic_read(u32 reg) { return 0; }
424 static inline void apic_write(u32 reg, u32 val) { }
425 static inline void apic_eoi(void) { }
426 static inline u64 apic_icr_read(void) { return 0; }
427 static inline void apic_icr_write(u32 low, u32 high) { }
428 static inline void apic_wait_icr_idle(void) { }
429 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
430 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
432 #endif /* CONFIG_X86_LOCAL_APIC */
434 static inline void ack_APIC_irq(void)
437 * ack_APIC_irq() actually gets compiled as a single instruction
443 static inline unsigned default_get_apic_id(unsigned long x)
445 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
447 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
448 return (x >> 24) & 0xFF;
450 return (x >> 24) & 0x0F;
454 * Warm reset vector position:
456 #define TRAMPOLINE_PHYS_LOW 0x467
457 #define TRAMPOLINE_PHYS_HIGH 0x469
460 extern void apic_send_IPI_self(int vector);
462 DECLARE_PER_CPU(int, x2apic_extra_bits);
464 extern int default_cpu_present_to_apicid(int mps_cpu);
465 extern int default_check_phys_apicid_present(int phys_apicid);
468 extern void generic_bigsmp_probe(void);
471 #ifdef CONFIG_X86_LOCAL_APIC
475 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
477 static inline const struct cpumask *default_target_cpus(void)
480 return cpu_online_mask;
482 return cpumask_of(0);
486 static inline const struct cpumask *online_target_cpus(void)
488 return cpu_online_mask;
491 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
494 static inline unsigned int read_apic_id(void)
498 reg = apic_read(APIC_ID);
500 return apic->get_apic_id(reg);
503 static inline int default_apic_id_valid(int apicid)
505 return (apicid < 255);
508 extern int default_acpi_madt_oem_check(char *, char *);
510 extern void default_setup_apic_routing(void);
512 extern struct apic apic_noop;
516 static inline int noop_x86_32_early_logical_apicid(int cpu)
522 * Set up the logical destination ID.
524 * Intel recommends to set DFR, LDR and TPR before enabling
525 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
526 * document number 292116). So here it goes...
528 extern void default_init_apic_ldr(void);
530 static inline int default_apic_id_registered(void)
532 return physid_isset(read_apic_id(), phys_cpu_present_map);
535 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
537 return cpuid_apic >> index_msb;
543 flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
544 const struct cpumask *andmask,
545 unsigned int *apicid)
547 unsigned long cpu_mask = cpumask_bits(cpumask)[0] &
548 cpumask_bits(andmask)[0] &
549 cpumask_bits(cpu_online_mask)[0] &
552 if (likely(cpu_mask)) {
553 *apicid = (unsigned int)cpu_mask;
561 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
562 const struct cpumask *andmask,
563 unsigned int *apicid);
566 flat_vector_allocation_domain(int cpu, struct cpumask *retmask,
567 const struct cpumask *mask)
569 /* Careful. Some cpus do not strictly honor the set of cpus
570 * specified in the interrupt destination when using lowest
571 * priority interrupt delivery mode.
573 * In particular there was a hyperthreading cpu observed to
574 * deliver interrupts to the wrong hyperthread when only one
575 * hyperthread was specified in the interrupt desitination.
577 cpumask_clear(retmask);
578 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
582 default_vector_allocation_domain(int cpu, struct cpumask *retmask,
583 const struct cpumask *mask)
585 cpumask_copy(retmask, cpumask_of(cpu));
588 static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
590 return physid_isset(apicid, *map);
593 static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
598 static inline int __default_cpu_present_to_apicid(int mps_cpu)
600 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
601 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
607 __default_check_phys_apicid_present(int phys_apicid)
609 return physid_isset(phys_apicid, phys_cpu_present_map);
613 static inline int default_cpu_present_to_apicid(int mps_cpu)
615 return __default_cpu_present_to_apicid(mps_cpu);
619 default_check_phys_apicid_present(int phys_apicid)
621 return __default_check_phys_apicid_present(phys_apicid);
624 extern int default_cpu_present_to_apicid(int mps_cpu);
625 extern int default_check_phys_apicid_present(int phys_apicid);
628 #endif /* CONFIG_X86_LOCAL_APIC */
629 extern void irq_enter(void);
630 extern void irq_exit(void);
632 static inline void entering_irq(void)
638 static inline void entering_ack_irq(void)
644 static inline void ipi_entering_ack_irq(void)
650 static inline void exiting_irq(void)
655 static inline void exiting_ack_irq(void)
658 /* Ack only at the end to avoid potential reentry */
662 extern void ioapic_zap_locks(void);
664 #endif /* _ASM_X86_APIC_H */