arch/sparc/mm/init_64.c

   1 /*
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/initrd.h>
  17 #include <linux/swap.h>
  18 #include <linux/pagemap.h>
  19 #include <linux/poison.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cache.h>
  24 #include <linux/sort.h>
  25 #include <linux/percpu.h>
  26 #include <linux/memblock.h>
  27 #include <linux/mmzone.h>
  28 #include <linux/gfp.h>
  29
  30 #include <asm/head.h>
  31 #include <asm/page.h>
  32 #include <asm/pgalloc.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/oplib.h>
  35 #include <asm/iommu.h>
  36 #include <asm/io.h>
  37 #include <asm/uaccess.h>
  38 #include <asm/mmu_context.h>
  39 #include <asm/tlbflush.h>
  40 #include <asm/dma.h>
  41 #include <asm/starfire.h>
  42 #include <asm/tlb.h>
  43 #include <asm/spitfire.h>
  44 #include <asm/sections.h>
  45 #include <asm/tsb.h>
  46 #include <asm/hypervisor.h>
  47 #include <asm/prom.h>
  48 #include <asm/mdesc.h>
  49 #include <asm/cpudata.h>
  50 #include <asm/setup.h>
  51 #include <asm/irq.h>
  52
  53 #include "init_64.h"
  54
  55 unsigned long kern_linear_pte_xor[4] __read_mostly;
  56
  57 /* A bitmap, two bits for every 256MB of physical memory.  These two
  58  * bits determine what page size we use for kernel linear
  59  * translations.  They form an index into kern_linear_pte_xor[].  The
  60  * value in the indexed slot is XOR'd with the TLB miss virtual
  61  * address to form the resulting TTE.  The mapping is:
  62  *
  63  *      0       ==>     4MB
  64  *      1       ==>     256MB
  65  *      2       ==>     2GB
  66  *      3       ==>     16GB
  67  *
  68  * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
  69  * support 2GB pages, and hopefully future cpus will support the 16GB
  70  * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
  71  * if these larger page sizes are not supported by the cpu.
  72  *
  73  * It would be nice to determine this from the machine description
  74  * 'cpu' properties, but we need to have this table setup before the
  75  * MDESC is initialized.
  76  */
  77
  78 #ifndef CONFIG_DEBUG_PAGEALLOC
  79 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
  80  * Space is allocated for this right after the trap table in
  81  * arch/sparc64/kernel/head.S
  82  */
  83 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
  84 #endif
  85 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
  86
  87 static unsigned long cpu_pgsz_mask;
  88
  89 #define MAX_BANKS       1024
  90
  91 static struct linux_prom64_registers pavail[MAX_BANKS];
  92 static int pavail_ents;
  93
  94 static int cmp_p64(const void *a, const void *b)
  95 {
  96         const struct linux_prom64_registers *x = a, *y = b;
  97
  98         if (x->phys_addr > y->phys_addr)
  99                 return 1;
 100         if (x->phys_addr < y->phys_addr)
 101                 return -1;
 102         return 0;
 103 }
 104
 105 static void __init read_obp_memory(const char *property,
 106                                    struct linux_prom64_registers *regs,
 107                                    int *num_ents)
 108 {
 109         phandle node = prom_finddevice("/memory");
 110         int prop_size = prom_getproplen(node, property);
 111         int ents, ret, i;
 112
 113         ents = prop_size / sizeof(struct linux_prom64_registers);
 114         if (ents > MAX_BANKS) {
 115                 prom_printf("The machine has more %s property entries than "
 116                             "this kernel can support (%d).\n",
 117                             property, MAX_BANKS);
 118                 prom_halt();
 119         }
 120
 121         ret = prom_getproperty(node, property, (char *) regs, prop_size);
 122         if (ret == -1) {
 123                 prom_printf("Couldn't get %s property from /memory.\n",
 124                                 property);
 125                 prom_halt();
 126         }
 127
 128         /* Sanitize what we got from the firmware, by page aligning
 129          * everything.
 130          */
 131         for (i = 0; i < ents; i++) {
 132                 unsigned long base, size;
 133
 134                 base = regs[i].phys_addr;
 135                 size = regs[i].reg_size;
 136
 137                 size &= PAGE_MASK;
 138                 if (base & ~PAGE_MASK) {
 139                         unsigned long new_base = PAGE_ALIGN(base);
 140
 141                         size -= new_base - base;
 142                         if ((long) size < 0L)
 143                                 size = 0UL;
 144                         base = new_base;
 145                 }
 146                 if (size == 0UL) {
 147                         /* If it is empty, simply get rid of it.
 148                          * This simplifies the logic of the other
 149                          * functions that process these arrays.
 150                          */
 151                         memmove(&regs[i], &regs[i + 1],
 152                                 (ents - i - 1) * sizeof(regs[0]));
 153                         i--;
 154                         ents--;
 155                         continue;
 156                 }
 157                 regs[i].phys_addr = base;
 158                 regs[i].reg_size = size;
 159         }
 160
 161         *num_ents = ents;
 162
 163         sort(regs, ents, sizeof(struct linux_prom64_registers),
 164              cmp_p64, NULL);
 165 }
 166
 167 /* Kernel physical address base and size in bytes.  */
 168 unsigned long kern_base __read_mostly;
 169 unsigned long kern_size __read_mostly;
 170
 171 /* Initial ramdisk setup */
 172 extern unsigned long sparc_ramdisk_image64;
 173 extern unsigned int sparc_ramdisk_image;
 174 extern unsigned int sparc_ramdisk_size;
 175
 176 struct page *mem_map_zero __read_mostly;
 177 EXPORT_SYMBOL(mem_map_zero);
 178
 179 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 180
 181 unsigned long sparc64_kern_pri_context __read_mostly;
 182 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 183 unsigned long sparc64_kern_sec_context __read_mostly;
 184
 185 int num_kernel_image_mappings;
 186
 187 #ifdef CONFIG_DEBUG_DCFLUSH
 188 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 189 #ifdef CONFIG_SMP
 190 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 191 #endif
 192 #endif
 193
 194 inline void flush_dcache_page_impl(struct page *page)
 195 {
 196         BUG_ON(tlb_type == hypervisor);
 197 #ifdef CONFIG_DEBUG_DCFLUSH
 198         atomic_inc(&dcpage_flushes);
 199 #endif
 200
 201 #ifdef DCACHE_ALIASING_POSSIBLE
 202         __flush_dcache_page(page_address(page),
 203                             ((tlb_type == spitfire) &&
 204                              page_mapping(page) != NULL));
 205 #else
 206         if (page_mapping(page) != NULL &&
 207             tlb_type == spitfire)
 208                 __flush_icache_page(__pa(page_address(page)));
 209 #endif
 210 }
 211
 212 #define PG_dcache_dirty         PG_arch_1
 213 #define PG_dcache_cpu_shift     32UL
 214 #define PG_dcache_cpu_mask      \
 215         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
 216
 217 #define dcache_dirty_cpu(page) \
 218         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 219
 220 static inline void set_dcache_dirty(struct page *page, int this_cpu)
 221 {
 222         unsigned long mask = this_cpu;
 223         unsigned long non_cpu_bits;
 224
 225         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 226         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 227
 228         __asm__ __volatile__("1:\n\t"
 229                              "ldx       [%2], %%g7\n\t"
 230                              "and       %%g7, %1, %%g1\n\t"
 231                              "or        %%g1, %0, %%g1\n\t"
 232                              "casx      [%2], %%g7, %%g1\n\t"
 233                              "cmp       %%g7, %%g1\n\t"
 234                              "bne,pn    %%xcc, 1b\n\t"
 235                              " nop"
 236                              : /* no outputs */
 237                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 238                              : "g1", "g7");
 239 }
 240
 241 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 242 {
 243         unsigned long mask = (1UL << PG_dcache_dirty);
 244
 245         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 246                              "1:\n\t"
 247                              "ldx       [%2], %%g7\n\t"
 248                              "srlx      %%g7, %4, %%g1\n\t"
 249                              "and       %%g1, %3, %%g1\n\t"
 250                              "cmp       %%g1, %0\n\t"
 251                              "bne,pn    %%icc, 2f\n\t"
 252                              " andn     %%g7, %1, %%g1\n\t"
 253                              "casx      [%2], %%g7, %%g1\n\t"
 254                              "cmp       %%g7, %%g1\n\t"
 255                              "bne,pn    %%xcc, 1b\n\t"
 256                              " nop\n"
 257                              "2:"
 258                              : /* no outputs */
 259                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 260                                "i" (PG_dcache_cpu_mask),
 261                                "i" (PG_dcache_cpu_shift)
 262                              : "g1", "g7");
 263 }
 264
 265 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 266 {
 267         unsigned long tsb_addr = (unsigned long) ent;
 268
 269         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
 270                 tsb_addr = __pa(tsb_addr);
 271
 272         __tsb_insert(tsb_addr, tag, pte);
 273 }
 274
 275 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
 276
 277 static void flush_dcache(unsigned long pfn)
 278 {
 279         struct page *page;
 280
 281         page = pfn_to_page(pfn);
 282         if (page) {
 283                 unsigned long pg_flags;
 284
 285                 pg_flags = page->flags;
 286                 if (pg_flags & (1UL << PG_dcache_dirty)) {
 287                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 288                                    PG_dcache_cpu_mask);
 289                         int this_cpu = get_cpu();
 290
 291                         /* This is just to optimize away some function calls
 292                          * in the SMP case.
 293                          */
 294                         if (cpu == this_cpu)
 295                                 flush_dcache_page_impl(page);
 296                         else
 297                                 smp_flush_dcache_page_impl(page, cpu);
 298
 299                         clear_dcache_dirty_cpu(page, cpu);
 300
 301                         put_cpu();
 302                 }
 303         }
 304 }
 305
 306 /* mm->context.lock must be held */
 307 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
 308                                     unsigned long tsb_hash_shift, unsigned long address,
 309                                     unsigned long tte)
 310 {
 311         struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
 312         unsigned long tag;
 313
 314         if (unlikely(!tsb))
 315                 return;
 316
 317         tsb += ((address >> tsb_hash_shift) &
 318                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
 319         tag = (address >> 22UL);
 320         tsb_insert(tsb, tag, tte);
 321 }
 322
 323 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
 324 static inline bool is_hugetlb_pte(pte_t pte)
 325 {
 326         if ((tlb_type == hypervisor &&
 327              (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
 328             (tlb_type != hypervisor &&
 329              (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
 330                 return true;
 331         return false;
 332 }
 333 #endif
 334
 335 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 336 {
 337         struct mm_struct *mm;
 338         unsigned long flags;
 339         pte_t pte = *ptep;
 340
 341         if (tlb_type != hypervisor) {
 342                 unsigned long pfn = pte_pfn(pte);
 343
 344                 if (pfn_valid(pfn))
 345                         flush_dcache(pfn);
 346         }
 347
 348         mm = vma->vm_mm;
 349
 350         /* Don't insert a non-valid PTE into the TSB, we'll deadlock.  */
 351         if (!pte_accessible(mm, pte))
 352                 return;
 353
 354         spin_lock_irqsave(&mm->context.lock, flags);
 355
 356 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
 357         if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
 358                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
 359                                         address, pte_val(pte));
 360         else
 361 #endif
 362                 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
 363                                         address, pte_val(pte));
 364
 365         spin_unlock_irqrestore(&mm->context.lock, flags);
 366 }
 367
 368 void flush_dcache_page(struct page *page)
 369 {
 370         struct address_space *mapping;
 371         int this_cpu;
 372
 373         if (tlb_type == hypervisor)
 374                 return;
 375
 376         /* Do not bother with the expensive D-cache flush if it
 377          * is merely the zero page.  The 'bigcore' testcase in GDB
 378          * causes this case to run millions of times.
 379          */
 380         if (page == ZERO_PAGE(0))
 381                 return;
 382
 383         this_cpu = get_cpu();
 384
 385         mapping = page_mapping(page);
 386         if (mapping && !mapping_mapped(mapping)) {
 387                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 388                 if (dirty) {
 389                         int dirty_cpu = dcache_dirty_cpu(page);
 390
 391                         if (dirty_cpu == this_cpu)
 392                                 goto out;
 393                         smp_flush_dcache_page_impl(page, dirty_cpu);
 394                 }
 395                 set_dcache_dirty(page, this_cpu);
 396         } else {
 397                 /* We could delay the flush for the !page_mapping
 398                  * case too.  But that case is for exec env/arg
 399                  * pages and those are %99 certainly going to get
 400                  * faulted into the tlb (and thus flushed) anyways.
 401                  */
 402                 flush_dcache_page_impl(page);
 403         }
 404
 405 out:
 406         put_cpu();
 407 }
 408 EXPORT_SYMBOL(flush_dcache_page);
 409
 410 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 411 {
 412         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
 413         if (tlb_type == spitfire) {
 414                 unsigned long kaddr;
 415
 416                 /* This code only runs on Spitfire cpus so this is
 417                  * why we can assume _PAGE_PADDR_4U.
 418                  */
 419                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
 420                         unsigned long paddr, mask = _PAGE_PADDR_4U;
 421
 422                         if (kaddr >= PAGE_OFFSET)
 423                                 paddr = kaddr & mask;
 424                         else {
 425                                 pgd_t *pgdp = pgd_offset_k(kaddr);
 426                                 pud_t *pudp = pud_offset(pgdp, kaddr);
 427                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
 428                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
 429
 430                                 paddr = pte_val(*ptep) & mask;
 431                         }
 432                         __flush_icache_page(paddr);
 433                 }
 434         }
 435 }
 436 EXPORT_SYMBOL(flush_icache_range);
 437
 438 void mmu_info(struct seq_file *m)
 439 {
 440         static const char *pgsz_strings[] = {
 441                 "8K", "64K", "512K", "4MB", "32MB",
 442                 "256MB", "2GB", "16GB",
 443         };
 444         int i, printed;
 445
 446         if (tlb_type == cheetah)
 447                 seq_printf(m, "MMU Type\t: Cheetah\n");
 448         else if (tlb_type == cheetah_plus)
 449                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 450         else if (tlb_type == spitfire)
 451                 seq_printf(m, "MMU Type\t: Spitfire\n");
 452         else if (tlb_type == hypervisor)
 453                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
 454         else
 455                 seq_printf(m, "MMU Type\t: ???\n");
 456
 457         seq_printf(m, "MMU PGSZs\t: ");
 458         printed = 0;
 459         for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
 460                 if (cpu_pgsz_mask & (1UL << i)) {
 461                         seq_printf(m, "%s%s",
 462                                    printed ? "," : "", pgsz_strings[i]);
 463                         printed++;
 464                 }
 465         }
 466         seq_putc(m, '\n');
 467
 468 #ifdef CONFIG_DEBUG_DCFLUSH
 469         seq_printf(m, "DCPageFlushes\t: %d\n",
 470                    atomic_read(&dcpage_flushes));
 471 #ifdef CONFIG_SMP
 472         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 473                    atomic_read(&dcpage_flushes_xcall));
 474 #endif /* CONFIG_SMP */
 475 #endif /* CONFIG_DEBUG_DCFLUSH */
 476 }
 477
 478 struct linux_prom_translation prom_trans[512] __read_mostly;
 479 unsigned int prom_trans_ents __read_mostly;
 480
 481 unsigned long kern_locked_tte_data;
 482
 483 /* The obp translations are saved based on 8k pagesize, since obp can
 484  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 485  * HI_OBP_ADDRESS range are handled in ktlb.S.
 486  */
 487 static inline int in_obp_range(unsigned long vaddr)
 488 {
 489         return (vaddr >= LOW_OBP_ADDRESS &&
 490                 vaddr < HI_OBP_ADDRESS);
 491 }
 492
 493 static int cmp_ptrans(const void *a, const void *b)
 494 {
 495         const struct linux_prom_translation *x = a, *y = b;
 496
 497         if (x->virt > y->virt)
 498                 return 1;
 499         if (x->virt < y->virt)
 500                 return -1;
 501         return 0;
 502 }
 503
 504 /* Read OBP translations property into 'prom_trans[]'.  */
 505 static void __init read_obp_translations(void)
 506 {
 507         int n, node, ents, first, last, i;
 508
 509         node = prom_finddevice("/virtual-memory");
 510         n = prom_getproplen(node, "translations");
 511         if (unlikely(n == 0 || n == -1)) {
 512                 prom_printf("prom_mappings: Couldn't get size.\n");
 513                 prom_halt();
 514         }
 515         if (unlikely(n > sizeof(prom_trans))) {
 516                 prom_printf("prom_mappings: Size %d is too big.\n", n);
 517                 prom_halt();
 518         }
 519
 520         if ((n = prom_getproperty(node, "translations",
 521                                   (char *)&prom_trans[0],
 522                                   sizeof(prom_trans))) == -1) {
 523                 prom_printf("prom_mappings: Couldn't get property.\n");
 524                 prom_halt();
 525         }
 526
 527         n = n / sizeof(struct linux_prom_translation);
 528
 529         ents = n;
 530
 531         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 532              cmp_ptrans, NULL);
 533
 534         /* Now kick out all the non-OBP entries.  */
 535         for (i = 0; i < ents; i++) {
 536                 if (in_obp_range(prom_trans[i].virt))
 537                         break;
 538         }
 539         first = i;
 540         for (; i < ents; i++) {
 541                 if (!in_obp_range(prom_trans[i].virt))
 542                         break;
 543         }
 544         last = i;
 545
 546         for (i = 0; i < (last - first); i++) {
 547                 struct linux_prom_translation *src = &prom_trans[i + first];
 548                 struct linux_prom_translation *dest = &prom_trans[i];
 549
 550                 *dest = *src;
 551         }
 552         for (; i < ents; i++) {
 553                 struct linux_prom_translation *dest = &prom_trans[i];
 554                 dest->virt = dest->size = dest->data = 0x0UL;
 555         }
 556
 557         prom_trans_ents = last - first;
 558
 559         if (tlb_type == spitfire) {
 560                 /* Clear diag TTE bits. */
 561                 for (i = 0; i < prom_trans_ents; i++)
 562                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 563         }
 564
 565         /* Force execute bit on.  */
 566         for (i = 0; i < prom_trans_ents; i++)
 567                 prom_trans[i].data |= (tlb_type == hypervisor ?
 568                                        _PAGE_EXEC_4V : _PAGE_EXEC_4U);
 569 }
 570
 571 static void __init hypervisor_tlb_lock(unsigned long vaddr,
 572                                        unsigned long pte,
 573                                        unsigned long mmu)
 574 {
 575         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
 576
 577         if (ret != 0) {
 578                 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
 579                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
 580                 prom_halt();
 581         }
 582 }
 583
 584 static unsigned long kern_large_tte(unsigned long paddr);
 585
 586 static void __init remap_kernel(void)
 587 {
 588         unsigned long phys_page, tte_vaddr, tte_data;
 589         int i, tlb_ent = sparc64_highest_locked_tlbent();
 590
 591         tte_vaddr = (unsigned long) KERNBASE;
 592         phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
 593         tte_data = kern_large_tte(phys_page);
 594
 595         kern_locked_tte_data = tte_data;
 596
 597         /* Now lock us into the TLBs via Hypervisor or OBP. */
 598         if (tlb_type == hypervisor) {
 599                 for (i = 0; i < num_kernel_image_mappings; i++) {
 600                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 601                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 602                         tte_vaddr += 0x400000;
 603                         tte_data += 0x400000;
 604                 }
 605         } else {
 606                 for (i = 0; i < num_kernel_image_mappings; i++) {
 607                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
 608                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
 609                         tte_vaddr += 0x400000;
 610                         tte_data += 0x400000;
 611                 }
 612                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
 613         }
 614         if (tlb_type == cheetah_plus) {
 615                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 616                                             CTX_CHEETAH_PLUS_NUC);
 617                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 618                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 619         }
 620 }
 621
 622
 623 static void __init inherit_prom_mappings(void)
 624 {
 625         /* Now fixup OBP's idea about where we really are mapped. */
 626         printk("Remapping the kernel... ");
 627         remap_kernel();
 628         printk("done.\n");
 629 }
 630
 631 void prom_world(int enter)
 632 {
 633         if (!enter)
 634                 set_fs(get_fs());
 635
 636         __asm__ __volatile__("flushw");
 637 }
 638
 639 void __flush_dcache_range(unsigned long start, unsigned long end)
 640 {
 641         unsigned long va;
 642
 643         if (tlb_type == spitfire) {
 644                 int n = 0;
 645
 646                 for (va = start; va < end; va += 32) {
 647                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 648                         if (++n >= 512)
 649                                 break;
 650                 }
 651         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 652                 start = __pa(start);
 653                 end = __pa(end);
 654                 for (va = start; va < end; va += 32)
 655                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 656                                              "membar #Sync"
 657                                              : /* no outputs */
 658                                              : "r" (va),
 659                                                "i" (ASI_DCACHE_INVALIDATE));
 660         }
 661 }
 662 EXPORT_SYMBOL(__flush_dcache_range);
 663
 664 /* get_new_mmu_context() uses "cache + 1".  */
 665 DEFINE_SPINLOCK(ctx_alloc_lock);
 666 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 667 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
 668 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
 669 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
 670
 671 /* Caller does TLB context flushing on local CPU if necessary.
 672  * The caller also ensures that CTX_VALID(mm->context) is false.
 673  *
 674  * We must be careful about boundary cases so that we never
 675  * let the user have CTX 0 (nucleus) or we ever use a CTX
 676  * version of zero (and thus NO_CONTEXT would not be caught
 677  * by version mis-match tests in mmu_context.h).
 678  *
 679  * Always invoked with interrupts disabled.
 680  */
 681 void get_new_mmu_context(struct mm_struct *mm)
 682 {
 683         unsigned long ctx, new_ctx;
 684         unsigned long orig_pgsz_bits;
 685         int new_version;
 686
 687         spin_lock(&ctx_alloc_lock);
 688         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 689         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 690         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 691         new_version = 0;
 692         if (new_ctx >= (1 << CTX_NR_BITS)) {
 693                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 694                 if (new_ctx >= ctx) {
 695                         int i;
 696                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
 697                                 CTX_FIRST_VERSION;
 698                         if (new_ctx == 1)
 699                                 new_ctx = CTX_FIRST_VERSION;
 700
 701                         /* Don't call memset, for 16 entries that's just
 702                          * plain silly...
 703                          */
 704                         mmu_context_bmap[0] = 3;
 705                         mmu_context_bmap[1] = 0;
 706                         mmu_context_bmap[2] = 0;
 707                         mmu_context_bmap[3] = 0;
 708                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
 709                                 mmu_context_bmap[i + 0] = 0;
 710                                 mmu_context_bmap[i + 1] = 0;
 711                                 mmu_context_bmap[i + 2] = 0;
 712                                 mmu_context_bmap[i + 3] = 0;
 713                         }
 714                         new_version = 1;
 715                         goto out;
 716                 }
 717         }
 718         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 719         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 720 out:
 721         tlb_context_cache = new_ctx;
 722         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 723         spin_unlock(&ctx_alloc_lock);
 724
 725         if (unlikely(new_version))
 726                 smp_new_mmu_context_version();
 727 }
 728
 729 static int numa_enabled = 1;
 730 static int numa_debug;
 731
 732 static int __init early_numa(char *p)
 733 {
 734         if (!p)
 735                 return 0;
 736
 737         if (strstr(p, "off"))
 738                 numa_enabled = 0;
 739
 740         if (strstr(p, "debug"))
 741                 numa_debug = 1;
 742
 743         return 0;
 744 }
 745 early_param("numa", early_numa);
 746
 747 #define numadbg(f, a...) \
 748 do {    if (numa_debug) \
 749                 printk(KERN_INFO f, ## a); \
 750 } while (0)
 751
 752 static void __init find_ramdisk(unsigned long phys_base)
 753 {
 754 #ifdef CONFIG_BLK_DEV_INITRD
 755         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 756                 unsigned long ramdisk_image;
 757
 758                 /* Older versions of the bootloader only supported a
 759                  * 32-bit physical address for the ramdisk image
 760                  * location, stored at sparc_ramdisk_image.  Newer
 761                  * SILO versions set sparc_ramdisk_image to zero and
 762                  * provide a full 64-bit physical address at
 763                  * sparc_ramdisk_image64.
 764                  */
 765                 ramdisk_image = sparc_ramdisk_image;
 766                 if (!ramdisk_image)
 767                         ramdisk_image = sparc_ramdisk_image64;
 768
 769                 /* Another bootloader quirk.  The bootloader normalizes
 770                  * the physical address to KERNBASE, so we have to
 771                  * factor that back out and add in the lowest valid
 772                  * physical page address to get the true physical address.
 773                  */
 774                 ramdisk_image -= KERNBASE;
 775                 ramdisk_image += phys_base;
 776
 777                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
 778                         ramdisk_image, sparc_ramdisk_size);
 779
 780                 initrd_start = ramdisk_image;
 781                 initrd_end = ramdisk_image + sparc_ramdisk_size;
 782
 783                 memblock_reserve(initrd_start, sparc_ramdisk_size);
 784
 785                 initrd_start += PAGE_OFFSET;
 786                 initrd_end += PAGE_OFFSET;
 787         }
 788 #endif
 789 }
 790
 791 struct node_mem_mask {
 792         unsigned long mask;
 793         unsigned long val;
 794 };
 795 static struct node_mem_mask node_masks[MAX_NUMNODES];
 796 static int num_node_masks;
 797
 798 #ifdef CONFIG_NEED_MULTIPLE_NODES
 799
 800 int numa_cpu_lookup_table[NR_CPUS];
 801 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
 802
 803 struct mdesc_mblock {
 804         u64     base;
 805         u64     size;
 806         u64     offset; /* RA-to-PA */
 807 };
 808 static struct mdesc_mblock *mblocks;
 809 static int num_mblocks;
 810
 811 static unsigned long ra_to_pa(unsigned long addr)
 812 {
 813         int i;
 814
 815         for (i = 0; i < num_mblocks; i++) {
 816                 struct mdesc_mblock *m = &mblocks[i];
 817
 818                 if (addr >= m->base &&
 819                     addr < (m->base + m->size)) {
 820                         addr += m->offset;
 821                         break;
 822                 }
 823         }
 824         return addr;
 825 }
 826
 827 static int find_node(unsigned long addr)
 828 {
 829         int i;
 830
 831         addr = ra_to_pa(addr);
 832         for (i = 0; i < num_node_masks; i++) {
 833                 struct node_mem_mask *p = &node_masks[i];
 834
 835                 if ((addr & p->mask) == p->val)
 836                         return i;
 837         }
 838         /* The following condition has been observed on LDOM guests.*/
 839         WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node"
 840                 " rule. Some physical memory will be owned by node 0.");
 841         return 0;
 842 }
 843
 844 static u64 memblock_nid_range(u64 start, u64 end, int *nid)
 845 {
 846         *nid = find_node(start);
 847         start += PAGE_SIZE;
 848         while (start < end) {
 849                 int n = find_node(start);
 850
 851                 if (n != *nid)
 852                         break;
 853                 start += PAGE_SIZE;
 854         }
 855
 856         if (start > end)
 857                 start = end;
 858
 859         return start;
 860 }
 861 #endif
 862
 863 /* This must be invoked after performing all of the necessary
 864  * memblock_set_node() calls for 'nid'.  We need to be able to get
 865  * correct data from get_pfn_range_for_nid().
 866  */
 867 static void __init allocate_node_data(int nid)
 868 {
 869         struct pglist_data *p;
 870         unsigned long start_pfn, end_pfn;
 871 #ifdef CONFIG_NEED_MULTIPLE_NODES
 872         unsigned long paddr;
 873
 874         paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
 875         if (!paddr) {
 876                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
 877                 prom_halt();
 878         }
 879         NODE_DATA(nid) = __va(paddr);
 880         memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
 881
 882         NODE_DATA(nid)->node_id = nid;
 883 #endif
 884
 885         p = NODE_DATA(nid);
 886
 887         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
 888         p->node_start_pfn = start_pfn;
 889         p->node_spanned_pages = end_pfn - start_pfn;
 890 }
 891
 892 static void init_node_masks_nonnuma(void)
 893 {
 894 #ifdef CONFIG_NEED_MULTIPLE_NODES
 895         int i;
 896 #endif
 897
 898         numadbg("Initializing tables for non-numa.\n");
 899
 900         node_masks[0].mask = node_masks[0].val = 0;
 901         num_node_masks = 1;
 902
 903 #ifdef CONFIG_NEED_MULTIPLE_NODES
 904         for (i = 0; i < NR_CPUS; i++)
 905                 numa_cpu_lookup_table[i] = 0;
 906
 907         cpumask_setall(&numa_cpumask_lookup_table[0]);
 908 #endif
 909 }
 910
 911 #ifdef CONFIG_NEED_MULTIPLE_NODES
 912 struct pglist_data *node_data[MAX_NUMNODES];
 913
 914 EXPORT_SYMBOL(numa_cpu_lookup_table);
 915 EXPORT_SYMBOL(numa_cpumask_lookup_table);
 916 EXPORT_SYMBOL(node_data);
 917
 918 struct mdesc_mlgroup {
 919         u64     node;
 920         u64     latency;
 921         u64     match;
 922         u64     mask;
 923 };
 924 static struct mdesc_mlgroup *mlgroups;
 925 static int num_mlgroups;
 926
 927 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
 928                                    u32 cfg_handle)
 929 {
 930         u64 arc;
 931
 932         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
 933                 u64 target = mdesc_arc_target(md, arc);
 934                 const u64 *val;
 935
 936                 val = mdesc_get_property(md, target,
 937                                          "cfg-handle", NULL);
 938                 if (val && *val == cfg_handle)
 939                         return 0;
 940         }
 941         return -ENODEV;
 942 }
 943
 944 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
 945                                     u32 cfg_handle)
 946 {
 947         u64 arc, candidate, best_latency = ~(u64)0;
 948
 949         candidate = MDESC_NODE_NULL;
 950         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
 951                 u64 target = mdesc_arc_target(md, arc);
 952                 const char *name = mdesc_node_name(md, target);
 953                 const u64 *val;
 954
 955                 if (strcmp(name, "pio-latency-group"))
 956                         continue;
 957
 958                 val = mdesc_get_property(md, target, "latency", NULL);
 959                 if (!val)
 960                         continue;
 961
 962                 if (*val < best_latency) {
 963                         candidate = target;
 964                         best_latency = *val;
 965                 }
 966         }
 967
 968         if (candidate == MDESC_NODE_NULL)
 969                 return -ENODEV;
 970
 971         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
 972 }
 973
 974 int of_node_to_nid(struct device_node *dp)
 975 {
 976         const struct linux_prom64_registers *regs;
 977         struct mdesc_handle *md;
 978         u32 cfg_handle;
 979         int count, nid;
 980         u64 grp;
 981
 982         /* This is the right thing to do on currently supported
 983          * SUN4U NUMA platforms as well, as the PCI controller does
 984          * not sit behind any particular memory controller.
 985          */
 986         if (!mlgroups)
 987                 return -1;
 988
 989         regs = of_get_property(dp, "reg", NULL);
 990         if (!regs)
 991                 return -1;
 992
 993         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
 994
 995         md = mdesc_grab();
 996
 997         count = 0;
 998         nid = -1;
 999         mdesc_for_each_node_by_name(md, grp, "group") {
1000                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1001                         nid = count;
1002                         break;
1003                 }
1004                 count++;
1005         }
1006
1007         mdesc_release(md);
1008
1009         return nid;
1010 }
1011
1012 static void __init add_node_ranges(void)
1013 {
1014         struct memblock_region *reg;
1015
1016         for_each_memblock(memory, reg) {
1017                 unsigned long size = reg->size;
1018                 unsigned long start, end;
1019
1020                 start = reg->base;
1021                 end = start + size;
1022                 while (start < end) {
1023                         unsigned long this_end;
1024                         int nid;
1025
1026                         this_end = memblock_nid_range(start, end, &nid);
1027
1028                         numadbg("Setting memblock NUMA node nid[%d] "
1029                                 "start[%lx] end[%lx]\n",
1030                                 nid, start, this_end);
1031
1032                         memblock_set_node(start, this_end - start,
1033                                           &memblock.memory, nid);
1034                         start = this_end;
1035                 }
1036         }
1037 }
1038
1039 static int __init grab_mlgroups(struct mdesc_handle *md)
1040 {
1041         unsigned long paddr;
1042         int count = 0;
1043         u64 node;
1044
1045         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1046                 count++;
1047         if (!count)
1048                 return -ENOENT;
1049
1050         paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1051                           SMP_CACHE_BYTES);
1052         if (!paddr)
1053                 return -ENOMEM;
1054
1055         mlgroups = __va(paddr);
1056         num_mlgroups = count;
1057
1058         count = 0;
1059         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1060                 struct mdesc_mlgroup *m = &mlgroups[count++];
1061                 const u64 *val;
1062
1063                 m->node = node;
1064
1065                 val = mdesc_get_property(md, node, "latency", NULL);
1066                 m->latency = *val;
1067                 val = mdesc_get_property(md, node, "address-match", NULL);
1068                 m->match = *val;
1069                 val = mdesc_get_property(md, node, "address-mask", NULL);
1070                 m->mask = *val;
1071
1072                 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1073                         "match[%llx] mask[%llx]\n",
1074                         count - 1, m->node, m->latency, m->match, m->mask);
1075         }
1076
1077         return 0;
1078 }
1079
1080 static int __init grab_mblocks(struct mdesc_handle *md)
1081 {
1082         unsigned long paddr;
1083         int count = 0;
1084         u64 node;
1085
1086         mdesc_for_each_node_by_name(md, node, "mblock")
1087                 count++;
1088         if (!count)
1089                 return -ENOENT;
1090
1091         paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1092                           SMP_CACHE_BYTES);
1093         if (!paddr)
1094                 return -ENOMEM;
1095
1096         mblocks = __va(paddr);
1097         num_mblocks = count;
1098
1099         count = 0;
1100         mdesc_for_each_node_by_name(md, node, "mblock") {
1101                 struct mdesc_mblock *m = &mblocks[count++];
1102                 const u64 *val;
1103
1104                 val = mdesc_get_property(md, node, "base", NULL);
1105                 m->base = *val;
1106                 val = mdesc_get_property(md, node, "size", NULL);
1107                 m->size = *val;
1108                 val = mdesc_get_property(md, node,
1109                                          "address-congruence-offset", NULL);
1110
1111                 /* The address-congruence-offset property is optional.
1112                  * Explicity zero it be identifty this.
1113                  */
1114                 if (val)
1115                         m->offset = *val;
1116                 else
1117                         m->offset = 0UL;
1118
1119                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1120                         count - 1, m->base, m->size, m->offset);
1121         }
1122
1123         return 0;
1124 }
1125
1126 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1127                                                u64 grp, cpumask_t *mask)
1128 {
1129         u64 arc;
1130
1131         cpumask_clear(mask);
1132
1133         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1134                 u64 target = mdesc_arc_target(md, arc);
1135                 const char *name = mdesc_node_name(md, target);
1136                 const u64 *id;
1137
1138                 if (strcmp(name, "cpu"))
1139                         continue;
1140                 id = mdesc_get_property(md, target, "id", NULL);
1141                 if (*id < nr_cpu_ids)
1142                         cpumask_set_cpu(*id, mask);
1143         }
1144 }
1145
1146 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1147 {
1148         int i;
1149
1150         for (i = 0; i < num_mlgroups; i++) {
1151                 struct mdesc_mlgroup *m = &mlgroups[i];
1152                 if (m->node == node)
1153                         return m;
1154         }
1155         return NULL;
1156 }
1157
1158 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1159                                       int index)
1160 {
1161         struct mdesc_mlgroup *candidate = NULL;
1162         u64 arc, best_latency = ~(u64)0;
1163         struct node_mem_mask *n;
1164
1165         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1166                 u64 target = mdesc_arc_target(md, arc);
1167                 struct mdesc_mlgroup *m = find_mlgroup(target);
1168                 if (!m)
1169                         continue;
1170                 if (m->latency < best_latency) {
1171                         candidate = m;
1172                         best_latency = m->latency;
1173                 }
1174         }
1175         if (!candidate)
1176                 return -ENOENT;
1177
1178         if (num_node_masks != index) {
1179                 printk(KERN_ERR "Inconsistent NUMA state, "
1180                        "index[%d] != num_node_masks[%d]\n",
1181                        index, num_node_masks);
1182                 return -EINVAL;
1183         }
1184
1185         n = &node_masks[num_node_masks++];
1186
1187         n->mask = candidate->mask;
1188         n->val = candidate->match;
1189
1190         numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1191                 index, n->mask, n->val, candidate->latency);
1192
1193         return 0;
1194 }
1195
1196 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1197                                          int index)
1198 {
1199         cpumask_t mask;
1200         int cpu;
1201
1202         numa_parse_mdesc_group_cpus(md, grp, &mask);
1203
1204         for_each_cpu(cpu, &mask)
1205                 numa_cpu_lookup_table[cpu] = index;
1206         cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1207
1208         if (numa_debug) {
1209                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1210                 for_each_cpu(cpu, &mask)
1211                         printk("%d ", cpu);
1212                 printk("]\n");
1213         }
1214
1215         return numa_attach_mlgroup(md, grp, index);
1216 }
1217
1218 static int __init numa_parse_mdesc(void)
1219 {
1220         struct mdesc_handle *md = mdesc_grab();
1221         int i, err, count;
1222         u64 node;
1223
1224         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1225         if (node == MDESC_NODE_NULL) {
1226                 mdesc_release(md);
1227                 return -ENOENT;
1228         }
1229
1230         err = grab_mblocks(md);
1231         if (err < 0)
1232                 goto out;
1233
1234         err = grab_mlgroups(md);
1235         if (err < 0)
1236                 goto out;
1237
1238         count = 0;
1239         mdesc_for_each_node_by_name(md, node, "group") {
1240                 err = numa_parse_mdesc_group(md, node, count);
1241                 if (err < 0)
1242                         break;
1243                 count++;
1244         }
1245
1246         add_node_ranges();
1247
1248         for (i = 0; i < num_node_masks; i++) {
1249                 allocate_node_data(i);
1250                 node_set_online(i);
1251         }
1252
1253         err = 0;
1254 out:
1255         mdesc_release(md);
1256         return err;
1257 }
1258
1259 static int __init numa_parse_jbus(void)
1260 {
1261         unsigned long cpu, index;
1262
1263         /* NUMA node id is encoded in bits 36 and higher, and there is
1264          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1265          */
1266         index = 0;
1267         for_each_present_cpu(cpu) {
1268                 numa_cpu_lookup_table[cpu] = index;
1269                 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1270                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1271                 node_masks[index].val = cpu << 36UL;
1272
1273                 index++;
1274         }
1275         num_node_masks = index;
1276
1277         add_node_ranges();
1278
1279         for (index = 0; index < num_node_masks; index++) {
1280                 allocate_node_data(index);
1281                 node_set_online(index);
1282         }
1283
1284         return 0;
1285 }
1286
1287 static int __init numa_parse_sun4u(void)
1288 {
1289         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1290                 unsigned long ver;
1291
1292                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1293                 if ((ver >> 32UL) == __JALAPENO_ID ||
1294                     (ver >> 32UL) == __SERRANO_ID)
1295                         return numa_parse_jbus();
1296         }
1297         return -1;
1298 }
1299
1300 static int __init bootmem_init_numa(void)
1301 {
1302         int err = -1;
1303
1304         numadbg("bootmem_init_numa()\n");
1305
1306         if (numa_enabled) {
1307                 if (tlb_type == hypervisor)
1308                         err = numa_parse_mdesc();
1309                 else
1310                         err = numa_parse_sun4u();
1311         }
1312         return err;
1313 }
1314
1315 #else
1316
1317 static int bootmem_init_numa(void)
1318 {
1319         return -1;
1320 }
1321
1322 #endif
1323
1324 static void __init bootmem_init_nonnuma(void)
1325 {
1326         unsigned long top_of_ram = memblock_end_of_DRAM();
1327         unsigned long total_ram = memblock_phys_mem_size();
1328
1329         numadbg("bootmem_init_nonnuma()\n");
1330
1331         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1332                top_of_ram, total_ram);
1333         printk(KERN_INFO "Memory hole size: %ldMB\n",
1334                (top_of_ram - total_ram) >> 20);
1335
1336         init_node_masks_nonnuma();
1337         memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1338         allocate_node_data(0);
1339         node_set_online(0);
1340 }
1341
1342 static unsigned long __init bootmem_init(unsigned long phys_base)
1343 {
1344         unsigned long end_pfn;
1345
1346         end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1347         max_pfn = max_low_pfn = end_pfn;
1348         min_low_pfn = (phys_base >> PAGE_SHIFT);
1349
1350         if (bootmem_init_numa() < 0)
1351                 bootmem_init_nonnuma();
1352
1353         /* Dump memblock with node info. */
1354         memblock_dump_all();
1355
1356         /* XXX cpu notifier XXX */
1357
1358         sparse_memory_present_with_active_regions(MAX_NUMNODES);
1359         sparse_init();
1360
1361         return end_pfn;
1362 }
1363
1364 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1365 static int pall_ents __initdata;
1366
1367 static unsigned long max_phys_bits = 40;
1368
1369 bool kern_addr_valid(unsigned long addr)
1370 {
1371         pgd_t *pgd;
1372         pud_t *pud;
1373         pmd_t *pmd;
1374         pte_t *pte;
1375
1376         if ((long)addr < 0L) {
1377                 unsigned long pa = __pa(addr);
1378
1379                 if ((addr >> max_phys_bits) != 0UL)
1380                         return false;
1381
1382                 return pfn_valid(pa >> PAGE_SHIFT);
1383         }
1384
1385         if (addr >= (unsigned long) KERNBASE &&
1386             addr < (unsigned long)&_end)
1387                 return true;
1388
1389         pgd = pgd_offset_k(addr);
1390         if (pgd_none(*pgd))
1391                 return 0;
1392
1393         pud = pud_offset(pgd, addr);
1394         if (pud_none(*pud))
1395                 return 0;
1396
1397         if (pud_large(*pud))
1398                 return pfn_valid(pud_pfn(*pud));
1399
1400         pmd = pmd_offset(pud, addr);
1401         if (pmd_none(*pmd))
1402                 return 0;
1403
1404         if (pmd_large(*pmd))
1405                 return pfn_valid(pmd_pfn(*pmd));
1406
1407         pte = pte_offset_kernel(pmd, addr);
1408         if (pte_none(*pte))
1409                 return 0;
1410
1411         return pfn_valid(pte_pfn(*pte));
1412 }
1413 EXPORT_SYMBOL(kern_addr_valid);
1414
1415 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1416                                               unsigned long vend,
1417                                               pud_t *pud)
1418 {
1419         const unsigned long mask16gb = (1UL << 34) - 1UL;
1420         u64 pte_val = vstart;
1421
1422         /* Each PUD is 8GB */
1423         if ((vstart & mask16gb) ||
1424             (vend - vstart <= mask16gb)) {
1425                 pte_val ^= kern_linear_pte_xor[2];
1426                 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1427
1428                 return vstart + PUD_SIZE;
1429         }
1430
1431         pte_val ^= kern_linear_pte_xor[3];
1432         pte_val |= _PAGE_PUD_HUGE;
1433
1434         vend = vstart + mask16gb + 1UL;
1435         while (vstart < vend) {
1436                 pud_val(*pud) = pte_val;
1437
1438                 pte_val += PUD_SIZE;
1439                 vstart += PUD_SIZE;
1440                 pud++;
1441         }
1442         return vstart;
1443 }
1444
1445 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1446                                    bool guard)
1447 {
1448         if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1449                 return true;
1450
1451         return false;
1452 }
1453
1454 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1455                                               unsigned long vend,
1456                                               pmd_t *pmd)
1457 {
1458         const unsigned long mask256mb = (1UL << 28) - 1UL;
1459         const unsigned long mask2gb = (1UL << 31) - 1UL;
1460         u64 pte_val = vstart;
1461
1462         /* Each PMD is 8MB */
1463         if ((vstart & mask256mb) ||
1464             (vend - vstart <= mask256mb)) {
1465                 pte_val ^= kern_linear_pte_xor[0];
1466                 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1467
1468                 return vstart + PMD_SIZE;
1469         }
1470
1471         if ((vstart & mask2gb) ||
1472             (vend - vstart <= mask2gb)) {
1473                 pte_val ^= kern_linear_pte_xor[1];
1474                 pte_val |= _PAGE_PMD_HUGE;
1475                 vend = vstart + mask256mb + 1UL;
1476         } else {
1477                 pte_val ^= kern_linear_pte_xor[2];
1478                 pte_val |= _PAGE_PMD_HUGE;
1479                 vend = vstart + mask2gb + 1UL;
1480         }
1481
1482         while (vstart < vend) {
1483                 pmd_val(*pmd) = pte_val;
1484
1485                 pte_val += PMD_SIZE;
1486                 vstart += PMD_SIZE;
1487                 pmd++;
1488         }
1489
1490         return vstart;
1491 }
1492
1493 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1494                                    bool guard)
1495 {
1496         if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1497                 return true;
1498
1499         return false;
1500 }
1501
1502 static unsigned long __ref kernel_map_range(unsigned long pstart,
1503                                             unsigned long pend, pgprot_t prot,
1504                                             bool use_huge)
1505 {
1506         unsigned long vstart = PAGE_OFFSET + pstart;
1507         unsigned long vend = PAGE_OFFSET + pend;
1508         unsigned long alloc_bytes = 0UL;
1509
1510         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1511                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1512                             vstart, vend);
1513                 prom_halt();
1514         }
1515
1516         while (vstart < vend) {
1517                 unsigned long this_end, paddr = __pa(vstart);
1518                 pgd_t *pgd = pgd_offset_k(vstart);
1519                 pud_t *pud;
1520                 pmd_t *pmd;
1521                 pte_t *pte;
1522
1523                 if (pgd_none(*pgd)) {
1524                         pud_t *new;
1525
1526                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1527                         alloc_bytes += PAGE_SIZE;
1528                         pgd_populate(&init_mm, pgd, new);
1529                 }
1530                 pud = pud_offset(pgd, vstart);
1531                 if (pud_none(*pud)) {
1532                         pmd_t *new;
1533
1534                         if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1535                                 vstart = kernel_map_hugepud(vstart, vend, pud);
1536                                 continue;
1537                         }
1538                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1539                         alloc_bytes += PAGE_SIZE;
1540                         pud_populate(&init_mm, pud, new);
1541                 }
1542
1543                 pmd = pmd_offset(pud, vstart);
1544                 if (pmd_none(*pmd)) {
1545                         pte_t *new;
1546
1547                         if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1548                                 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1549                                 continue;
1550                         }
1551                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1552                         alloc_bytes += PAGE_SIZE;
1553                         pmd_populate_kernel(&init_mm, pmd, new);
1554                 }
1555
1556                 pte = pte_offset_kernel(pmd, vstart);
1557                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1558                 if (this_end > vend)
1559                         this_end = vend;
1560
1561                 while (vstart < this_end) {
1562                         pte_val(*pte) = (paddr | pgprot_val(prot));
1563
1564                         vstart += PAGE_SIZE;
1565                         paddr += PAGE_SIZE;
1566                         pte++;
1567                 }
1568         }
1569
1570         return alloc_bytes;
1571 }
1572
1573 static void __init flush_all_kernel_tsbs(void)
1574 {
1575         int i;
1576
1577         for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1578                 struct tsb *ent = &swapper_tsb[i];
1579
1580                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1581         }
1582 #ifndef CONFIG_DEBUG_PAGEALLOC
1583         for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1584                 struct tsb *ent = &swapper_4m_tsb[i];
1585
1586                 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1587         }
1588 #endif
1589 }
1590
1591 extern unsigned int kvmap_linear_patch[1];
1592
1593 static void __init kernel_physical_mapping_init(void)
1594 {
1595         unsigned long i, mem_alloced = 0UL;
1596         bool use_huge = true;
1597
1598 #ifdef CONFIG_DEBUG_PAGEALLOC
1599         use_huge = false;
1600 #endif
1601         for (i = 0; i < pall_ents; i++) {
1602                 unsigned long phys_start, phys_end;
1603
1604                 phys_start = pall[i].phys_addr;
1605                 phys_end = phys_start + pall[i].reg_size;
1606
1607                 mem_alloced += kernel_map_range(phys_start, phys_end,
1608                                                 PAGE_KERNEL, use_huge);
1609         }
1610
1611         printk("Allocated %ld bytes for kernel page tables.\n",
1612                mem_alloced);
1613
1614         kvmap_linear_patch[0] = 0x01000000; /* nop */
1615         flushi(&kvmap_linear_patch[0]);
1616
1617         flush_all_kernel_tsbs();
1618
1619         __flush_tlb_all();
1620 }
1621
1622 #ifdef CONFIG_DEBUG_PAGEALLOC
1623 void kernel_map_pages(struct page *page, int numpages, int enable)
1624 {
1625         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1626         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1627
1628         kernel_map_range(phys_start, phys_end,
1629                          (enable ? PAGE_KERNEL : __pgprot(0)), false);
1630
1631         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1632                                PAGE_OFFSET + phys_end);
1633
1634         /* we should perform an IPI and flush all tlbs,
1635          * but that can deadlock->flush only current cpu.
1636          */
1637         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1638                                  PAGE_OFFSET + phys_end);
1639 }
1640 #endif
1641
1642 unsigned long __init find_ecache_flush_span(unsigned long size)
1643 {
1644         int i;
1645
1646         for (i = 0; i < pavail_ents; i++) {
1647                 if (pavail[i].reg_size >= size)
1648                         return pavail[i].phys_addr;
1649         }
1650
1651         return ~0UL;
1652 }
1653
1654 unsigned long PAGE_OFFSET;
1655 EXPORT_SYMBOL(PAGE_OFFSET);
1656
1657 unsigned long VMALLOC_END   = 0x0000010000000000UL;
1658 EXPORT_SYMBOL(VMALLOC_END);
1659
1660 unsigned long sparc64_va_hole_top =    0xfffff80000000000UL;
1661 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1662
1663 static void __init setup_page_offset(void)
1664 {
1665         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1666                 /* Cheetah/Panther support a full 64-bit virtual
1667                  * address, so we can use all that our page tables
1668                  * support.
1669                  */
1670                 sparc64_va_hole_top =    0xfff0000000000000UL;
1671                 sparc64_va_hole_bottom = 0x0010000000000000UL;
1672
1673                 max_phys_bits = 42;
1674         } else if (tlb_type == hypervisor) {
1675                 switch (sun4v_chip_type) {
1676                 case SUN4V_CHIP_NIAGARA1:
1677                 case SUN4V_CHIP_NIAGARA2:
1678                         /* T1 and T2 support 48-bit virtual addresses.  */
1679                         sparc64_va_hole_top =    0xffff800000000000UL;
1680                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1681
1682                         max_phys_bits = 39;
1683                         break;
1684                 case SUN4V_CHIP_NIAGARA3:
1685                         /* T3 supports 48-bit virtual addresses.  */
1686                         sparc64_va_hole_top =    0xffff800000000000UL;
1687                         sparc64_va_hole_bottom = 0x0000800000000000UL;
1688
1689                         max_phys_bits = 43;
1690                         break;
1691                 case SUN4V_CHIP_NIAGARA4:
1692                 case SUN4V_CHIP_NIAGARA5:
1693                 case SUN4V_CHIP_SPARC64X:
1694                 case SUN4V_CHIP_SPARC_M6:
1695                         /* T4 and later support 52-bit virtual addresses.  */
1696                         sparc64_va_hole_top =    0xfff8000000000000UL;
1697                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1698                         max_phys_bits = 47;
1699                         break;
1700                 case SUN4V_CHIP_SPARC_M7:
1701                 default:
1702                         /* M7 and later support 52-bit virtual addresses.  */
1703                         sparc64_va_hole_top =    0xfff8000000000000UL;
1704                         sparc64_va_hole_bottom = 0x0008000000000000UL;
1705                         max_phys_bits = 49;
1706                         break;
1707                 }
1708         }
1709
1710         if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
1711                 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1712                             max_phys_bits);
1713                 prom_halt();
1714         }
1715
1716         PAGE_OFFSET = sparc64_va_hole_top;
1717         VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
1718                        (sparc64_va_hole_bottom >> 2));
1719
1720         pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1721                 PAGE_OFFSET, max_phys_bits);
1722         pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
1723                 VMALLOC_START, VMALLOC_END);
1724         pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
1725                 VMEMMAP_BASE, VMEMMAP_BASE << 1);
1726 }
1727
1728 static void __init tsb_phys_patch(void)
1729 {
1730         struct tsb_ldquad_phys_patch_entry *pquad;
1731         struct tsb_phys_patch_entry *p;
1732
1733         pquad = &__tsb_ldquad_phys_patch;
1734         while (pquad < &__tsb_ldquad_phys_patch_end) {
1735                 unsigned long addr = pquad->addr;
1736
1737                 if (tlb_type == hypervisor)
1738                         *(unsigned int *) addr = pquad->sun4v_insn;
1739                 else
1740                         *(unsigned int *) addr = pquad->sun4u_insn;
1741                 wmb();
1742                 __asm__ __volatile__("flush     %0"
1743                                      : /* no outputs */
1744                                      : "r" (addr));
1745
1746                 pquad++;
1747         }
1748
1749         p = &__tsb_phys_patch;
1750         while (p < &__tsb_phys_patch_end) {
1751                 unsigned long addr = p->addr;
1752
1753                 *(unsigned int *) addr = p->insn;
1754                 wmb();
1755                 __asm__ __volatile__("flush     %0"
1756                                      : /* no outputs */
1757                                      : "r" (addr));
1758
1759                 p++;
1760         }
1761 }
1762
1763 /* Don't mark as init, we give this to the Hypervisor.  */
1764 #ifndef CONFIG_DEBUG_PAGEALLOC
1765 #define NUM_KTSB_DESCR  2
1766 #else
1767 #define NUM_KTSB_DESCR  1
1768 #endif
1769 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1770
1771 /* The swapper TSBs are loaded with a base sequence of:
1772  *
1773  *      sethi   %uhi(SYMBOL), REG1
1774  *      sethi   %hi(SYMBOL), REG2
1775  *      or      REG1, %ulo(SYMBOL), REG1
1776  *      or      REG2, %lo(SYMBOL), REG2
1777  *      sllx    REG1, 32, REG1
1778  *      or      REG1, REG2, REG1
1779  *
1780  * When we use physical addressing for the TSB accesses, we patch the
1781  * first four instructions in the above sequence.
1782  */
1783
1784 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1785 {
1786         unsigned long high_bits, low_bits;
1787
1788         high_bits = (pa >> 32) & 0xffffffff;
1789         low_bits = (pa >> 0) & 0xffffffff;
1790
1791         while (start < end) {
1792                 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1793
1794                 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
1795                 __asm__ __volatile__("flush     %0" : : "r" (ia));
1796
1797                 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
1798                 __asm__ __volatile__("flush     %0" : : "r" (ia + 1));
1799
1800                 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
1801                 __asm__ __volatile__("flush     %0" : : "r" (ia + 2));
1802
1803                 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
1804                 __asm__ __volatile__("flush     %0" : : "r" (ia + 3));
1805
1806                 start++;
1807         }
1808 }
1809
1810 static void ktsb_phys_patch(void)
1811 {
1812         extern unsigned int __swapper_tsb_phys_patch;
1813         extern unsigned int __swapper_tsb_phys_patch_end;
1814         unsigned long ktsb_pa;
1815
1816         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1817         patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1818                             &__swapper_tsb_phys_patch_end, ktsb_pa);
1819 #ifndef CONFIG_DEBUG_PAGEALLOC
1820         {
1821         extern unsigned int __swapper_4m_tsb_phys_patch;
1822         extern unsigned int __swapper_4m_tsb_phys_patch_end;
1823         ktsb_pa = (kern_base +
1824                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1825         patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1826                             &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1827         }
1828 #endif
1829 }
1830
1831 static void __init sun4v_ktsb_init(void)
1832 {
1833         unsigned long ktsb_pa;
1834
1835         /* First KTSB for PAGE_SIZE mappings.  */
1836         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1837
1838         switch (PAGE_SIZE) {
1839         case 8 * 1024:
1840         default:
1841                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1842                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1843                 break;
1844
1845         case 64 * 1024:
1846                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1847                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1848                 break;
1849
1850         case 512 * 1024:
1851                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1852                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1853                 break;
1854
1855         case 4 * 1024 * 1024:
1856                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1857                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1858                 break;
1859         }
1860
1861         ktsb_descr[0].assoc = 1;
1862         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1863         ktsb_descr[0].ctx_idx = 0;
1864         ktsb_descr[0].tsb_base = ktsb_pa;
1865         ktsb_descr[0].resv = 0;
1866
1867 #ifndef CONFIG_DEBUG_PAGEALLOC
1868         /* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
1869         ktsb_pa = (kern_base +
1870                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1871
1872         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1873         ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1874                                     HV_PGSZ_MASK_256MB |
1875                                     HV_PGSZ_MASK_2GB |
1876                                     HV_PGSZ_MASK_16GB) &
1877                                    cpu_pgsz_mask);
1878         ktsb_descr[1].assoc = 1;
1879         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1880         ktsb_descr[1].ctx_idx = 0;
1881         ktsb_descr[1].tsb_base = ktsb_pa;
1882         ktsb_descr[1].resv = 0;
1883 #endif
1884 }
1885
1886 void sun4v_ktsb_register(void)
1887 {
1888         unsigned long pa, ret;
1889
1890         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1891
1892         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1893         if (ret != 0) {
1894                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1895                             "errors with %lx\n", pa, ret);
1896                 prom_halt();
1897         }
1898 }
1899
1900 static void __init sun4u_linear_pte_xor_finalize(void)
1901 {
1902 #ifndef CONFIG_DEBUG_PAGEALLOC
1903         /* This is where we would add Panther support for
1904          * 32MB and 256MB pages.
1905          */
1906 #endif
1907 }
1908
1909 static void __init sun4v_linear_pte_xor_finalize(void)
1910 {
1911 #ifndef CONFIG_DEBUG_PAGEALLOC
1912         if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1913                 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1914                         PAGE_OFFSET;
1915                 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1916                                            _PAGE_P_4V | _PAGE_W_4V);
1917         } else {
1918                 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1919         }
1920
1921         if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1922                 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1923                         PAGE_OFFSET;
1924                 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1925                                            _PAGE_P_4V | _PAGE_W_4V);
1926         } else {
1927                 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
1928         }
1929
1930         if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
1931                 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1932                         PAGE_OFFSET;
1933                 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1934                                            _PAGE_P_4V | _PAGE_W_4V);
1935         } else {
1936                 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
1937         }
1938 #endif
1939 }
1940
1941 /* paging_init() sets up the page tables */
1942
1943 static unsigned long last_valid_pfn;
1944
1945 static void sun4u_pgprot_init(void);
1946 static void sun4v_pgprot_init(void);
1947
1948 void __init paging_init(void)
1949 {
1950         unsigned long end_pfn, shift, phys_base;
1951         unsigned long real_end, i;
1952         int node;
1953
1954         setup_page_offset();
1955
1956         /* These build time checkes make sure that the dcache_dirty_cpu()
1957          * page->flags usage will work.
1958          *
1959          * When a page gets marked as dcache-dirty, we store the
1960          * cpu number starting at bit 32 in the page->flags.  Also,
1961          * functions like clear_dcache_dirty_cpu use the cpu mask
1962          * in 13-bit signed-immediate instruction fields.
1963          */
1964
1965         /*
1966          * Page flags must not reach into upper 32 bits that are used
1967          * for the cpu number
1968          */
1969         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1970
1971         /*
1972          * The bit fields placed in the high range must not reach below
1973          * the 32 bit boundary. Otherwise we cannot place the cpu field
1974          * at the 32 bit boundary.
1975          */
1976         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1977                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1978
1979         BUILD_BUG_ON(NR_CPUS > 4096);
1980
1981         kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
1982         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1983
1984         /* Invalidate both kernel TSBs.  */
1985         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1986 #ifndef CONFIG_DEBUG_PAGEALLOC
1987         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1988 #endif
1989
1990         if (tlb_type == hypervisor)
1991                 sun4v_pgprot_init();
1992         else
1993                 sun4u_pgprot_init();
1994
1995         if (tlb_type == cheetah_plus ||
1996             tlb_type == hypervisor) {
1997                 tsb_phys_patch();
1998                 ktsb_phys_patch();
1999         }
2000
2001         if (tlb_type == hypervisor)
2002                 sun4v_patch_tlb_handlers();
2003
2004         /* Find available physical memory...
2005          *
2006          * Read it twice in order to work around a bug in openfirmware.
2007          * The call to grab this table itself can cause openfirmware to
2008          * allocate memory, which in turn can take away some space from
2009          * the list of available memory.  Reading it twice makes sure
2010          * we really do get the final value.
2011          */
2012         read_obp_translations();
2013         read_obp_memory("reg", &pall[0], &pall_ents);
2014         read_obp_memory("available", &pavail[0], &pavail_ents);
2015         read_obp_memory("available", &pavail[0], &pavail_ents);
2016
2017         phys_base = 0xffffffffffffffffUL;
2018         for (i = 0; i < pavail_ents; i++) {
2019                 phys_base = min(phys_base, pavail[i].phys_addr);
2020                 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2021         }
2022
2023         memblock_reserve(kern_base, kern_size);
2024
2025         find_ramdisk(phys_base);
2026
2027         memblock_enforce_memory_limit(cmdline_memory_size);
2028
2029         memblock_allow_resize();
2030         memblock_dump_all();
2031
2032         set_bit(0, mmu_context_bmap);
2033
2034         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2035
2036         real_end = (unsigned long)_end;
2037         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2038         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2039                num_kernel_image_mappings);
2040
2041         /* Set kernel pgd to upper alias so physical page computations
2042          * work.
2043          */
2044         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2045
2046         memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2047
2048         inherit_prom_mappings();
2049
2050         /* Ok, we can use our TLB miss and window trap handlers safely.  */
2051         setup_tba();
2052
2053         __flush_tlb_all();
2054
2055         prom_build_devicetree();
2056         of_populate_present_mask();
2057 #ifndef CONFIG_SMP
2058         of_fill_in_cpu_data();
2059 #endif
2060
2061         if (tlb_type == hypervisor) {
2062                 sun4v_mdesc_init();
2063                 mdesc_populate_present_mask(cpu_all_mask);
2064 #ifndef CONFIG_SMP
2065                 mdesc_fill_in_cpu_data(cpu_all_mask);
2066 #endif
2067                 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2068
2069                 sun4v_linear_pte_xor_finalize();
2070
2071                 sun4v_ktsb_init();
2072                 sun4v_ktsb_register();
2073         } else {
2074                 unsigned long impl, ver;
2075
2076                 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2077                                  HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2078
2079                 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2080                 impl = ((ver >> 32) & 0xffff);
2081                 if (impl == PANTHER_IMPL)
2082                         cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2083                                           HV_PGSZ_MASK_256MB);
2084
2085                 sun4u_linear_pte_xor_finalize();
2086         }
2087
2088         /* Flush the TLBs and the 4M TSB so that the updated linear
2089          * pte XOR settings are realized for all mappings.
2090          */
2091         __flush_tlb_all();
2092 #ifndef CONFIG_DEBUG_PAGEALLOC
2093         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2094 #endif
2095         __flush_tlb_all();
2096
2097         /* Setup bootmem... */
2098         last_valid_pfn = end_pfn = bootmem_init(phys_base);
2099
2100         /* Once the OF device tree and MDESC have been setup, we know
2101          * the list of possible cpus.  Therefore we can allocate the
2102          * IRQ stacks.
2103          */
2104         for_each_possible_cpu(i) {
2105                 node = cpu_to_node(i);
2106
2107                 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2108                                                         THREAD_SIZE,
2109                                                         THREAD_SIZE, 0);
2110                 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2111                                                         THREAD_SIZE,
2112                                                         THREAD_SIZE, 0);
2113         }
2114
2115         kernel_physical_mapping_init();
2116
2117         {
2118                 unsigned long max_zone_pfns[MAX_NR_ZONES];
2119
2120                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2121
2122                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2123
2124                 free_area_init_nodes(max_zone_pfns);
2125         }
2126
2127         printk("Booting Linux...\n");
2128 }
2129
2130 int page_in_phys_avail(unsigned long paddr)
2131 {
2132         int i;
2133
2134         paddr &= PAGE_MASK;
2135
2136         for (i = 0; i < pavail_ents; i++) {
2137                 unsigned long start, end;
2138
2139                 start = pavail[i].phys_addr;
2140                 end = start + pavail[i].reg_size;
2141
2142                 if (paddr >= start && paddr < end)
2143                         return 1;
2144         }
2145         if (paddr >= kern_base && paddr < (kern_base + kern_size))
2146                 return 1;
2147 #ifdef CONFIG_BLK_DEV_INITRD
2148         if (paddr >= __pa(initrd_start) &&
2149             paddr < __pa(PAGE_ALIGN(initrd_end)))
2150                 return 1;
2151 #endif
2152
2153         return 0;
2154 }
2155
2156 static void __init register_page_bootmem_info(void)
2157 {
2158 #ifdef CONFIG_NEED_MULTIPLE_NODES
2159         int i;
2160
2161         for_each_online_node(i)
2162                 if (NODE_DATA(i)->node_spanned_pages)
2163                         register_page_bootmem_info_node(NODE_DATA(i));
2164 #endif
2165 }
2166 void __init mem_init(void)
2167 {
2168         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2169
2170         register_page_bootmem_info();
2171         free_all_bootmem();
2172
2173         /*
2174          * Set up the zero page, mark it reserved, so that page count
2175          * is not manipulated when freeing the page from user ptes.
2176          */
2177         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2178         if (mem_map_zero == NULL) {
2179                 prom_printf("paging_init: Cannot alloc zero page.\n");
2180                 prom_halt();
2181         }
2182         mark_page_reserved(mem_map_zero);
2183
2184         mem_init_print_info(NULL);
2185
2186         if (tlb_type == cheetah || tlb_type == cheetah_plus)
2187                 cheetah_ecache_flush_init();
2188 }
2189
2190 void free_initmem(void)
2191 {
2192         unsigned long addr, initend;
2193         int do_free = 1;
2194
2195         /* If the physical memory maps were trimmed by kernel command
2196          * line options, don't even try freeing this initmem stuff up.
2197          * The kernel image could have been in the trimmed out region
2198          * and if so the freeing below will free invalid page structs.
2199          */
2200         if (cmdline_memory_size)
2201                 do_free = 0;
2202
2203         /*
2204          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2205          */
2206         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2207         initend = (unsigned long)(__init_end) & PAGE_MASK;
2208         for (; addr < initend; addr += PAGE_SIZE) {
2209                 unsigned long page;
2210
2211                 page = (addr +
2212                         ((unsigned long) __va(kern_base)) -
2213                         ((unsigned long) KERNBASE));
2214                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2215
2216                 if (do_free)
2217                         free_reserved_page(virt_to_page(page));
2218         }
2219 }
2220
2221 #ifdef CONFIG_BLK_DEV_INITRD
2222 void free_initrd_mem(unsigned long start, unsigned long end)
2223 {
2224         free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2225                            "initrd");
2226 }
2227 #endif
2228
2229 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2230 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2231 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2232 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2233 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2234 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2235
2236 pgprot_t PAGE_KERNEL __read_mostly;
2237 EXPORT_SYMBOL(PAGE_KERNEL);
2238
2239 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2240 pgprot_t PAGE_COPY __read_mostly;
2241
2242 pgprot_t PAGE_SHARED __read_mostly;
2243 EXPORT_SYMBOL(PAGE_SHARED);
2244
2245 unsigned long pg_iobits __read_mostly;
2246
2247 unsigned long _PAGE_IE __read_mostly;
2248 EXPORT_SYMBOL(_PAGE_IE);
2249
2250 unsigned long _PAGE_E __read_mostly;
2251 EXPORT_SYMBOL(_PAGE_E);
2252
2253 unsigned long _PAGE_CACHE __read_mostly;
2254 EXPORT_SYMBOL(_PAGE_CACHE);
2255
2256 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2257 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2258                                int node)
2259 {
2260         unsigned long pte_base;
2261
2262         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2263                     _PAGE_CP_4U | _PAGE_CV_4U |
2264                     _PAGE_P_4U | _PAGE_W_4U);
2265         if (tlb_type == hypervisor)
2266                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2267                             _PAGE_CP_4V | _PAGE_CV_4V |
2268                             _PAGE_P_4V | _PAGE_W_4V);
2269
2270         pte_base |= _PAGE_PMD_HUGE;
2271
2272         vstart = vstart & PMD_MASK;
2273         vend = ALIGN(vend, PMD_SIZE);
2274         for (; vstart < vend; vstart += PMD_SIZE) {
2275                 pgd_t *pgd = pgd_offset_k(vstart);
2276                 unsigned long pte;
2277                 pud_t *pud;
2278                 pmd_t *pmd;
2279
2280                 if (pgd_none(*pgd)) {
2281                         pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2282
2283                         if (!new)
2284                                 return -ENOMEM;
2285                         pgd_populate(&init_mm, pgd, new);
2286                 }
2287
2288                 pud = pud_offset(pgd, vstart);
2289                 if (pud_none(*pud)) {
2290                         pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2291
2292                         if (!new)
2293                                 return -ENOMEM;
2294                         pud_populate(&init_mm, pud, new);
2295                 }
2296
2297                 pmd = pmd_offset(pud, vstart);
2298
2299                 pte = pmd_val(*pmd);
2300                 if (!(pte & _PAGE_VALID)) {
2301                         void *block = vmemmap_alloc_block(PMD_SIZE, node);
2302
2303                         if (!block)
2304                                 return -ENOMEM;
2305
2306                         pmd_val(*pmd) = pte_base | __pa(block);
2307                 }
2308         }
2309
2310         return 0;
2311 }
2312
2313 void vmemmap_free(unsigned long start, unsigned long end)
2314 {
2315 }
2316 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2317
2318 static void prot_init_common(unsigned long page_none,
2319                              unsigned long page_shared,
2320                              unsigned long page_copy,
2321                              unsigned long page_readonly,
2322                              unsigned long page_exec_bit)
2323 {
2324         PAGE_COPY = __pgprot(page_copy);
2325         PAGE_SHARED = __pgprot(page_shared);
2326
2327         protection_map[0x0] = __pgprot(page_none);
2328         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2329         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2330         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2331         protection_map[0x4] = __pgprot(page_readonly);
2332         protection_map[0x5] = __pgprot(page_readonly);
2333         protection_map[0x6] = __pgprot(page_copy);
2334         protection_map[0x7] = __pgprot(page_copy);
2335         protection_map[0x8] = __pgprot(page_none);
2336         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2337         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2338         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2339         protection_map[0xc] = __pgprot(page_readonly);
2340         protection_map[0xd] = __pgprot(page_readonly);
2341         protection_map[0xe] = __pgprot(page_shared);
2342         protection_map[0xf] = __pgprot(page_shared);
2343 }
2344
2345 static void __init sun4u_pgprot_init(void)
2346 {
2347         unsigned long page_none, page_shared, page_copy, page_readonly;
2348         unsigned long page_exec_bit;
2349         int i;
2350
2351         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2352                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2353                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2354                                 _PAGE_EXEC_4U);
2355         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2356                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2357                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2358                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2359
2360         _PAGE_IE = _PAGE_IE_4U;
2361         _PAGE_E = _PAGE_E_4U;
2362         _PAGE_CACHE = _PAGE_CACHE_4U;
2363
2364         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2365                      __ACCESS_BITS_4U | _PAGE_E_4U);
2366
2367 #ifdef CONFIG_DEBUG_PAGEALLOC
2368         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2369 #else
2370         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2371                 PAGE_OFFSET;
2372 #endif
2373         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2374                                    _PAGE_P_4U | _PAGE_W_4U);
2375
2376         for (i = 1; i < 4; i++)
2377                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2378
2379         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2380                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2381                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2382
2383
2384         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2385         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2386                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2387         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2388                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2389         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2390                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2391
2392         page_exec_bit = _PAGE_EXEC_4U;
2393
2394         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2395                          page_exec_bit);
2396 }
2397
2398 static void __init sun4v_pgprot_init(void)
2399 {
2400         unsigned long page_none, page_shared, page_copy, page_readonly;
2401         unsigned long page_exec_bit;
2402         int i;
2403
2404         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2405                                 _PAGE_CACHE_4V | _PAGE_P_4V |
2406                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2407                                 _PAGE_EXEC_4V);
2408         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2409
2410         _PAGE_IE = _PAGE_IE_4V;
2411         _PAGE_E = _PAGE_E_4V;
2412         _PAGE_CACHE = _PAGE_CACHE_4V;
2413
2414 #ifdef CONFIG_DEBUG_PAGEALLOC
2415         kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2416 #else
2417         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2418                 PAGE_OFFSET;
2419 #endif
2420         kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2421                                    _PAGE_P_4V | _PAGE_W_4V);
2422
2423         for (i = 1; i < 4; i++)
2424                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2425
2426         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2427                      __ACCESS_BITS_4V | _PAGE_E_4V);
2428
2429         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2430                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2431                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2432                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2433
2434         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2435         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2436                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2437         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2438                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2439         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2440                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2441
2442         page_exec_bit = _PAGE_EXEC_4V;
2443
2444         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2445                          page_exec_bit);
2446 }
2447
2448 unsigned long pte_sz_bits(unsigned long sz)
2449 {
2450         if (tlb_type == hypervisor) {
2451                 switch (sz) {
2452                 case 8 * 1024:
2453                 default:
2454                         return _PAGE_SZ8K_4V;
2455                 case 64 * 1024:
2456                         return _PAGE_SZ64K_4V;
2457                 case 512 * 1024:
2458                         return _PAGE_SZ512K_4V;
2459                 case 4 * 1024 * 1024:
2460                         return _PAGE_SZ4MB_4V;
2461                 }
2462         } else {
2463                 switch (sz) {
2464                 case 8 * 1024:
2465                 default:
2466                         return _PAGE_SZ8K_4U;
2467                 case 64 * 1024:
2468                         return _PAGE_SZ64K_4U;
2469                 case 512 * 1024:
2470                         return _PAGE_SZ512K_4U;
2471                 case 4 * 1024 * 1024:
2472                         return _PAGE_SZ4MB_4U;
2473                 }
2474         }
2475 }
2476
2477 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2478 {
2479         pte_t pte;
2480
2481         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2482         pte_val(pte) |= (((unsigned long)space) << 32);
2483         pte_val(pte) |= pte_sz_bits(page_size);
2484
2485         return pte;
2486 }
2487
2488 static unsigned long kern_large_tte(unsigned long paddr)
2489 {
2490         unsigned long val;
2491
2492         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2493                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2494                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2495         if (tlb_type == hypervisor)
2496                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2497                        _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2498                        _PAGE_EXEC_4V | _PAGE_W_4V);
2499
2500         return val | paddr;
2501 }
2502
2503 /* If not locked, zap it. */
2504 void __flush_tlb_all(void)
2505 {
2506         unsigned long pstate;
2507         int i;
2508
2509         __asm__ __volatile__("flushw\n\t"
2510                              "rdpr      %%pstate, %0\n\t"
2511                              "wrpr      %0, %1, %%pstate"
2512                              : "=r" (pstate)
2513                              : "i" (PSTATE_IE));
2514         if (tlb_type == hypervisor) {
2515                 sun4v_mmu_demap_all();
2516         } else if (tlb_type == spitfire) {
2517                 for (i = 0; i < 64; i++) {
2518                         /* Spitfire Errata #32 workaround */
2519                         /* NOTE: Always runs on spitfire, so no
2520                          *       cheetah+ page size encodings.
2521                          */
2522                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2523                                              "flush     %%g6"
2524                                              : /* No outputs */
2525                                              : "r" (0),
2526                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2527
2528                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2529                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2530                                                      "membar #Sync"
2531                                                      : /* no outputs */
2532                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2533                                 spitfire_put_dtlb_data(i, 0x0UL);
2534                         }
2535
2536                         /* Spitfire Errata #32 workaround */
2537                         /* NOTE: Always runs on spitfire, so no
2538                          *       cheetah+ page size encodings.
2539                          */
2540                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2541                                              "flush     %%g6"
2542                                              : /* No outputs */
2543                                              : "r" (0),
2544                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2545
2546                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2547                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2548                                                      "membar #Sync"
2549                                                      : /* no outputs */
2550                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2551                                 spitfire_put_itlb_data(i, 0x0UL);
2552                         }
2553                 }
2554         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2555                 cheetah_flush_dtlb_all();
2556                 cheetah_flush_itlb_all();
2557         }
2558         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2559                              : : "r" (pstate));
2560 }
2561
2562 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2563                             unsigned long address)
2564 {
2565         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2566                                        __GFP_REPEAT | __GFP_ZERO);
2567         pte_t *pte = NULL;
2568
2569         if (page)
2570                 pte = (pte_t *) page_address(page);
2571
2572         return pte;
2573 }
2574
2575 pgtable_t pte_alloc_one(struct mm_struct *mm,
2576                         unsigned long address)
2577 {
2578         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2579                                        __GFP_REPEAT | __GFP_ZERO);
2580         if (!page)
2581                 return NULL;
2582         if (!pgtable_page_ctor(page)) {
2583                 free_hot_cold_page(page, 0);
2584                 return NULL;
2585         }
2586         return (pte_t *) page_address(page);
2587 }
2588
2589 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2590 {
2591         free_page((unsigned long)pte);
2592 }
2593
2594 static void __pte_free(pgtable_t pte)
2595 {
2596         struct page *page = virt_to_page(pte);
2597
2598         pgtable_page_dtor(page);
2599         __free_page(page);
2600 }
2601
2602 void pte_free(struct mm_struct *mm, pgtable_t pte)
2603 {
2604         __pte_free(pte);
2605 }
2606
2607 void pgtable_free(void *table, bool is_page)
2608 {
2609         if (is_page)
2610                 __pte_free(table);
2611         else
2612                 kmem_cache_free(pgtable_cache, table);
2613 }
2614
2615 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2616 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2617                           pmd_t *pmd)
2618 {
2619         unsigned long pte, flags;
2620         struct mm_struct *mm;
2621         pmd_t entry = *pmd;
2622
2623         if (!pmd_large(entry) || !pmd_young(entry))
2624                 return;
2625
2626         pte = pmd_val(entry);
2627
2628         /* Don't insert a non-valid PMD into the TSB, we'll deadlock.  */
2629         if (!(pte & _PAGE_VALID))
2630                 return;
2631
2632         /* We are fabricating 8MB pages using 4MB real hw pages.  */
2633         pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2634
2635         mm = vma->vm_mm;
2636
2637         spin_lock_irqsave(&mm->context.lock, flags);
2638
2639         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2640                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2641                                         addr, pte);
2642
2643         spin_unlock_irqrestore(&mm->context.lock, flags);
2644 }
2645 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2646
2647 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2648 static void context_reload(void *__data)
2649 {
2650         struct mm_struct *mm = __data;
2651
2652         if (mm == current->mm)
2653                 load_secondary_context(mm);
2654 }
2655
2656 void hugetlb_setup(struct pt_regs *regs)
2657 {
2658         struct mm_struct *mm = current->mm;
2659         struct tsb_config *tp;
2660
2661         if (in_atomic() || !mm) {
2662                 const struct exception_table_entry *entry;
2663
2664                 entry = search_exception_tables(regs->tpc);
2665                 if (entry) {
2666                         regs->tpc = entry->fixup;
2667                         regs->tnpc = regs->tpc + 4;
2668                         return;
2669                 }
2670                 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2671                 die_if_kernel("HugeTSB in atomic", regs);
2672         }
2673
2674         tp = &mm->context.tsb_block[MM_TSB_HUGE];
2675         if (likely(tp->tsb == NULL))
2676                 tsb_grow(mm, MM_TSB_HUGE, 0);
2677
2678         tsb_context_switch(mm);
2679         smp_tsb_sync(mm);
2680
2681         /* On UltraSPARC-III+ and later, configure the second half of
2682          * the Data-TLB for huge pages.
2683          */
2684         if (tlb_type == cheetah_plus) {
2685                 unsigned long ctx;
2686
2687                 spin_lock(&ctx_alloc_lock);
2688                 ctx = mm->context.sparc64_ctx_val;
2689                 ctx &= ~CTX_PGSZ_MASK;
2690                 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2691                 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2692
2693                 if (ctx != mm->context.sparc64_ctx_val) {
2694                         /* When changing the page size fields, we
2695                          * must perform a context flush so that no
2696                          * stale entries match.  This flush must
2697                          * occur with the original context register
2698                          * settings.
2699                          */
2700                         do_flush_tlb_mm(mm);
2701
2702                         /* Reload the context register of all processors
2703                          * also executing in this address space.
2704                          */
2705                         mm->context.sparc64_ctx_val = ctx;
2706                         on_each_cpu(context_reload, mm, 0);
2707                 }
2708                 spin_unlock(&ctx_alloc_lock);
2709         }
2710 }
2711 #endif
2712
2713 #ifdef CONFIG_SMP
2714 #define do_flush_tlb_kernel_range       smp_flush_tlb_kernel_range
2715 #else
2716 #define do_flush_tlb_kernel_range       __flush_tlb_kernel_range
2717 #endif
2718
2719 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
2720 {
2721         if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
2722                 if (start < LOW_OBP_ADDRESS) {
2723                         flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
2724                         do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
2725                 }
2726                 if (end > HI_OBP_ADDRESS) {
2727                         flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
2728                         do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
2729                 }
2730         } else {
2731                 flush_tsb_kernel_range(start, end);
2732                 do_flush_tlb_kernel_range(start, end);
2733         }
2734 }