arch/sparc/kernel/perf_event.c

   1 /* Performance event support for sparc64.
   2  *
   3  * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net>
   4  *
   5  * This code is based almost entirely upon the x86 perf event
   6  * code, which is:
   7  *
   8  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   9  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
  10  *  Copyright (C) 2009 Jaswinder Singh Rajput
  11  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
  12  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/kprobes.h>
  17 #include <linux/ftrace.h>
  18 #include <linux/kernel.h>
  19 #include <linux/kdebug.h>
  20 #include <linux/mutex.h>
  21
  22 #include <asm/stacktrace.h>
  23 #include <asm/cpudata.h>
  24 #include <asm/uaccess.h>
  25 #include <asm/atomic.h>
  26 #include <asm/nmi.h>
  27 #include <asm/pcr.h>
  28
  29 #include "kernel.h"
  30 #include "kstack.h"
  31
  32 /* Sparc64 chips have two performance counters, 32-bits each, with
  33  * overflow interrupts generated on transition from 0xffffffff to 0.
  34  * The counters are accessed in one go using a 64-bit register.
  35  *
  36  * Both counters are controlled using a single control register.  The
  37  * only way to stop all sampling is to clear all of the context (user,
  38  * supervisor, hypervisor) sampling enable bits.  But these bits apply
  39  * to both counters, thus the two counters can't be enabled/disabled
  40  * individually.
  41  *
  42  * The control register has two event fields, one for each of the two
  43  * counters.  It's thus nearly impossible to have one counter going
  44  * while keeping the other one stopped.  Therefore it is possible to
  45  * get overflow interrupts for counters not currently "in use" and
  46  * that condition must be checked in the overflow interrupt handler.
  47  *
  48  * So we use a hack, in that we program inactive counters with the
  49  * "sw_count0" and "sw_count1" events.  These count how many times
  50  * the instruction "sethi %hi(0xfc000), %g0" is executed.  It's an
  51  * unusual way to encode a NOP and therefore will not trigger in
  52  * normal code.
  53  */
  54
  55 #define MAX_HWEVENTS                    2
  56 #define MAX_PERIOD                      ((1UL << 32) - 1)
  57
  58 #define PIC_UPPER_INDEX                 0
  59 #define PIC_LOWER_INDEX                 1
  60 #define PIC_NO_INDEX                    -1
  61
  62 struct cpu_hw_events {
  63         /* Number of events currently scheduled onto this cpu.
  64          * This tells how many entries in the arrays below
  65          * are valid.
  66          */
  67         int                     n_events;
  68
  69         /* Number of new events added since the last hw_perf_disable().
  70          * This works because the perf event layer always adds new
  71          * events inside of a perf_{disable,enable}() sequence.
  72          */
  73         int                     n_added;
  74
  75         /* Array of events current scheduled on this cpu.  */
  76         struct perf_event       *event[MAX_HWEVENTS];
  77
  78         /* Array of encoded longs, specifying the %pcr register
  79          * encoding and the mask of PIC counters this even can
  80          * be scheduled on.  See perf_event_encode() et al.
  81          */
  82         unsigned long           events[MAX_HWEVENTS];
  83
  84         /* The current counter index assigned to an event.  When the
  85          * event hasn't been programmed into the cpu yet, this will
  86          * hold PIC_NO_INDEX.  The event->hw.idx value tells us where
  87          * we ought to schedule the event.
  88          */
  89         int                     current_idx[MAX_HWEVENTS];
  90
  91         /* Software copy of %pcr register on this cpu.  */
  92         u64                     pcr;
  93
  94         /* Enabled/disable state.  */
  95         int                     enabled;
  96
  97         unsigned int            group_flag;
  98 };
  99 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
 100
 101 /* An event map describes the characteristics of a performance
 102  * counter event.  In particular it gives the encoding as well as
 103  * a mask telling which counters the event can be measured on.
 104  */
 105 struct perf_event_map {
 106         u16     encoding;
 107         u8      pic_mask;
 108 #define PIC_NONE        0x00
 109 #define PIC_UPPER       0x01
 110 #define PIC_LOWER       0x02
 111 };
 112
 113 /* Encode a perf_event_map entry into a long.  */
 114 static unsigned long perf_event_encode(const struct perf_event_map *pmap)
 115 {
 116         return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
 117 }
 118
 119 static u8 perf_event_get_msk(unsigned long val)
 120 {
 121         return val & 0xff;
 122 }
 123
 124 static u64 perf_event_get_enc(unsigned long val)
 125 {
 126         return val >> 16;
 127 }
 128
 129 #define C(x) PERF_COUNT_HW_CACHE_##x
 130
 131 #define CACHE_OP_UNSUPPORTED    0xfffe
 132 #define CACHE_OP_NONSENSE       0xffff
 133
 134 typedef struct perf_event_map cache_map_t
 135                                 [PERF_COUNT_HW_CACHE_MAX]
 136                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 137                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 138
 139 struct sparc_pmu {
 140         const struct perf_event_map     *(*event_map)(int);
 141         const cache_map_t               *cache_map;
 142         int                             max_events;
 143         int                             upper_shift;
 144         int                             lower_shift;
 145         int                             event_mask;
 146         int                             hv_bit;
 147         int                             irq_bit;
 148         int                             upper_nop;
 149         int                             lower_nop;
 150 };
 151
 152 static const struct perf_event_map ultra3_perfmon_event_map[] = {
 153         [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER },
 154         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER },
 155         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER },
 156         [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
 157 };
 158
 159 static const struct perf_event_map *ultra3_event_map(int event_id)
 160 {
 161         return &ultra3_perfmon_event_map[event_id];
 162 }
 163
 164 static const cache_map_t ultra3_cache_map = {
 165 [C(L1D)] = {
 166         [C(OP_READ)] = {
 167                 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
 168                 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
 169         },
 170         [C(OP_WRITE)] = {
 171                 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
 172                 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
 173         },
 174         [C(OP_PREFETCH)] = {
 175                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 176                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 177         },
 178 },
 179 [C(L1I)] = {
 180         [C(OP_READ)] = {
 181                 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
 182                 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
 183         },
 184         [ C(OP_WRITE) ] = {
 185                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
 186                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
 187         },
 188         [ C(OP_PREFETCH) ] = {
 189                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 190                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 191         },
 192 },
 193 [C(LL)] = {
 194         [C(OP_READ)] = {
 195                 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
 196                 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
 197         },
 198         [C(OP_WRITE)] = {
 199                 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
 200                 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
 201         },
 202         [C(OP_PREFETCH)] = {
 203                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 204                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 205         },
 206 },
 207 [C(DTLB)] = {
 208         [C(OP_READ)] = {
 209                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 210                 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
 211         },
 212         [ C(OP_WRITE) ] = {
 213                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 214                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 215         },
 216         [ C(OP_PREFETCH) ] = {
 217                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 218                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 219         },
 220 },
 221 [C(ITLB)] = {
 222         [C(OP_READ)] = {
 223                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 224                 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
 225         },
 226         [ C(OP_WRITE) ] = {
 227                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 228                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 229         },
 230         [ C(OP_PREFETCH) ] = {
 231                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 232                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 233         },
 234 },
 235 [C(BPU)] = {
 236         [C(OP_READ)] = {
 237                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 238                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 239         },
 240         [ C(OP_WRITE) ] = {
 241                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 242                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 243         },
 244         [ C(OP_PREFETCH) ] = {
 245                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 246                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 247         },
 248 },
 249 };
 250
 251 static const struct sparc_pmu ultra3_pmu = {
 252         .event_map      = ultra3_event_map,
 253         .cache_map      = &ultra3_cache_map,
 254         .max_events     = ARRAY_SIZE(ultra3_perfmon_event_map),
 255         .upper_shift    = 11,
 256         .lower_shift    = 4,
 257         .event_mask     = 0x3f,
 258         .upper_nop      = 0x1c,
 259         .lower_nop      = 0x14,
 260 };
 261
 262 /* Niagara1 is very limited.  The upper PIC is hard-locked to count
 263  * only instructions, so it is free running which creates all kinds of
 264  * problems.  Some hardware designs make one wonder if the creator
 265  * even looked at how this stuff gets used by software.
 266  */
 267 static const struct perf_event_map niagara1_perfmon_event_map[] = {
 268         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER },
 269         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER },
 270         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE },
 271         [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER },
 272 };
 273
 274 static const struct perf_event_map *niagara1_event_map(int event_id)
 275 {
 276         return &niagara1_perfmon_event_map[event_id];
 277 }
 278
 279 static const cache_map_t niagara1_cache_map = {
 280 [C(L1D)] = {
 281         [C(OP_READ)] = {
 282                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 283                 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
 284         },
 285         [C(OP_WRITE)] = {
 286                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 287                 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
 288         },
 289         [C(OP_PREFETCH)] = {
 290                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 291                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 292         },
 293 },
 294 [C(L1I)] = {
 295         [C(OP_READ)] = {
 296                 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
 297                 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
 298         },
 299         [ C(OP_WRITE) ] = {
 300                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
 301                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
 302         },
 303         [ C(OP_PREFETCH) ] = {
 304                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 305                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 306         },
 307 },
 308 [C(LL)] = {
 309         [C(OP_READ)] = {
 310                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 311                 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
 312         },
 313         [C(OP_WRITE)] = {
 314                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 315                 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
 316         },
 317         [C(OP_PREFETCH)] = {
 318                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 319                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 320         },
 321 },
 322 [C(DTLB)] = {
 323         [C(OP_READ)] = {
 324                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 325                 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
 326         },
 327         [ C(OP_WRITE) ] = {
 328                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 329                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 330         },
 331         [ C(OP_PREFETCH) ] = {
 332                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 333                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 334         },
 335 },
 336 [C(ITLB)] = {
 337         [C(OP_READ)] = {
 338                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 339                 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
 340         },
 341         [ C(OP_WRITE) ] = {
 342                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 343                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 344         },
 345         [ C(OP_PREFETCH) ] = {
 346                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 347                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 348         },
 349 },
 350 [C(BPU)] = {
 351         [C(OP_READ)] = {
 352                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 353                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 354         },
 355         [ C(OP_WRITE) ] = {
 356                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 357                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 358         },
 359         [ C(OP_PREFETCH) ] = {
 360                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 361                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 362         },
 363 },
 364 };
 365
 366 static const struct sparc_pmu niagara1_pmu = {
 367         .event_map      = niagara1_event_map,
 368         .cache_map      = &niagara1_cache_map,
 369         .max_events     = ARRAY_SIZE(niagara1_perfmon_event_map),
 370         .upper_shift    = 0,
 371         .lower_shift    = 4,
 372         .event_mask     = 0x7,
 373         .upper_nop      = 0x0,
 374         .lower_nop      = 0x0,
 375 };
 376
 377 static const struct perf_event_map niagara2_perfmon_event_map[] = {
 378         [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER },
 379         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER },
 380         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER },
 381         [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER },
 382         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER },
 383         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER },
 384 };
 385
 386 static const struct perf_event_map *niagara2_event_map(int event_id)
 387 {
 388         return &niagara2_perfmon_event_map[event_id];
 389 }
 390
 391 static const cache_map_t niagara2_cache_map = {
 392 [C(L1D)] = {
 393         [C(OP_READ)] = {
 394                 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
 395                 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
 396         },
 397         [C(OP_WRITE)] = {
 398                 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
 399                 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
 400         },
 401         [C(OP_PREFETCH)] = {
 402                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 403                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 404         },
 405 },
 406 [C(L1I)] = {
 407         [C(OP_READ)] = {
 408                 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
 409                 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
 410         },
 411         [ C(OP_WRITE) ] = {
 412                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
 413                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
 414         },
 415         [ C(OP_PREFETCH) ] = {
 416                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 417                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 418         },
 419 },
 420 [C(LL)] = {
 421         [C(OP_READ)] = {
 422                 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
 423                 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
 424         },
 425         [C(OP_WRITE)] = {
 426                 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
 427                 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
 428         },
 429         [C(OP_PREFETCH)] = {
 430                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 431                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 432         },
 433 },
 434 [C(DTLB)] = {
 435         [C(OP_READ)] = {
 436                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 437                 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
 438         },
 439         [ C(OP_WRITE) ] = {
 440                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 441                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 442         },
 443         [ C(OP_PREFETCH) ] = {
 444                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 445                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 446         },
 447 },
 448 [C(ITLB)] = {
 449         [C(OP_READ)] = {
 450                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 451                 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
 452         },
 453         [ C(OP_WRITE) ] = {
 454                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 455                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 456         },
 457         [ C(OP_PREFETCH) ] = {
 458                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 459                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 460         },
 461 },
 462 [C(BPU)] = {
 463         [C(OP_READ)] = {
 464                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 465                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 466         },
 467         [ C(OP_WRITE) ] = {
 468                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 469                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 470         },
 471         [ C(OP_PREFETCH) ] = {
 472                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 473                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 474         },
 475 },
 476 };
 477
 478 static const struct sparc_pmu niagara2_pmu = {
 479         .event_map      = niagara2_event_map,
 480         .cache_map      = &niagara2_cache_map,
 481         .max_events     = ARRAY_SIZE(niagara2_perfmon_event_map),
 482         .upper_shift    = 19,
 483         .lower_shift    = 6,
 484         .event_mask     = 0xfff,
 485         .hv_bit         = 0x8,
 486         .irq_bit        = 0x30,
 487         .upper_nop      = 0x220,
 488         .lower_nop      = 0x220,
 489 };
 490
 491 static const struct sparc_pmu *sparc_pmu __read_mostly;
 492
 493 static u64 event_encoding(u64 event_id, int idx)
 494 {
 495         if (idx == PIC_UPPER_INDEX)
 496                 event_id <<= sparc_pmu->upper_shift;
 497         else
 498                 event_id <<= sparc_pmu->lower_shift;
 499         return event_id;
 500 }
 501
 502 static u64 mask_for_index(int idx)
 503 {
 504         return event_encoding(sparc_pmu->event_mask, idx);
 505 }
 506
 507 static u64 nop_for_index(int idx)
 508 {
 509         return event_encoding(idx == PIC_UPPER_INDEX ?
 510                               sparc_pmu->upper_nop :
 511                               sparc_pmu->lower_nop, idx);
 512 }
 513
 514 static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
 515 {
 516         u64 enc, val, mask = mask_for_index(idx);
 517
 518         enc = perf_event_get_enc(cpuc->events[idx]);
 519
 520         val = cpuc->pcr;
 521         val &= ~mask;
 522         val |= event_encoding(enc, idx);
 523         cpuc->pcr = val;
 524
 525         pcr_ops->write(cpuc->pcr);
 526 }
 527
 528 static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
 529 {
 530         u64 mask = mask_for_index(idx);
 531         u64 nop = nop_for_index(idx);
 532         u64 val;
 533
 534         val = cpuc->pcr;
 535         val &= ~mask;
 536         val |= nop;
 537         cpuc->pcr = val;
 538
 539         pcr_ops->write(cpuc->pcr);
 540 }
 541
 542 static u32 read_pmc(int idx)
 543 {
 544         u64 val;
 545
 546         read_pic(val);
 547         if (idx == PIC_UPPER_INDEX)
 548                 val >>= 32;
 549
 550         return val & 0xffffffff;
 551 }
 552
 553 static void write_pmc(int idx, u64 val)
 554 {
 555         u64 shift, mask, pic;
 556
 557         shift = 0;
 558         if (idx == PIC_UPPER_INDEX)
 559                 shift = 32;
 560
 561         mask = ((u64) 0xffffffff) << shift;
 562         val <<= shift;
 563
 564         read_pic(pic);
 565         pic &= ~mask;
 566         pic |= val;
 567         write_pic(pic);
 568 }
 569
 570 static u64 sparc_perf_event_update(struct perf_event *event,
 571                                    struct hw_perf_event *hwc, int idx)
 572 {
 573         int shift = 64 - 32;
 574         u64 prev_raw_count, new_raw_count;
 575         s64 delta;
 576
 577 again:
 578         prev_raw_count = local64_read(&hwc->prev_count);
 579         new_raw_count = read_pmc(idx);
 580
 581         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 582                              new_raw_count) != prev_raw_count)
 583                 goto again;
 584
 585         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 586         delta >>= shift;
 587
 588         local64_add(delta, &event->count);
 589         local64_sub(delta, &hwc->period_left);
 590
 591         return new_raw_count;
 592 }
 593
 594 static int sparc_perf_event_set_period(struct perf_event *event,
 595                                        struct hw_perf_event *hwc, int idx)
 596 {
 597         s64 left = local64_read(&hwc->period_left);
 598         s64 period = hwc->sample_period;
 599         int ret = 0;
 600
 601         if (unlikely(left <= -period)) {
 602                 left = period;
 603                 local64_set(&hwc->period_left, left);
 604                 hwc->last_period = period;
 605                 ret = 1;
 606         }
 607
 608         if (unlikely(left <= 0)) {
 609                 left += period;
 610                 local64_set(&hwc->period_left, left);
 611                 hwc->last_period = period;
 612                 ret = 1;
 613         }
 614         if (left > MAX_PERIOD)
 615                 left = MAX_PERIOD;
 616
 617         local64_set(&hwc->prev_count, (u64)-left);
 618
 619         write_pmc(idx, (u64)(-left) & 0xffffffff);
 620
 621         perf_event_update_userpage(event);
 622
 623         return ret;
 624 }
 625
 626 /* If performance event entries have been added, move existing
 627  * events around (if necessary) and then assign new entries to
 628  * counters.
 629  */
 630 static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr)
 631 {
 632         int i;
 633
 634         if (!cpuc->n_added)
 635                 goto out;
 636
 637         /* Read in the counters which are moving.  */
 638         for (i = 0; i < cpuc->n_events; i++) {
 639                 struct perf_event *cp = cpuc->event[i];
 640
 641                 if (cpuc->current_idx[i] != PIC_NO_INDEX &&
 642                     cpuc->current_idx[i] != cp->hw.idx) {
 643                         sparc_perf_event_update(cp, &cp->hw,
 644                                                 cpuc->current_idx[i]);
 645                         cpuc->current_idx[i] = PIC_NO_INDEX;
 646                 }
 647         }
 648
 649         /* Assign to counters all unassigned events.  */
 650         for (i = 0; i < cpuc->n_events; i++) {
 651                 struct perf_event *cp = cpuc->event[i];
 652                 struct hw_perf_event *hwc = &cp->hw;
 653                 int idx = hwc->idx;
 654                 u64 enc;
 655
 656                 if (cpuc->current_idx[i] != PIC_NO_INDEX)
 657                         continue;
 658
 659                 sparc_perf_event_set_period(cp, hwc, idx);
 660                 cpuc->current_idx[i] = idx;
 661
 662                 enc = perf_event_get_enc(cpuc->events[i]);
 663                 pcr &= ~mask_for_index(idx);
 664                 if (hwc->state & PERF_HES_STOPPED)
 665                         pcr |= nop_for_index(idx);
 666                 else
 667                         pcr |= event_encoding(enc, idx);
 668         }
 669 out:
 670         return pcr;
 671 }
 672
 673 static void sparc_pmu_enable(struct pmu *pmu)
 674 {
 675         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 676         u64 pcr;
 677
 678         if (cpuc->enabled)
 679                 return;
 680
 681         cpuc->enabled = 1;
 682         barrier();
 683
 684         pcr = cpuc->pcr;
 685         if (!cpuc->n_events) {
 686                 pcr = 0;
 687         } else {
 688                 pcr = maybe_change_configuration(cpuc, pcr);
 689
 690                 /* We require that all of the events have the same
 691                  * configuration, so just fetch the settings from the
 692                  * first entry.
 693                  */
 694                 cpuc->pcr = pcr | cpuc->event[0]->hw.config_base;
 695         }
 696
 697         pcr_ops->write(cpuc->pcr);
 698 }
 699
 700 static void sparc_pmu_disable(struct pmu *pmu)
 701 {
 702         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 703         u64 val;
 704
 705         if (!cpuc->enabled)
 706                 return;
 707
 708         cpuc->enabled = 0;
 709         cpuc->n_added = 0;
 710
 711         val = cpuc->pcr;
 712         val &= ~(PCR_UTRACE | PCR_STRACE |
 713                  sparc_pmu->hv_bit | sparc_pmu->irq_bit);
 714         cpuc->pcr = val;
 715
 716         pcr_ops->write(cpuc->pcr);
 717 }
 718
 719 static int active_event_index(struct cpu_hw_events *cpuc,
 720                               struct perf_event *event)
 721 {
 722         int i;
 723
 724         for (i = 0; i < cpuc->n_events; i++) {
 725                 if (cpuc->event[i] == event)
 726                         break;
 727         }
 728         BUG_ON(i == cpuc->n_events);
 729         return cpuc->current_idx[i];
 730 }
 731
 732 static void sparc_pmu_start(struct perf_event *event, int flags)
 733 {
 734         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 735         int idx = active_event_index(cpuc, event);
 736
 737         if (flags & PERF_EF_RELOAD) {
 738                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
 739                 sparc_perf_event_set_period(event, &event->hw, idx);
 740         }
 741
 742         event->hw.state = 0;
 743
 744         sparc_pmu_enable_event(cpuc, &event->hw, idx);
 745 }
 746
 747 static void sparc_pmu_stop(struct perf_event *event, int flags)
 748 {
 749         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 750         int idx = active_event_index(cpuc, event);
 751
 752         if (!(event->hw.state & PERF_HES_STOPPED)) {
 753                 sparc_pmu_disable_event(cpuc, &event->hw, idx);
 754                 event->hw.state |= PERF_HES_STOPPED;
 755         }
 756
 757         if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) {
 758                 sparc_perf_event_update(event, &event->hw, idx);
 759                 event->hw.state |= PERF_HES_UPTODATE;
 760         }
 761 }
 762
 763 static void sparc_pmu_del(struct perf_event *event, int _flags)
 764 {
 765         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 766         unsigned long flags;
 767         int i;
 768
 769         local_irq_save(flags);
 770         perf_pmu_disable(event->pmu);
 771
 772         for (i = 0; i < cpuc->n_events; i++) {
 773                 if (event == cpuc->event[i]) {
 774                         /* Absorb the final count and turn off the
 775                          * event.
 776                          */
 777                         sparc_pmu_stop(event, PERF_EF_UPDATE);
 778
 779                         /* Shift remaining entries down into
 780                          * the existing slot.
 781                          */
 782                         while (++i < cpuc->n_events) {
 783                                 cpuc->event[i - 1] = cpuc->event[i];
 784                                 cpuc->events[i - 1] = cpuc->events[i];
 785                                 cpuc->current_idx[i - 1] =
 786                                         cpuc->current_idx[i];
 787                         }
 788
 789                         perf_event_update_userpage(event);
 790
 791                         cpuc->n_events--;
 792                         break;
 793                 }
 794         }
 795
 796         perf_pmu_enable(event->pmu);
 797         local_irq_restore(flags);
 798 }
 799
 800 static void sparc_pmu_read(struct perf_event *event)
 801 {
 802         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 803         int idx = active_event_index(cpuc, event);
 804         struct hw_perf_event *hwc = &event->hw;
 805
 806         sparc_perf_event_update(event, hwc, idx);
 807 }
 808
 809 static atomic_t active_events = ATOMIC_INIT(0);
 810 static DEFINE_MUTEX(pmc_grab_mutex);
 811
 812 static void perf_stop_nmi_watchdog(void *unused)
 813 {
 814         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 815
 816         stop_nmi_watchdog(NULL);
 817         cpuc->pcr = pcr_ops->read();
 818 }
 819
 820 void perf_event_grab_pmc(void)
 821 {
 822         if (atomic_inc_not_zero(&active_events))
 823                 return;
 824
 825         mutex_lock(&pmc_grab_mutex);
 826         if (atomic_read(&active_events) == 0) {
 827                 if (atomic_read(&nmi_active) > 0) {
 828                         on_each_cpu(perf_stop_nmi_watchdog, NULL, 1);
 829                         BUG_ON(atomic_read(&nmi_active) != 0);
 830                 }
 831                 atomic_inc(&active_events);
 832         }
 833         mutex_unlock(&pmc_grab_mutex);
 834 }
 835
 836 void perf_event_release_pmc(void)
 837 {
 838         if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) {
 839                 if (atomic_read(&nmi_active) == 0)
 840                         on_each_cpu(start_nmi_watchdog, NULL, 1);
 841                 mutex_unlock(&pmc_grab_mutex);
 842         }
 843 }
 844
 845 static const struct perf_event_map *sparc_map_cache_event(u64 config)
 846 {
 847         unsigned int cache_type, cache_op, cache_result;
 848         const struct perf_event_map *pmap;
 849
 850         if (!sparc_pmu->cache_map)
 851                 return ERR_PTR(-ENOENT);
 852
 853         cache_type = (config >>  0) & 0xff;
 854         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 855                 return ERR_PTR(-EINVAL);
 856
 857         cache_op = (config >>  8) & 0xff;
 858         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 859                 return ERR_PTR(-EINVAL);
 860
 861         cache_result = (config >> 16) & 0xff;
 862         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 863                 return ERR_PTR(-EINVAL);
 864
 865         pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]);
 866
 867         if (pmap->encoding == CACHE_OP_UNSUPPORTED)
 868                 return ERR_PTR(-ENOENT);
 869
 870         if (pmap->encoding == CACHE_OP_NONSENSE)
 871                 return ERR_PTR(-EINVAL);
 872
 873         return pmap;
 874 }
 875
 876 static void hw_perf_event_destroy(struct perf_event *event)
 877 {
 878         perf_event_release_pmc();
 879 }
 880
 881 /* Make sure all events can be scheduled into the hardware at
 882  * the same time.  This is simplified by the fact that we only
 883  * need to support 2 simultaneous HW events.
 884  *
 885  * As a side effect, the evts[]->hw.idx values will be assigned
 886  * on success.  These are pending indexes.  When the events are
 887  * actually programmed into the chip, these values will propagate
 888  * to the per-cpu cpuc->current_idx[] slots, see the code in
 889  * maybe_change_configuration() for details.
 890  */
 891 static int sparc_check_constraints(struct perf_event **evts,
 892                                    unsigned long *events, int n_ev)
 893 {
 894         u8 msk0 = 0, msk1 = 0;
 895         int idx0 = 0;
 896
 897         /* This case is possible when we are invoked from
 898          * hw_perf_group_sched_in().
 899          */
 900         if (!n_ev)
 901                 return 0;
 902
 903         if (n_ev > MAX_HWEVENTS)
 904                 return -1;
 905
 906         msk0 = perf_event_get_msk(events[0]);
 907         if (n_ev == 1) {
 908                 if (msk0 & PIC_LOWER)
 909                         idx0 = 1;
 910                 goto success;
 911         }
 912         BUG_ON(n_ev != 2);
 913         msk1 = perf_event_get_msk(events[1]);
 914
 915         /* If both events can go on any counter, OK.  */
 916         if (msk0 == (PIC_UPPER | PIC_LOWER) &&
 917             msk1 == (PIC_UPPER | PIC_LOWER))
 918                 goto success;
 919
 920         /* If one event is limited to a specific counter,
 921          * and the other can go on both, OK.
 922          */
 923         if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
 924             msk1 == (PIC_UPPER | PIC_LOWER)) {
 925                 if (msk0 & PIC_LOWER)
 926                         idx0 = 1;
 927                 goto success;
 928         }
 929
 930         if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
 931             msk0 == (PIC_UPPER | PIC_LOWER)) {
 932                 if (msk1 & PIC_UPPER)
 933                         idx0 = 1;
 934                 goto success;
 935         }
 936
 937         /* If the events are fixed to different counters, OK.  */
 938         if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
 939             (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
 940                 if (msk0 & PIC_LOWER)
 941                         idx0 = 1;
 942                 goto success;
 943         }
 944
 945         /* Otherwise, there is a conflict.  */
 946         return -1;
 947
 948 success:
 949         evts[0]->hw.idx = idx0;
 950         if (n_ev == 2)
 951                 evts[1]->hw.idx = idx0 ^ 1;
 952         return 0;
 953 }
 954
 955 static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
 956 {
 957         int eu = 0, ek = 0, eh = 0;
 958         struct perf_event *event;
 959         int i, n, first;
 960
 961         n = n_prev + n_new;
 962         if (n <= 1)
 963                 return 0;
 964
 965         first = 1;
 966         for (i = 0; i < n; i++) {
 967                 event = evts[i];
 968                 if (first) {
 969                         eu = event->attr.exclude_user;
 970                         ek = event->attr.exclude_kernel;
 971                         eh = event->attr.exclude_hv;
 972                         first = 0;
 973                 } else if (event->attr.exclude_user != eu ||
 974                            event->attr.exclude_kernel != ek ||
 975                            event->attr.exclude_hv != eh) {
 976                         return -EAGAIN;
 977                 }
 978         }
 979
 980         return 0;
 981 }
 982
 983 static int collect_events(struct perf_event *group, int max_count,
 984                           struct perf_event *evts[], unsigned long *events,
 985                           int *current_idx)
 986 {
 987         struct perf_event *event;
 988         int n = 0;
 989
 990         if (!is_software_event(group)) {
 991                 if (n >= max_count)
 992                         return -1;
 993                 evts[n] = group;
 994                 events[n] = group->hw.event_base;
 995                 current_idx[n++] = PIC_NO_INDEX;
 996         }
 997         list_for_each_entry(event, &group->sibling_list, group_entry) {
 998                 if (!is_software_event(event) &&
 999                     event->state != PERF_EVENT_STATE_OFF) {
1000                         if (n >= max_count)
1001                                 return -1;
1002                         evts[n] = event;
1003                         events[n] = event->hw.event_base;
1004                         current_idx[n++] = PIC_NO_INDEX;
1005                 }
1006         }
1007         return n;
1008 }
1009
1010 static int sparc_pmu_add(struct perf_event *event, int ef_flags)
1011 {
1012         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1013         int n0, ret = -EAGAIN;
1014         unsigned long flags;
1015
1016         local_irq_save(flags);
1017         perf_pmu_disable(event->pmu);
1018
1019         n0 = cpuc->n_events;
1020         if (n0 >= MAX_HWEVENTS)
1021                 goto out;
1022
1023         cpuc->event[n0] = event;
1024         cpuc->events[n0] = event->hw.event_base;
1025         cpuc->current_idx[n0] = PIC_NO_INDEX;
1026
1027         event->hw.state = PERF_HES_UPTODATE;
1028         if (!(ef_flags & PERF_EF_START))
1029                 event->hw.state |= PERF_HES_STOPPED;
1030
1031         /*
1032          * If group events scheduling transaction was started,
1033          * skip the schedulability test here, it will be performed
1034          * at commit time(->commit_txn) as a whole
1035          */
1036         if (cpuc->group_flag & PERF_EVENT_TXN)
1037                 goto nocheck;
1038
1039         if (check_excludes(cpuc->event, n0, 1))
1040                 goto out;
1041         if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
1042                 goto out;
1043
1044 nocheck:
1045         cpuc->n_events++;
1046         cpuc->n_added++;
1047
1048         ret = 0;
1049 out:
1050         perf_pmu_enable(event->pmu);
1051         local_irq_restore(flags);
1052         return ret;
1053 }
1054
1055 static int sparc_pmu_event_init(struct perf_event *event)
1056 {
1057         struct perf_event_attr *attr = &event->attr;
1058         struct perf_event *evts[MAX_HWEVENTS];
1059         struct hw_perf_event *hwc = &event->hw;
1060         unsigned long events[MAX_HWEVENTS];
1061         int current_idx_dmy[MAX_HWEVENTS];
1062         const struct perf_event_map *pmap;
1063         int n;
1064
1065         if (atomic_read(&nmi_active) < 0)
1066                 return -ENODEV;
1067
1068         switch (attr->type) {
1069         case PERF_TYPE_HARDWARE:
1070                 if (attr->config >= sparc_pmu->max_events)
1071                         return -EINVAL;
1072                 pmap = sparc_pmu->event_map(attr->config);
1073                 break;
1074
1075         case PERF_TYPE_HW_CACHE:
1076                 pmap = sparc_map_cache_event(attr->config);
1077                 if (IS_ERR(pmap))
1078                         return PTR_ERR(pmap);
1079                 break;
1080
1081         case PERF_TYPE_RAW:
1082                 pmap = NULL;
1083                 break;
1084
1085         default:
1086                 return -ENOENT;
1087
1088         }
1089
1090         if (pmap) {
1091                 hwc->event_base = perf_event_encode(pmap);
1092         } else {
1093                 /*
1094                  * User gives us "(encoding << 16) | pic_mask" for
1095                  * PERF_TYPE_RAW events.
1096                  */
1097                 hwc->event_base = attr->config;
1098         }
1099
1100         /* We save the enable bits in the config_base.  */
1101         hwc->config_base = sparc_pmu->irq_bit;
1102         if (!attr->exclude_user)
1103                 hwc->config_base |= PCR_UTRACE;
1104         if (!attr->exclude_kernel)
1105                 hwc->config_base |= PCR_STRACE;
1106         if (!attr->exclude_hv)
1107                 hwc->config_base |= sparc_pmu->hv_bit;
1108
1109         n = 0;
1110         if (event->group_leader != event) {
1111                 n = collect_events(event->group_leader,
1112                                    MAX_HWEVENTS - 1,
1113                                    evts, events, current_idx_dmy);
1114                 if (n < 0)
1115                         return -EINVAL;
1116         }
1117         events[n] = hwc->event_base;
1118         evts[n] = event;
1119
1120         if (check_excludes(evts, n, 1))
1121                 return -EINVAL;
1122
1123         if (sparc_check_constraints(evts, events, n + 1))
1124                 return -EINVAL;
1125
1126         hwc->idx = PIC_NO_INDEX;
1127
1128         /* Try to do all error checking before this point, as unwinding
1129          * state after grabbing the PMC is difficult.
1130          */
1131         perf_event_grab_pmc();
1132         event->destroy = hw_perf_event_destroy;
1133
1134         if (!hwc->sample_period) {
1135                 hwc->sample_period = MAX_PERIOD;
1136                 hwc->last_period = hwc->sample_period;
1137                 local64_set(&hwc->period_left, hwc->sample_period);
1138         }
1139
1140         return 0;
1141 }
1142
1143 /*
1144  * Start group events scheduling transaction
1145  * Set the flag to make pmu::enable() not perform the
1146  * schedulability test, it will be performed at commit time
1147  */
1148 static void sparc_pmu_start_txn(struct pmu *pmu)
1149 {
1150         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1151
1152         perf_pmu_disable(pmu);
1153         cpuhw->group_flag |= PERF_EVENT_TXN;
1154 }
1155
1156 /*
1157  * Stop group events scheduling transaction
1158  * Clear the flag and pmu::enable() will perform the
1159  * schedulability test.
1160  */
1161 static void sparc_pmu_cancel_txn(struct pmu *pmu)
1162 {
1163         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1164
1165         cpuhw->group_flag &= ~PERF_EVENT_TXN;
1166         perf_pmu_enable(pmu);
1167 }
1168
1169 /*
1170  * Commit group events scheduling transaction
1171  * Perform the group schedulability test as a whole
1172  * Return 0 if success
1173  */
1174 static int sparc_pmu_commit_txn(struct pmu *pmu)
1175 {
1176         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1177         int n;
1178
1179         if (!sparc_pmu)
1180                 return -EINVAL;
1181
1182         cpuc = &__get_cpu_var(cpu_hw_events);
1183         n = cpuc->n_events;
1184         if (check_excludes(cpuc->event, 0, n))
1185                 return -EINVAL;
1186         if (sparc_check_constraints(cpuc->event, cpuc->events, n))
1187                 return -EAGAIN;
1188
1189         cpuc->group_flag &= ~PERF_EVENT_TXN;
1190         perf_pmu_enable(pmu);
1191         return 0;
1192 }
1193
1194 static struct pmu pmu = {
1195         .pmu_enable     = sparc_pmu_enable,
1196         .pmu_disable    = sparc_pmu_disable,
1197         .event_init     = sparc_pmu_event_init,
1198         .add            = sparc_pmu_add,
1199         .del            = sparc_pmu_del,
1200         .start          = sparc_pmu_start,
1201         .stop           = sparc_pmu_stop,
1202         .read           = sparc_pmu_read,
1203         .start_txn      = sparc_pmu_start_txn,
1204         .cancel_txn     = sparc_pmu_cancel_txn,
1205         .commit_txn     = sparc_pmu_commit_txn,
1206 };
1207
1208 void perf_event_print_debug(void)
1209 {
1210         unsigned long flags;
1211         u64 pcr, pic;
1212         int cpu;
1213
1214         if (!sparc_pmu)
1215                 return;
1216
1217         local_irq_save(flags);
1218
1219         cpu = smp_processor_id();
1220
1221         pcr = pcr_ops->read();
1222         read_pic(pic);
1223
1224         pr_info("\n");
1225         pr_info("CPU#%d: PCR[%016llx] PIC[%016llx]\n",
1226                 cpu, pcr, pic);
1227
1228         local_irq_restore(flags);
1229 }
1230
1231 static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
1232                                             unsigned long cmd, void *__args)
1233 {
1234         struct die_args *args = __args;
1235         struct perf_sample_data data;
1236         struct cpu_hw_events *cpuc;
1237         struct pt_regs *regs;
1238         int i;
1239
1240         if (!atomic_read(&active_events))
1241                 return NOTIFY_DONE;
1242
1243         switch (cmd) {
1244         case DIE_NMI:
1245                 break;
1246
1247         default:
1248                 return NOTIFY_DONE;
1249         }
1250
1251         regs = args->regs;
1252
1253         perf_sample_data_init(&data, 0);
1254
1255         cpuc = &__get_cpu_var(cpu_hw_events);
1256
1257         /* If the PMU has the TOE IRQ enable bits, we need to do a
1258          * dummy write to the %pcr to clear the overflow bits and thus
1259          * the interrupt.
1260          *
1261          * Do this before we peek at the counters to determine
1262          * overflow so we don't lose any events.
1263          */
1264         if (sparc_pmu->irq_bit)
1265                 pcr_ops->write(cpuc->pcr);
1266
1267         for (i = 0; i < cpuc->n_events; i++) {
1268                 struct perf_event *event = cpuc->event[i];
1269                 int idx = cpuc->current_idx[i];
1270                 struct hw_perf_event *hwc;
1271                 u64 val;
1272
1273                 hwc = &event->hw;
1274                 val = sparc_perf_event_update(event, hwc, idx);
1275                 if (val & (1ULL << 31))
1276                         continue;
1277
1278                 data.period = event->hw.last_period;
1279                 if (!sparc_perf_event_set_period(event, hwc, idx))
1280                         continue;
1281
1282                 if (perf_event_overflow(event, 1, &data, regs))
1283                         sparc_pmu_stop(event, 0);
1284         }
1285
1286         return NOTIFY_STOP;
1287 }
1288
1289 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1290         .notifier_call          = perf_event_nmi_handler,
1291 };
1292
1293 static bool __init supported_pmu(void)
1294 {
1295         if (!strcmp(sparc_pmu_type, "ultra3") ||
1296             !strcmp(sparc_pmu_type, "ultra3+") ||
1297             !strcmp(sparc_pmu_type, "ultra3i") ||
1298             !strcmp(sparc_pmu_type, "ultra4+")) {
1299                 sparc_pmu = &ultra3_pmu;
1300                 return true;
1301         }
1302         if (!strcmp(sparc_pmu_type, "niagara")) {
1303                 sparc_pmu = &niagara1_pmu;
1304                 return true;
1305         }
1306         if (!strcmp(sparc_pmu_type, "niagara2") ||
1307             !strcmp(sparc_pmu_type, "niagara3")) {
1308                 sparc_pmu = &niagara2_pmu;
1309                 return true;
1310         }
1311         return false;
1312 }
1313
1314 int __init init_hw_perf_events(void)
1315 {
1316         pr_info("Performance events: ");
1317
1318         if (!supported_pmu()) {
1319                 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
1320                 return 0;
1321         }
1322
1323         pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
1324
1325         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1326         register_die_notifier(&perf_event_nmi_notifier);
1327
1328         return 0;
1329 }
1330 early_initcall(init_hw_perf_events);
1331
1332 void perf_callchain_kernel(struct perf_callchain_entry *entry,
1333                            struct pt_regs *regs)
1334 {
1335         unsigned long ksp, fp;
1336 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1337         int graph = 0;
1338 #endif
1339
1340         stack_trace_flush();
1341
1342         perf_callchain_store(entry, regs->tpc);
1343
1344         ksp = regs->u_regs[UREG_I6];
1345         fp = ksp + STACK_BIAS;
1346         do {
1347                 struct sparc_stackf *sf;
1348                 struct pt_regs *regs;
1349                 unsigned long pc;
1350
1351                 if (!kstack_valid(current_thread_info(), fp))
1352                         break;
1353
1354                 sf = (struct sparc_stackf *) fp;
1355                 regs = (struct pt_regs *) (sf + 1);
1356
1357                 if (kstack_is_trap_frame(current_thread_info(), regs)) {
1358                         if (user_mode(regs))
1359                                 break;
1360                         pc = regs->tpc;
1361                         fp = regs->u_regs[UREG_I6] + STACK_BIAS;
1362                 } else {
1363                         pc = sf->callers_pc;
1364                         fp = (unsigned long)sf->fp + STACK_BIAS;
1365                 }
1366                 perf_callchain_store(entry, pc);
1367 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1368                 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
1369                         int index = current->curr_ret_stack;
1370                         if (current->ret_stack && index >= graph) {
1371                                 pc = current->ret_stack[index - graph].ret;
1372                                 perf_callchain_store(entry, pc);
1373                                 graph++;
1374                         }
1375                 }
1376 #endif
1377         } while (entry->nr < PERF_MAX_STACK_DEPTH);
1378 }
1379
1380 static void perf_callchain_user_64(struct perf_callchain_entry *entry,
1381                                    struct pt_regs *regs)
1382 {
1383         unsigned long ufp;
1384
1385         ufp = regs->u_regs[UREG_I6] + STACK_BIAS;
1386         do {
1387                 struct sparc_stackf *usf, sf;
1388                 unsigned long pc;
1389
1390                 usf = (struct sparc_stackf *) ufp;
1391                 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1392                         break;
1393
1394                 pc = sf.callers_pc;
1395                 ufp = (unsigned long)sf.fp + STACK_BIAS;
1396                 perf_callchain_store(entry, pc);
1397         } while (entry->nr < PERF_MAX_STACK_DEPTH);
1398 }
1399
1400 static void perf_callchain_user_32(struct perf_callchain_entry *entry,
1401                                    struct pt_regs *regs)
1402 {
1403         unsigned long ufp;
1404
1405         ufp = regs->u_regs[UREG_I6] & 0xffffffffUL;
1406         do {
1407                 struct sparc_stackf32 *usf, sf;
1408                 unsigned long pc;
1409
1410                 usf = (struct sparc_stackf32 *) ufp;
1411                 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1412                         break;
1413
1414                 pc = sf.callers_pc;
1415                 ufp = (unsigned long)sf.fp;
1416                 perf_callchain_store(entry, pc);
1417         } while (entry->nr < PERF_MAX_STACK_DEPTH);
1418 }
1419
1420 void
1421 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1422 {
1423         perf_callchain_store(entry, regs->tpc);
1424
1425         if (!current->mm)
1426                 return;
1427
1428         flushw_user();
1429         if (test_thread_flag(TIF_32BIT))
1430                 perf_callchain_user_32(entry, regs);
1431         else
1432                 perf_callchain_user_64(entry, regs);
1433 }