1 // SPDX-License-Identifier: GPL-2.0
3 * arch/sh/kernel/cpu/init.c
7 * Copyright (C) 2002 - 2009 Paul Mundt
8 * Copyright (C) 2003 Richard Curnow
10 #include <linux/init.h>
11 #include <linux/kernel.h>
13 #include <linux/log2.h>
14 #include <asm/mmu_context.h>
15 #include <asm/processor.h>
16 #include <linux/uaccess.h>
18 #include <asm/cacheflush.h>
19 #include <asm/cache.h>
23 #include <asm/sh_bios.h>
24 #include <asm/setup.h>
39 * Generic wrapper for command line arguments to disable on-chip
40 * peripherals (nofpu, nodsp, and so forth).
42 #define onchip_setup(x) \
43 static int x##_disabled = !cpu_has_##x; \
45 static int x##_setup(char *opts) \
50 __setup("no" __stringify(x), x##_setup);
55 #ifdef CONFIG_SPECULATIVE_EXECUTION
56 #define CPUOPM 0xff2f0000
57 #define CPUOPM_RABD (1 << 5)
59 static void speculative_execution_init(void)
62 __raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
64 /* Flush the update */
65 (void)__raw_readl(CPUOPM);
69 #define speculative_execution_init() do { } while (0)
72 #ifdef CONFIG_CPU_SH4A
73 #define EXPMASK 0xff2f0004
74 #define EXPMASK_RTEDS (1 << 0)
75 #define EXPMASK_BRDSSLP (1 << 1)
76 #define EXPMASK_MMCAW (1 << 4)
78 static void expmask_init(void)
80 unsigned long expmask = __raw_readl(EXPMASK);
85 * Disable support for slottable sleep instruction, non-nop
86 * instructions in the rte delay slot, and associative writes to
87 * the memory-mapped cache array.
89 expmask &= ~(EXPMASK_RTEDS | EXPMASK_BRDSSLP | EXPMASK_MMCAW);
91 __raw_writel(expmask, EXPMASK);
95 #define expmask_init() do { } while (0)
98 /* 2nd-level cache init */
99 void __attribute__ ((weak)) l2_cache_init(void)
104 * Generic first-level cache init
106 #if defined(CONFIG_SUPERH32) && !defined(CONFIG_CPU_J2)
107 static void cache_init(void)
109 unsigned long ccr, flags;
112 ccr = __raw_readl(SH_CCR);
115 * At this point we don't know whether the cache is enabled or not - a
116 * bootloader may have enabled it. There are at least 2 things that
117 * could be dirty in the cache at this point:
118 * 1. kernel command line set up by boot loader
119 * 2. spilled registers from the prolog of this function
120 * => before re-initialising the cache, we must do a purge of the whole
121 * cache out to memory for safety. As long as nothing is spilled
122 * during the loop to lines that have already been done, this is safe.
125 if (ccr & CCR_CACHE_ENABLE) {
126 unsigned long ways, waysize, addrstart;
128 waysize = current_cpu_data.dcache.sets;
132 * If the OC is already in RAM mode, we only have
133 * half of the entries to flush..
135 if (ccr & CCR_CACHE_ORA)
139 waysize <<= current_cpu_data.dcache.entry_shift;
141 #ifdef CCR_CACHE_EMODE
142 /* If EMODE is not set, we only have 1 way to flush. */
143 if (!(ccr & CCR_CACHE_EMODE))
147 ways = current_cpu_data.dcache.ways;
149 addrstart = CACHE_OC_ADDRESS_ARRAY;
153 for (addr = addrstart;
154 addr < addrstart + waysize;
155 addr += current_cpu_data.dcache.linesz)
156 __raw_writel(0, addr);
158 addrstart += current_cpu_data.dcache.way_incr;
163 * Default CCR values .. enable the caches
164 * and invalidate them immediately..
166 flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE;
168 #ifdef CCR_CACHE_EMODE
169 /* Force EMODE if possible */
170 if (current_cpu_data.dcache.ways > 1)
171 flags |= CCR_CACHE_EMODE;
173 flags &= ~CCR_CACHE_EMODE;
176 #if defined(CONFIG_CACHE_WRITETHROUGH)
178 flags |= CCR_CACHE_WT;
179 #elif defined(CONFIG_CACHE_WRITEBACK)
181 flags |= CCR_CACHE_CB;
184 flags &= ~CCR_CACHE_ENABLE;
189 __raw_writel(flags, SH_CCR);
193 #define cache_init() do { } while (0)
196 #define CSHAPE(totalsize, linesize, assoc) \
197 ((totalsize & ~0xff) | (linesize << 4) | assoc)
199 #define CACHE_DESC_SHAPE(desc) \
200 CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways)
202 static void detect_cache_shape(void)
204 l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache);
206 if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED)
207 l1i_cache_shape = l1d_cache_shape;
209 l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache);
211 if (current_cpu_data.flags & CPU_HAS_L2_CACHE)
212 l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache);
214 l2_cache_shape = -1; /* No S-cache */
217 static void fpu_init(void)
219 /* Disable the FPU */
220 if (fpu_disabled && (current_cpu_data.flags & CPU_HAS_FPU)) {
221 printk("FPU Disabled\n");
222 current_cpu_data.flags &= ~CPU_HAS_FPU;
230 static void release_dsp(void)
234 /* Clear SR.DSP bit */
235 __asm__ __volatile__ (
244 static void dsp_init(void)
249 * Set the SR.DSP bit, wait for one instruction, and then read
252 __asm__ __volatile__ (
262 /* If the DSP bit is still set, this CPU has a DSP */
264 current_cpu_data.flags |= CPU_HAS_DSP;
266 /* Disable the DSP */
267 if (dsp_disabled && (current_cpu_data.flags & CPU_HAS_DSP)) {
268 printk("DSP Disabled\n");
269 current_cpu_data.flags &= ~CPU_HAS_DSP;
272 /* Now that we've determined the DSP status, clear the DSP bit. */
276 static inline void dsp_init(void) { }
277 #endif /* CONFIG_SH_DSP */
282 * This is our initial entry point for each CPU, and is invoked on the
283 * boot CPU prior to calling start_kernel(). For SMP, a combination of
284 * this and start_secondary() will bring up each processor to a ready
285 * state prior to hand forking the idle loop.
287 * We do all of the basic processor init here, including setting up
288 * the caches, FPU, DSP, etc. By the time start_kernel() is hit (and
289 * subsequently platform_setup()) things like determining the CPU
290 * subtype and initial configuration will all be done.
292 * Each processor family is still responsible for doing its own probing
293 * and cache configuration in cpu_probe().
295 asmlinkage void cpu_init(void)
297 current_thread_info()->cpu = hard_smp_processor_id();
299 /* First, probe the CPU */
302 if (current_cpu_data.type == CPU_SH_NONE)
303 panic("Unknown CPU");
305 /* First setup the rest of the I-cache info */
306 current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
307 current_cpu_data.icache.linesz;
309 current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
310 current_cpu_data.icache.linesz;
312 /* And the D-cache too */
313 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
314 current_cpu_data.dcache.linesz;
316 current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
317 current_cpu_data.dcache.linesz;
322 if (raw_smp_processor_id() == 0) {
324 shm_align_mask = max_t(unsigned long,
325 current_cpu_data.dcache.way_size - 1,
328 shm_align_mask = PAGE_SIZE - 1;
331 /* Boot CPU sets the cache shape */
332 detect_cache_shape();
339 * Initialize the per-CPU ASID cache very early, since the
340 * TLB flushing routines depend on this being setup.
342 current_cpu_data.asid_cache = NO_CONTEXT;
344 current_cpu_data.phys_bits = __in_29bit_mode() ? 29 : 32;
346 speculative_execution_init();
349 /* Do the rest of the boot processor setup */
350 if (raw_smp_processor_id() == 0) {
351 /* Save off the BIOS VBR, if there is one */
355 * Setup VBR for boot CPU. Secondary CPUs do this through
361 * Boot processor to setup the FP and extended state
364 init_thread_xstate();