1 #ifndef _ASM_S390_PCI_CLP_H
2 #define _ASM_S390_PCI_CLP_H
7 * Call Logical Processor - Command Codes
9 #define CLP_LIST_PCI 0x0002
10 #define CLP_QUERY_PCI_FN 0x0003
11 #define CLP_QUERY_PCI_FNGRP 0x0004
12 #define CLP_SET_PCI_FN 0x0005
14 /* PCI function handle list entry */
15 struct clp_fh_list_entry {
20 u32 fid; /* PCI function id */
21 u32 fh; /* PCI function handle */
24 #define CLP_RC_SETPCIFN_FH 0x0101 /* Invalid PCI fn handle */
25 #define CLP_RC_SETPCIFN_FHOP 0x0102 /* Fn handle not valid for op */
26 #define CLP_RC_SETPCIFN_DMAAS 0x0103 /* Invalid DMA addr space */
27 #define CLP_RC_SETPCIFN_RES 0x0104 /* Insufficient resources */
28 #define CLP_RC_SETPCIFN_ALRDY 0x0105 /* Fn already in requested state */
29 #define CLP_RC_SETPCIFN_ERR 0x0106 /* Fn in permanent error state */
30 #define CLP_RC_SETPCIFN_RECPND 0x0107 /* Error recovery pending */
31 #define CLP_RC_SETPCIFN_BUSY 0x0108 /* Fn busy */
32 #define CLP_RC_LISTPCI_BADRT 0x010a /* Resume token not recognized */
33 #define CLP_RC_QUERYPCIFG_PFGID 0x010b /* Unrecognized PFGID */
35 /* request or response block header length */
36 #define LIST_PCI_HDR_LEN 32
38 /* Number of function handles fitting in response block */
39 #define CLP_FH_LIST_NR_ENTRIES \
40 ((CLP_BLK_SIZE - 2 * LIST_PCI_HDR_LEN) \
41 / sizeof(struct clp_fh_list_entry))
43 #define CLP_SET_ENABLE_PCI_FN 0 /* Yes, 0 enables it */
44 #define CLP_SET_DISABLE_PCI_FN 1 /* Yes, 1 disables it */
46 #define CLP_UTIL_STR_LEN 64
47 #define CLP_PFIP_NR_SEGMENTS 4
49 extern bool zpci_unique_uid;
51 /* List PCI functions request */
52 struct clp_req_list_pci {
53 struct clp_req_hdr hdr;
58 /* List PCI functions response */
59 struct clp_rsp_list_pci {
60 struct clp_rsp_hdr hdr;
67 struct clp_fh_list_entry fh_list[CLP_FH_LIST_NR_ENTRIES];
70 /* Query PCI function request */
71 struct clp_req_query_pci {
72 struct clp_req_hdr hdr;
73 u32 fh; /* function handle */
78 /* Query PCI function response */
79 struct clp_rsp_query_pci {
80 struct clp_rsp_hdr hdr;
81 u16 vfn; /* virtual fn number */
83 u16 util_str_avail : 1; /* utility string available? */
84 u16 pfgid : 8; /* pci function group id */
85 u32 fid; /* pci function id */
86 u8 bar_size[PCI_BAR_COUNT];
88 __le32 bar[PCI_BAR_COUNT];
89 u8 pfip[CLP_PFIP_NR_SEGMENTS]; /* pci function internal path */
92 u8 pft; /* pci function type */
93 u64 sdma; /* start dma as */
94 u64 edma; /* end dma as */
96 u32 uid; /* user defined id */
97 u8 util_str[CLP_UTIL_STR_LEN]; /* utility string */
100 /* Query PCI function group request */
101 struct clp_req_query_pci_grp {
102 struct clp_req_hdr hdr;
104 u32 pfgid : 8; /* function group id */
109 /* Query PCI function group response */
110 struct clp_rsp_query_pci_grp {
111 struct clp_rsp_hdr hdr;
113 u16 noi : 12; /* number of interrupts */
117 u8 refresh : 1; /* TLB refresh mode */
121 u64 dasm; /* dma address space mask */
122 u64 msia; /* MSI address */
127 /* Set PCI function request */
128 struct clp_req_set_pci {
129 struct clp_req_hdr hdr;
130 u32 fh; /* function handle */
132 u8 oc; /* operation controls */
133 u8 ndas; /* number of dma spaces */
137 /* Set PCI function response */
138 struct clp_rsp_set_pci {
139 struct clp_rsp_hdr hdr;
140 u32 fh; /* function handle */
145 /* Combined request/response block structures used by clp insn */
146 struct clp_req_rsp_list_pci {
147 struct clp_req_list_pci request;
148 struct clp_rsp_list_pci response;
151 struct clp_req_rsp_set_pci {
152 struct clp_req_set_pci request;
153 struct clp_rsp_set_pci response;
156 struct clp_req_rsp_query_pci {
157 struct clp_req_query_pci request;
158 struct clp_rsp_query_pci response;
161 struct clp_req_rsp_query_pci_grp {
162 struct clp_req_query_pci_grp request;
163 struct clp_rsp_query_pci_grp response;