2 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
4 * Author: Tony Li <tony.li@freescale.com>
5 * Jason Jin <Jason.jin@freescale.com>
7 * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; version 2 of the
15 #include <linux/irq.h>
16 #include <linux/bootmem.h>
17 #include <linux/msi.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/of_platform.h>
21 #include <sysdev/fsl_soc.h>
23 #include <asm/hw_irq.h>
24 #include <asm/ppc-pci.h>
26 #include <asm/fsl_hcalls.h>
31 #define MSIIR_OFFSET_MASK 0xfffff
32 #define MSIIR_IBS_SHIFT 0
33 #define MSIIR_SRS_SHIFT 5
34 #define MSIIR1_IBS_SHIFT 4
35 #define MSIIR1_SRS_SHIFT 0
36 #define MSI_SRS_MASK 0xf
37 #define MSI_IBS_MASK 0x1f
39 #define msi_hwirq(msi, msir_index, intr_index) \
40 ((msir_index) << (msi)->srs_shift | \
41 ((intr_index) << (msi)->ibs_shift))
43 static LIST_HEAD(msi_head);
45 struct fsl_msi_feature {
47 u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
50 struct fsl_msi_cascade_data {
51 struct fsl_msi *msi_data;
55 static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
57 return in_be32(base + (reg >> 2));
61 * We do not need this actually. The MSIR register has been read once
62 * in the cascade interrupt. So, this MSI interrupt has been acked
64 static void fsl_msi_end_irq(struct irq_data *d)
68 static struct irq_chip fsl_msi_chip = {
69 .irq_mask = mask_msi_irq,
70 .irq_unmask = unmask_msi_irq,
71 .irq_ack = fsl_msi_end_irq,
75 static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
78 struct fsl_msi *msi_data = h->host_data;
79 struct irq_chip *chip = &fsl_msi_chip;
81 irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
83 irq_set_chip_data(virq, msi_data);
84 irq_set_chip_and_handler(virq, chip, handle_edge_irq);
89 static const struct irq_domain_ops fsl_msi_host_ops = {
90 .map = fsl_msi_host_map,
93 static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
97 rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX,
98 msi_data->irqhost->of_node);
103 * Reserve all the hwirqs
104 * The available hwirqs will be released in fsl_msi_setup_hwirq()
106 for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
107 msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
112 static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
114 if (type == PCI_CAP_ID_MSIX)
115 pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
120 static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
122 struct msi_desc *entry;
123 struct fsl_msi *msi_data;
124 irq_hw_number_t hwirq;
126 list_for_each_entry(entry, &pdev->msi_list, list) {
127 if (entry->irq == NO_IRQ)
129 hwirq = virq_to_hw(entry->irq);
130 msi_data = irq_get_chip_data(entry->irq);
131 irq_set_msi_desc(entry->irq, NULL);
132 irq_dispose_mapping(entry->irq);
133 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
139 static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
141 struct fsl_msi *fsl_msi_data)
143 struct fsl_msi *msi_data = fsl_msi_data;
144 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
145 u64 address; /* Physical address of the MSIIR */
149 /* If the msi-address-64 property exists, then use it */
150 reg = of_get_property(hose->dn, "msi-address-64", &len);
151 if (reg && (len == sizeof(u64)))
152 address = be64_to_cpup(reg);
154 address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
156 msg->address_lo = lower_32_bits(address);
157 msg->address_hi = upper_32_bits(address);
161 pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
162 (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
163 (hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
166 static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
168 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
169 struct device_node *np;
171 int rc, hwirq = -ENOMEM;
173 struct msi_desc *entry;
175 struct fsl_msi *msi_data;
178 * If the PCI node has an fsl,msi property, then we need to use it
179 * to find the specific MSI.
181 np = of_parse_phandle(hose->dn, "fsl,msi", 0);
183 if (of_device_is_compatible(np, "fsl,mpic-msi") ||
184 of_device_is_compatible(np, "fsl,vmpic-msi"))
185 phandle = np->phandle;
188 "node %s has an invalid fsl,msi phandle %u\n",
189 hose->dn->full_name, np->phandle);
194 list_for_each_entry(entry, &pdev->msi_list, list) {
196 * Loop over all the MSI devices until we find one that has an
197 * available interrupt.
199 list_for_each_entry(msi_data, &msi_head, list) {
201 * If the PCI node has an fsl,msi property, then we
202 * restrict our search to the corresponding MSI node.
203 * The simplest way is to skip over MSI nodes with the
204 * wrong phandle. Under the Freescale hypervisor, this
205 * has the additional benefit of skipping over MSI
206 * nodes that are not mapped in the PAMU.
208 if (phandle && (phandle != msi_data->phandle))
211 hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
218 dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
222 virq = irq_create_mapping(msi_data->irqhost, hwirq);
224 if (virq == NO_IRQ) {
225 dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
226 msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
230 /* chip_data is msi_data via host->hostdata in host->map() */
231 irq_set_msi_desc(virq, entry);
233 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
234 write_msi_msg(virq, &msg);
239 /* free by the caller of this function */
243 static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
245 struct irq_chip *chip = irq_desc_get_chip(desc);
246 struct irq_data *idata = irq_desc_get_irq_data(desc);
247 unsigned int cascade_irq;
248 struct fsl_msi *msi_data;
253 struct fsl_msi_cascade_data *cascade_data;
255 cascade_data = irq_get_handler_data(irq);
256 msi_data = cascade_data->msi_data;
258 raw_spin_lock(&desc->lock);
259 if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
260 if (chip->irq_mask_ack)
261 chip->irq_mask_ack(idata);
263 chip->irq_mask(idata);
264 chip->irq_ack(idata);
268 if (unlikely(irqd_irq_inprogress(idata)))
271 msir_index = cascade_data->index;
273 if (msir_index >= NR_MSI_REG_MAX)
274 cascade_irq = NO_IRQ;
276 irqd_set_chained_irq_inprogress(idata);
277 switch (msi_data->feature & FSL_PIC_IP_MASK) {
278 case FSL_PIC_IP_MPIC:
279 msir_value = fsl_msi_read(msi_data->msi_regs,
282 case FSL_PIC_IP_IPIC:
283 msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
285 #ifdef CONFIG_EPAPR_PARAVIRT
286 case FSL_PIC_IP_VMPIC: {
288 ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
290 pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
291 "irq %u (ret=%u)\n", irq, ret);
300 intr_index = ffs(msir_value) - 1;
302 cascade_irq = irq_linear_revmap(msi_data->irqhost,
303 msi_hwirq(msi_data, msir_index,
304 intr_index + have_shift));
305 if (cascade_irq != NO_IRQ)
306 generic_handle_irq(cascade_irq);
307 have_shift += intr_index + 1;
308 msir_value = msir_value >> (intr_index + 1);
310 irqd_clr_chained_irq_inprogress(idata);
312 switch (msi_data->feature & FSL_PIC_IP_MASK) {
313 case FSL_PIC_IP_MPIC:
314 case FSL_PIC_IP_VMPIC:
315 chip->irq_eoi(idata);
317 case FSL_PIC_IP_IPIC:
318 if (!irqd_irq_disabled(idata) && chip->irq_unmask)
319 chip->irq_unmask(idata);
323 raw_spin_unlock(&desc->lock);
326 static int fsl_of_msi_remove(struct platform_device *ofdev)
328 struct fsl_msi *msi = platform_get_drvdata(ofdev);
330 struct fsl_msi_cascade_data *cascade_data;
332 if (msi->list.prev != NULL)
333 list_del(&msi->list);
334 for (i = 0; i < NR_MSI_REG_MAX; i++) {
335 virq = msi->msi_virqs[i];
336 if (virq != NO_IRQ) {
337 cascade_data = irq_get_handler_data(virq);
339 irq_dispose_mapping(virq);
342 if (msi->bitmap.bitmap)
343 msi_bitmap_free(&msi->bitmap);
344 if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
345 iounmap(msi->msi_regs);
351 static struct lock_class_key fsl_msi_irq_class;
353 static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
354 int offset, int irq_index)
356 struct fsl_msi_cascade_data *cascade_data = NULL;
359 virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
360 if (virt_msir == NO_IRQ) {
361 dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
362 __func__, irq_index);
366 cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
368 dev_err(&dev->dev, "No memory for MSI cascade data\n");
371 irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
372 msi->msi_virqs[irq_index] = virt_msir;
373 cascade_data->index = offset;
374 cascade_data->msi_data = msi;
375 irq_set_handler_data(virt_msir, cascade_data);
376 irq_set_chained_handler(virt_msir, fsl_msi_cascade);
378 /* Release the hwirqs corresponding to this MSI register */
379 for (i = 0; i < IRQS_PER_MSI_REG; i++)
380 msi_bitmap_free_hwirqs(&msi->bitmap,
381 msi_hwirq(msi, offset, i), 1);
386 static const struct of_device_id fsl_of_msi_ids[];
387 static int fsl_of_msi_probe(struct platform_device *dev)
389 const struct of_device_id *match;
391 struct resource res, msiir;
392 int err, i, j, irq_index, count;
394 const struct fsl_msi_feature *features;
398 match = of_match_device(fsl_of_msi_ids, &dev->dev);
401 features = match->data;
403 printk(KERN_DEBUG "Setting up Freescale MSI support\n");
405 msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
407 dev_err(&dev->dev, "No memory for MSI structure\n");
410 platform_set_drvdata(dev, msi);
412 msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
413 NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi);
415 if (msi->irqhost == NULL) {
416 dev_err(&dev->dev, "No memory for MSI irqhost\n");
422 * Under the Freescale hypervisor, the msi nodes don't have a 'reg'
423 * property. Instead, we use hypercalls to access the MSI.
425 if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
426 err = of_address_to_resource(dev->dev.of_node, 0, &res);
428 dev_err(&dev->dev, "invalid resource for node %s\n",
429 dev->dev.of_node->full_name);
433 msi->msi_regs = ioremap(res.start, resource_size(&res));
434 if (!msi->msi_regs) {
436 dev_err(&dev->dev, "could not map node %s\n",
437 dev->dev.of_node->full_name);
441 features->msiir_offset + (res.start & 0xfffff);
444 * First read the MSIIR/MSIIR1 offset from dts
445 * On failure use the hardcode MSIIR offset
447 if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
448 msi->msiir_offset = features->msiir_offset +
449 (res.start & MSIIR_OFFSET_MASK);
451 msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
454 msi->feature = features->fsl_pic_ip;
457 * Remember the phandle, so that we can match with any PCI nodes
458 * that have an "fsl,msi" property.
460 msi->phandle = dev->dev.of_node->phandle;
462 err = fsl_msi_init_allocator(msi);
464 dev_err(&dev->dev, "Error allocating MSI bitmap\n");
468 p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
470 if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3")) {
471 msi->srs_shift = MSIIR1_SRS_SHIFT;
472 msi->ibs_shift = MSIIR1_IBS_SHIFT;
474 dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n",
477 for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1;
479 err = fsl_msi_setup_hwirq(msi, dev,
480 irq_index, irq_index);
485 static const u32 all_avail[] =
486 { 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };
488 msi->srs_shift = MSIIR_SRS_SHIFT;
489 msi->ibs_shift = MSIIR_IBS_SHIFT;
491 if (p && len % (2 * sizeof(u32)) != 0) {
492 dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
500 len = sizeof(all_avail);
503 for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
504 if (p[i * 2] % IRQS_PER_MSI_REG ||
505 p[i * 2 + 1] % IRQS_PER_MSI_REG) {
506 pr_warn("%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
507 __func__, dev->dev.of_node->full_name,
508 p[i * 2 + 1], p[i * 2]);
513 offset = p[i * 2] / IRQS_PER_MSI_REG;
514 count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
516 for (j = 0; j < count; j++, irq_index++) {
517 err = fsl_msi_setup_hwirq(msi, dev, offset + j,
525 list_add_tail(&msi->list, &msi_head);
527 /* The multiple setting ppc_md.setup_msi_irqs will not harm things */
528 if (!ppc_md.setup_msi_irqs) {
529 ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
530 ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
531 ppc_md.msi_check_device = fsl_msi_check_device;
532 } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
533 dev_err(&dev->dev, "Different MSI driver already installed!\n");
539 fsl_of_msi_remove(dev);
543 static const struct fsl_msi_feature mpic_msi_feature = {
544 .fsl_pic_ip = FSL_PIC_IP_MPIC,
545 .msiir_offset = 0x140,
548 static const struct fsl_msi_feature ipic_msi_feature = {
549 .fsl_pic_ip = FSL_PIC_IP_IPIC,
550 .msiir_offset = 0x38,
553 static const struct fsl_msi_feature vmpic_msi_feature = {
554 .fsl_pic_ip = FSL_PIC_IP_VMPIC,
558 static const struct of_device_id fsl_of_msi_ids[] = {
560 .compatible = "fsl,mpic-msi",
561 .data = &mpic_msi_feature,
564 .compatible = "fsl,mpic-msi-v4.3",
565 .data = &mpic_msi_feature,
568 .compatible = "fsl,ipic-msi",
569 .data = &ipic_msi_feature,
571 #ifdef CONFIG_EPAPR_PARAVIRT
573 .compatible = "fsl,vmpic-msi",
574 .data = &vmpic_msi_feature,
580 static struct platform_driver fsl_of_msi_driver = {
583 .owner = THIS_MODULE,
584 .of_match_table = fsl_of_msi_ids,
586 .probe = fsl_of_msi_probe,
587 .remove = fsl_of_msi_remove,
590 static __init int fsl_of_msi_init(void)
592 return platform_driver_register(&fsl_of_msi_driver);
595 subsys_initcall(fsl_of_msi_init);