arch/powerpc/platforms/powernv/pci-ioda.c

   1 /*
   2  * Support PCI/PCIe on PowerNV platforms
   3  *
   4  * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #undef DEBUG
  13
  14 #include <linux/kernel.h>
  15 #include <linux/pci.h>
  16 #include <linux/delay.h>
  17 #include <linux/string.h>
  18 #include <linux/init.h>
  19 #include <linux/bootmem.h>
  20 #include <linux/irq.h>
  21 #include <linux/io.h>
  22 #include <linux/msi.h>
  23
  24 #include <asm/sections.h>
  25 #include <asm/io.h>
  26 #include <asm/prom.h>
  27 #include <asm/pci-bridge.h>
  28 #include <asm/machdep.h>
  29 #include <asm/msi_bitmap.h>
  30 #include <asm/ppc-pci.h>
  31 #include <asm/opal.h>
  32 #include <asm/iommu.h>
  33 #include <asm/tce.h>
  34 #include <asm/xics.h>
  35
  36 #include "powernv.h"
  37 #include "pci.h"
  38
  39 #define define_pe_printk_level(func, kern_level)                \
  40 static int func(const struct pnv_ioda_pe *pe, const char *fmt, ...)     \
  41 {                                                               \
  42         struct va_format vaf;                                   \
  43         va_list args;                                           \
  44         char pfix[32];                                          \
  45         int r;                                                  \
  46                                                                 \
  47         va_start(args, fmt);                                    \
  48                                                                 \
  49         vaf.fmt = fmt;                                          \
  50         vaf.va = &args;                                         \
  51                                                                 \
  52         if (pe->pdev)                                           \
  53                 strlcpy(pfix, dev_name(&pe->pdev->dev),         \
  54                         sizeof(pfix));                          \
  55         else                                                    \
  56                 sprintf(pfix, "%04x:%02x     ",                 \
  57                         pci_domain_nr(pe->pbus),                \
  58                         pe->pbus->number);                      \
  59         r = printk(kern_level "pci %s: [PE# %.3d] %pV",         \
  60                    pfix, pe->pe_number, &vaf);                  \
  61                                                                 \
  62         va_end(args);                                           \
  63                                                                 \
  64         return r;                                               \
  65 }                                                               \
  66
  67 define_pe_printk_level(pe_err, KERN_ERR);
  68 define_pe_printk_level(pe_warn, KERN_WARNING);
  69 define_pe_printk_level(pe_info, KERN_INFO);
  70
  71 static int pnv_ioda_alloc_pe(struct pnv_phb *phb)
  72 {
  73         unsigned long pe;
  74
  75         do {
  76                 pe = find_next_zero_bit(phb->ioda.pe_alloc,
  77                                         phb->ioda.total_pe, 0);
  78                 if (pe >= phb->ioda.total_pe)
  79                         return IODA_INVALID_PE;
  80         } while(test_and_set_bit(pe, phb->ioda.pe_alloc));
  81
  82         phb->ioda.pe_array[pe].phb = phb;
  83         phb->ioda.pe_array[pe].pe_number = pe;
  84         return pe;
  85 }
  86
  87 static void pnv_ioda_free_pe(struct pnv_phb *phb, int pe)
  88 {
  89         WARN_ON(phb->ioda.pe_array[pe].pdev);
  90
  91         memset(&phb->ioda.pe_array[pe], 0, sizeof(struct pnv_ioda_pe));
  92         clear_bit(pe, phb->ioda.pe_alloc);
  93 }
  94
  95 /* Currently those 2 are only used when MSIs are enabled, this will change
  96  * but in the meantime, we need to protect them to avoid warnings
  97  */
  98 #ifdef CONFIG_PCI_MSI
  99 static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
 100 {
 101         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 102         struct pnv_phb *phb = hose->private_data;
 103         struct pci_dn *pdn = pci_get_pdn(dev);
 104
 105         if (!pdn)
 106                 return NULL;
 107         if (pdn->pe_number == IODA_INVALID_PE)
 108                 return NULL;
 109         return &phb->ioda.pe_array[pdn->pe_number];
 110 }
 111 #endif /* CONFIG_PCI_MSI */
 112
 113 static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe)
 114 {
 115         struct pci_dev *parent;
 116         uint8_t bcomp, dcomp, fcomp;
 117         long rc, rid_end, rid;
 118
 119         /* Bus validation ? */
 120         if (pe->pbus) {
 121                 int count;
 122
 123                 dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER;
 124                 fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER;
 125                 parent = pe->pbus->self;
 126                 if (pe->flags & PNV_IODA_PE_BUS_ALL)
 127                         count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1;
 128                 else
 129                         count = 1;
 130
 131                 switch(count) {
 132                 case  1: bcomp = OpalPciBusAll;         break;
 133                 case  2: bcomp = OpalPciBus7Bits;       break;
 134                 case  4: bcomp = OpalPciBus6Bits;       break;
 135                 case  8: bcomp = OpalPciBus5Bits;       break;
 136                 case 16: bcomp = OpalPciBus4Bits;       break;
 137                 case 32: bcomp = OpalPciBus3Bits;       break;
 138                 default:
 139                         pr_err("%s: Number of subordinate busses %d"
 140                                " unsupported\n",
 141                                pci_name(pe->pbus->self), count);
 142                         /* Do an exact match only */
 143                         bcomp = OpalPciBusAll;
 144                 }
 145                 rid_end = pe->rid + (count << 8);
 146         } else {
 147                 parent = pe->pdev->bus->self;
 148                 bcomp = OpalPciBusAll;
 149                 dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER;
 150                 fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER;
 151                 rid_end = pe->rid + 1;
 152         }
 153
 154         /*
 155          * Associate PE in PELT. We need add the PE into the
 156          * corresponding PELT-V as well. Otherwise, the error
 157          * originated from the PE might contribute to other
 158          * PEs.
 159          */
 160         rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid,
 161                              bcomp, dcomp, fcomp, OPAL_MAP_PE);
 162         if (rc) {
 163                 pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc);
 164                 return -ENXIO;
 165         }
 166
 167         rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number,
 168                                 pe->pe_number, OPAL_ADD_PE_TO_DOMAIN);
 169         if (rc)
 170                 pe_warn(pe, "OPAL error %d adding self to PELTV\n", rc);
 171         opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number,
 172                                   OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
 173
 174         /* Add to all parents PELT-V */
 175         while (parent) {
 176                 struct pci_dn *pdn = pci_get_pdn(parent);
 177                 if (pdn && pdn->pe_number != IODA_INVALID_PE) {
 178                         rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number,
 179                                                 pe->pe_number, OPAL_ADD_PE_TO_DOMAIN);
 180                         /* XXX What to do in case of error ? */
 181                 }
 182                 parent = parent->bus->self;
 183         }
 184         /* Setup reverse map */
 185         for (rid = pe->rid; rid < rid_end; rid++)
 186                 phb->ioda.pe_rmap[rid] = pe->pe_number;
 187
 188         /* Setup one MVTs on IODA1 */
 189         if (phb->type == PNV_PHB_IODA1) {
 190                 pe->mve_number = pe->pe_number;
 191                 rc = opal_pci_set_mve(phb->opal_id, pe->mve_number,
 192                                       pe->pe_number);
 193                 if (rc) {
 194                         pe_err(pe, "OPAL error %ld setting up MVE %d\n",
 195                                rc, pe->mve_number);
 196                         pe->mve_number = -1;
 197                 } else {
 198                         rc = opal_pci_set_mve_enable(phb->opal_id,
 199                                                      pe->mve_number, OPAL_ENABLE_MVE);
 200                         if (rc) {
 201                                 pe_err(pe, "OPAL error %ld enabling MVE %d\n",
 202                                        rc, pe->mve_number);
 203                                 pe->mve_number = -1;
 204                         }
 205                 }
 206         } else if (phb->type == PNV_PHB_IODA2)
 207                 pe->mve_number = 0;
 208
 209         return 0;
 210 }
 211
 212 static void pnv_ioda_link_pe_by_weight(struct pnv_phb *phb,
 213                                        struct pnv_ioda_pe *pe)
 214 {
 215         struct pnv_ioda_pe *lpe;
 216
 217         list_for_each_entry(lpe, &phb->ioda.pe_dma_list, dma_link) {
 218                 if (lpe->dma_weight < pe->dma_weight) {
 219                         list_add_tail(&pe->dma_link, &lpe->dma_link);
 220                         return;
 221                 }
 222         }
 223         list_add_tail(&pe->dma_link, &phb->ioda.pe_dma_list);
 224 }
 225
 226 static unsigned int pnv_ioda_dma_weight(struct pci_dev *dev)
 227 {
 228         /* This is quite simplistic. The "base" weight of a device
 229          * is 10. 0 means no DMA is to be accounted for it.
 230          */
 231
 232         /* If it's a bridge, no DMA */
 233         if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL)
 234                 return 0;
 235
 236         /* Reduce the weight of slow USB controllers */
 237         if (dev->class == PCI_CLASS_SERIAL_USB_UHCI ||
 238             dev->class == PCI_CLASS_SERIAL_USB_OHCI ||
 239             dev->class == PCI_CLASS_SERIAL_USB_EHCI)
 240                 return 3;
 241
 242         /* Increase the weight of RAID (includes Obsidian) */
 243         if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID)
 244                 return 15;
 245
 246         /* Default */
 247         return 10;
 248 }
 249
 250 #if 0
 251 static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev)
 252 {
 253         struct pci_controller *hose = pci_bus_to_host(dev->bus);
 254         struct pnv_phb *phb = hose->private_data;
 255         struct pci_dn *pdn = pci_get_pdn(dev);
 256         struct pnv_ioda_pe *pe;
 257         int pe_num;
 258
 259         if (!pdn) {
 260                 pr_err("%s: Device tree node not associated properly\n",
 261                            pci_name(dev));
 262                 return NULL;
 263         }
 264         if (pdn->pe_number != IODA_INVALID_PE)
 265                 return NULL;
 266
 267         /* PE#0 has been pre-set */
 268         if (dev->bus->number == 0)
 269                 pe_num = 0;
 270         else
 271                 pe_num = pnv_ioda_alloc_pe(phb);
 272         if (pe_num == IODA_INVALID_PE) {
 273                 pr_warning("%s: Not enough PE# available, disabling device\n",
 274                            pci_name(dev));
 275                 return NULL;
 276         }
 277
 278         /* NOTE: We get only one ref to the pci_dev for the pdn, not for the
 279          * pointer in the PE data structure, both should be destroyed at the
 280          * same time. However, this needs to be looked at more closely again
 281          * once we actually start removing things (Hotplug, SR-IOV, ...)
 282          *
 283          * At some point we want to remove the PDN completely anyways
 284          */
 285         pe = &phb->ioda.pe_array[pe_num];
 286         pci_dev_get(dev);
 287         pdn->pcidev = dev;
 288         pdn->pe_number = pe_num;
 289         pe->pdev = dev;
 290         pe->pbus = NULL;
 291         pe->tce32_seg = -1;
 292         pe->mve_number = -1;
 293         pe->rid = dev->bus->number << 8 | pdn->devfn;
 294
 295         pe_info(pe, "Associated device to PE\n");
 296
 297         if (pnv_ioda_configure_pe(phb, pe)) {
 298                 /* XXX What do we do here ? */
 299                 if (pe_num)
 300                         pnv_ioda_free_pe(phb, pe_num);
 301                 pdn->pe_number = IODA_INVALID_PE;
 302                 pe->pdev = NULL;
 303                 pci_dev_put(dev);
 304                 return NULL;
 305         }
 306
 307         /* Assign a DMA weight to the device */
 308         pe->dma_weight = pnv_ioda_dma_weight(dev);
 309         if (pe->dma_weight != 0) {
 310                 phb->ioda.dma_weight += pe->dma_weight;
 311                 phb->ioda.dma_pe_count++;
 312         }
 313
 314         /* Link the PE */
 315         pnv_ioda_link_pe_by_weight(phb, pe);
 316
 317         return pe;
 318 }
 319 #endif /* Useful for SRIOV case */
 320
 321 static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe)
 322 {
 323         struct pci_dev *dev;
 324
 325         list_for_each_entry(dev, &bus->devices, bus_list) {
 326                 struct pci_dn *pdn = pci_get_pdn(dev);
 327
 328                 if (pdn == NULL) {
 329                         pr_warn("%s: No device node associated with device !\n",
 330                                 pci_name(dev));
 331                         continue;
 332                 }
 333                 pci_dev_get(dev);
 334                 pdn->pcidev = dev;
 335                 pdn->pe_number = pe->pe_number;
 336                 pe->dma_weight += pnv_ioda_dma_weight(dev);
 337                 if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate)
 338                         pnv_ioda_setup_same_PE(dev->subordinate, pe);
 339         }
 340 }
 341
 342 /*
 343  * There're 2 types of PCI bus sensitive PEs: One that is compromised of
 344  * single PCI bus. Another one that contains the primary PCI bus and its
 345  * subordinate PCI devices and buses. The second type of PE is normally
 346  * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports.
 347  */
 348 static void pnv_ioda_setup_bus_PE(struct pci_bus *bus, int all)
 349 {
 350         struct pci_controller *hose = pci_bus_to_host(bus);
 351         struct pnv_phb *phb = hose->private_data;
 352         struct pnv_ioda_pe *pe;
 353         int pe_num;
 354
 355         pe_num = pnv_ioda_alloc_pe(phb);
 356         if (pe_num == IODA_INVALID_PE) {
 357                 pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n",
 358                         __func__, pci_domain_nr(bus), bus->number);
 359                 return;
 360         }
 361
 362         pe = &phb->ioda.pe_array[pe_num];
 363         pe->flags = (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS);
 364         pe->pbus = bus;
 365         pe->pdev = NULL;
 366         pe->tce32_seg = -1;
 367         pe->mve_number = -1;
 368         pe->rid = bus->busn_res.start << 8;
 369         pe->dma_weight = 0;
 370
 371         if (all)
 372                 pe_info(pe, "Secondary bus %d..%d associated with PE#%d\n",
 373                         bus->busn_res.start, bus->busn_res.end, pe_num);
 374         else
 375                 pe_info(pe, "Secondary bus %d associated with PE#%d\n",
 376                         bus->busn_res.start, pe_num);
 377
 378         if (pnv_ioda_configure_pe(phb, pe)) {
 379                 /* XXX What do we do here ? */
 380                 if (pe_num)
 381                         pnv_ioda_free_pe(phb, pe_num);
 382                 pe->pbus = NULL;
 383                 return;
 384         }
 385
 386         /* Associate it with all child devices */
 387         pnv_ioda_setup_same_PE(bus, pe);
 388
 389         /* Put PE to the list */
 390         list_add_tail(&pe->list, &phb->ioda.pe_list);
 391
 392         /* Account for one DMA PE if at least one DMA capable device exist
 393          * below the bridge
 394          */
 395         if (pe->dma_weight != 0) {
 396                 phb->ioda.dma_weight += pe->dma_weight;
 397                 phb->ioda.dma_pe_count++;
 398         }
 399
 400         /* Link the PE */
 401         pnv_ioda_link_pe_by_weight(phb, pe);
 402 }
 403
 404 static void pnv_ioda_setup_PEs(struct pci_bus *bus)
 405 {
 406         struct pci_dev *dev;
 407
 408         pnv_ioda_setup_bus_PE(bus, 0);
 409
 410         list_for_each_entry(dev, &bus->devices, bus_list) {
 411                 if (dev->subordinate) {
 412                         if (pci_pcie_type(dev) == PCI_EXP_TYPE_PCI_BRIDGE)
 413                                 pnv_ioda_setup_bus_PE(dev->subordinate, 1);
 414                         else
 415                                 pnv_ioda_setup_PEs(dev->subordinate);
 416                 }
 417         }
 418 }
 419
 420 /*
 421  * Configure PEs so that the downstream PCI buses and devices
 422  * could have their associated PE#. Unfortunately, we didn't
 423  * figure out the way to identify the PLX bridge yet. So we
 424  * simply put the PCI bus and the subordinate behind the root
 425  * port to PE# here. The game rule here is expected to be changed
 426  * as soon as we can detected PLX bridge correctly.
 427  */
 428 static void pnv_pci_ioda_setup_PEs(void)
 429 {
 430         struct pci_controller *hose, *tmp;
 431
 432         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 433                 pnv_ioda_setup_PEs(hose->bus);
 434         }
 435 }
 436
 437 static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev)
 438 {
 439         struct pci_dn *pdn = pci_get_pdn(pdev);
 440         struct pnv_ioda_pe *pe;
 441
 442         /*
 443          * The function can be called while the PE#
 444          * hasn't been assigned. Do nothing for the
 445          * case.
 446          */
 447         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
 448                 return;
 449
 450         pe = &phb->ioda.pe_array[pdn->pe_number];
 451         set_iommu_table_base(&pdev->dev, &pe->tce32_table);
 452 }
 453
 454 static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, struct pci_bus *bus)
 455 {
 456         struct pci_dev *dev;
 457
 458         list_for_each_entry(dev, &bus->devices, bus_list) {
 459                 set_iommu_table_base(&dev->dev, &pe->tce32_table);
 460                 if (dev->subordinate)
 461                         pnv_ioda_setup_bus_dma(pe, dev->subordinate);
 462         }
 463 }
 464
 465 static void pnv_pci_ioda1_tce_invalidate(struct iommu_table *tbl,
 466                                          u64 *startp, u64 *endp)
 467 {
 468         u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
 469         unsigned long start, end, inc;
 470
 471         start = __pa(startp);
 472         end = __pa(endp);
 473
 474         /* BML uses this case for p6/p7/galaxy2: Shift addr and put in node */
 475         if (tbl->it_busno) {
 476                 start <<= 12;
 477                 end <<= 12;
 478                 inc = 128 << 12;
 479                 start |= tbl->it_busno;
 480                 end |= tbl->it_busno;
 481         } else if (tbl->it_type & TCE_PCI_SWINV_PAIR) {
 482                 /* p7ioc-style invalidation, 2 TCEs per write */
 483                 start |= (1ull << 63);
 484                 end |= (1ull << 63);
 485                 inc = 16;
 486         } else {
 487                 /* Default (older HW) */
 488                 inc = 128;
 489         }
 490
 491         end |= inc - 1; /* round up end to be different than start */
 492
 493         mb(); /* Ensure above stores are visible */
 494         while (start <= end) {
 495                 __raw_writeq(start, invalidate);
 496                 start += inc;
 497         }
 498
 499         /*
 500          * The iommu layer will do another mb() for us on build()
 501          * and we don't care on free()
 502          */
 503 }
 504
 505 static void pnv_pci_ioda2_tce_invalidate(struct pnv_ioda_pe *pe,
 506                                          struct iommu_table *tbl,
 507                                          u64 *startp, u64 *endp)
 508 {
 509         unsigned long start, end, inc;
 510         u64 __iomem *invalidate = (u64 __iomem *)tbl->it_index;
 511
 512         /* We'll invalidate DMA address in PE scope */
 513         start = 0x2ul << 60;
 514         start |= (pe->pe_number & 0xFF);
 515         end = start;
 516
 517         /* Figure out the start, end and step */
 518         inc = tbl->it_offset + (((u64)startp - tbl->it_base) / sizeof(u64));
 519         start |= (inc << 12);
 520         inc = tbl->it_offset + (((u64)endp - tbl->it_base) / sizeof(u64));
 521         end |= (inc << 12);
 522         inc = (0x1ul << 12);
 523         mb();
 524
 525         while (start <= end) {
 526                 __raw_writeq(start, invalidate);
 527                 start += inc;
 528         }
 529 }
 530
 531 void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
 532                                  u64 *startp, u64 *endp)
 533 {
 534         struct pnv_ioda_pe *pe = container_of(tbl, struct pnv_ioda_pe,
 535                                               tce32_table);
 536         struct pnv_phb *phb = pe->phb;
 537
 538         if (phb->type == PNV_PHB_IODA1)
 539                 pnv_pci_ioda1_tce_invalidate(tbl, startp, endp);
 540         else
 541                 pnv_pci_ioda2_tce_invalidate(pe, tbl, startp, endp);
 542 }
 543
 544 static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
 545                                       struct pnv_ioda_pe *pe, unsigned int base,
 546                                       unsigned int segs)
 547 {
 548
 549         struct page *tce_mem = NULL;
 550         const __be64 *swinvp;
 551         struct iommu_table *tbl;
 552         unsigned int i;
 553         int64_t rc;
 554         void *addr;
 555
 556         /* 256M DMA window, 4K TCE pages, 8 bytes TCE */
 557 #define TCE32_TABLE_SIZE        ((0x10000000 / 0x1000) * 8)
 558
 559         /* XXX FIXME: Handle 64-bit only DMA devices */
 560         /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */
 561         /* XXX FIXME: Allocate multi-level tables on PHB3 */
 562
 563         /* We shouldn't already have a 32-bit DMA associated */
 564         if (WARN_ON(pe->tce32_seg >= 0))
 565                 return;
 566
 567         /* Grab a 32-bit TCE table */
 568         pe->tce32_seg = base;
 569         pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n",
 570                 (base << 28), ((base + segs) << 28) - 1);
 571
 572         /* XXX Currently, we allocate one big contiguous table for the
 573          * TCEs. We only really need one chunk per 256M of TCE space
 574          * (ie per segment) but that's an optimization for later, it
 575          * requires some added smarts with our get/put_tce implementation
 576          */
 577         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
 578                                    get_order(TCE32_TABLE_SIZE * segs));
 579         if (!tce_mem) {
 580                 pe_err(pe, " Failed to allocate a 32-bit TCE memory\n");
 581                 goto fail;
 582         }
 583         addr = page_address(tce_mem);
 584         memset(addr, 0, TCE32_TABLE_SIZE * segs);
 585
 586         /* Configure HW */
 587         for (i = 0; i < segs; i++) {
 588                 rc = opal_pci_map_pe_dma_window(phb->opal_id,
 589                                               pe->pe_number,
 590                                               base + i, 1,
 591                                               __pa(addr) + TCE32_TABLE_SIZE * i,
 592                                               TCE32_TABLE_SIZE, 0x1000);
 593                 if (rc) {
 594                         pe_err(pe, " Failed to configure 32-bit TCE table,"
 595                                " err %ld\n", rc);
 596                         goto fail;
 597                 }
 598         }
 599
 600         /* Setup linux iommu table */
 601         tbl = &pe->tce32_table;
 602         pnv_pci_setup_iommu_table(tbl, addr, TCE32_TABLE_SIZE * segs,
 603                                   base << 28);
 604
 605         /* OPAL variant of P7IOC SW invalidated TCEs */
 606         swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
 607         if (swinvp) {
 608                 /* We need a couple more fields -- an address and a data
 609                  * to or.  Since the bus is only printed out on table free
 610                  * errors, and on the first pass the data will be a relative
 611                  * bus number, print that out instead.
 612                  */
 613                 tbl->it_busno = 0;
 614                 tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
 615                 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE |
 616                                TCE_PCI_SWINV_PAIR;
 617         }
 618         iommu_init_table(tbl, phb->hose->node);
 619
 620         if (pe->pdev)
 621                 set_iommu_table_base(&pe->pdev->dev, tbl);
 622         else
 623                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
 624
 625         return;
 626  fail:
 627         /* XXX Failure: Try to fallback to 64-bit only ? */
 628         if (pe->tce32_seg >= 0)
 629                 pe->tce32_seg = -1;
 630         if (tce_mem)
 631                 __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
 632 }
 633
 634 static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
 635                                        struct pnv_ioda_pe *pe)
 636 {
 637         struct page *tce_mem = NULL;
 638         void *addr;
 639         const __be64 *swinvp;
 640         struct iommu_table *tbl;
 641         unsigned int tce_table_size, end;
 642         int64_t rc;
 643
 644         /* We shouldn't already have a 32-bit DMA associated */
 645         if (WARN_ON(pe->tce32_seg >= 0))
 646                 return;
 647
 648         /* The PE will reserve all possible 32-bits space */
 649         pe->tce32_seg = 0;
 650         end = (1 << ilog2(phb->ioda.m32_pci_base));
 651         tce_table_size = (end / 0x1000) * 8;
 652         pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
 653                 end);
 654
 655         /* Allocate TCE table */
 656         tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL,
 657                                    get_order(tce_table_size));
 658         if (!tce_mem) {
 659                 pe_err(pe, "Failed to allocate a 32-bit TCE memory\n");
 660                 goto fail;
 661         }
 662         addr = page_address(tce_mem);
 663         memset(addr, 0, tce_table_size);
 664
 665         /*
 666          * Map TCE table through TVT. The TVE index is the PE number
 667          * shifted by 1 bit for 32-bits DMA space.
 668          */
 669         rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
 670                                         pe->pe_number << 1, 1, __pa(addr),
 671                                         tce_table_size, 0x1000);
 672         if (rc) {
 673                 pe_err(pe, "Failed to configure 32-bit TCE table,"
 674                        " err %ld\n", rc);
 675                 goto fail;
 676         }
 677
 678         /* Setup linux iommu table */
 679         tbl = &pe->tce32_table;
 680         pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0);
 681
 682         /* OPAL variant of PHB3 invalidated TCEs */
 683         swinvp = of_get_property(phb->hose->dn, "ibm,opal-tce-kill", NULL);
 684         if (swinvp) {
 685                 /* We need a couple more fields -- an address and a data
 686                  * to or.  Since the bus is only printed out on table free
 687                  * errors, and on the first pass the data will be a relative
 688                  * bus number, print that out instead.
 689                  */
 690                 tbl->it_busno = 0;
 691                 tbl->it_index = (unsigned long)ioremap(be64_to_cpup(swinvp), 8);
 692                 tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
 693         }
 694         iommu_init_table(tbl, phb->hose->node);
 695
 696         if (pe->pdev)
 697                 set_iommu_table_base(&pe->pdev->dev, tbl);
 698         else
 699                 pnv_ioda_setup_bus_dma(pe, pe->pbus);
 700
 701         return;
 702 fail:
 703         if (pe->tce32_seg >= 0)
 704                 pe->tce32_seg = -1;
 705         if (tce_mem)
 706                 __free_pages(tce_mem, get_order(tce_table_size));
 707 }
 708
 709 static void pnv_ioda_setup_dma(struct pnv_phb *phb)
 710 {
 711         struct pci_controller *hose = phb->hose;
 712         unsigned int residual, remaining, segs, tw, base;
 713         struct pnv_ioda_pe *pe;
 714
 715         /* If we have more PE# than segments available, hand out one
 716          * per PE until we run out and let the rest fail. If not,
 717          * then we assign at least one segment per PE, plus more based
 718          * on the amount of devices under that PE
 719          */
 720         if (phb->ioda.dma_pe_count > phb->ioda.tce32_count)
 721                 residual = 0;
 722         else
 723                 residual = phb->ioda.tce32_count -
 724                         phb->ioda.dma_pe_count;
 725
 726         pr_info("PCI: Domain %04x has %ld available 32-bit DMA segments\n",
 727                 hose->global_number, phb->ioda.tce32_count);
 728         pr_info("PCI: %d PE# for a total weight of %d\n",
 729                 phb->ioda.dma_pe_count, phb->ioda.dma_weight);
 730
 731         /* Walk our PE list and configure their DMA segments, hand them
 732          * out one base segment plus any residual segments based on
 733          * weight
 734          */
 735         remaining = phb->ioda.tce32_count;
 736         tw = phb->ioda.dma_weight;
 737         base = 0;
 738         list_for_each_entry(pe, &phb->ioda.pe_dma_list, dma_link) {
 739                 if (!pe->dma_weight)
 740                         continue;
 741                 if (!remaining) {
 742                         pe_warn(pe, "No DMA32 resources available\n");
 743                         continue;
 744                 }
 745                 segs = 1;
 746                 if (residual) {
 747                         segs += ((pe->dma_weight * residual)  + (tw / 2)) / tw;
 748                         if (segs > remaining)
 749                                 segs = remaining;
 750                 }
 751
 752                 /*
 753                  * For IODA2 compliant PHB3, we needn't care about the weight.
 754                  * The all available 32-bits DMA space will be assigned to
 755                  * the specific PE.
 756                  */
 757                 if (phb->type == PNV_PHB_IODA1) {
 758                         pe_info(pe, "DMA weight %d, assigned %d DMA32 segments\n",
 759                                 pe->dma_weight, segs);
 760                         pnv_pci_ioda_setup_dma_pe(phb, pe, base, segs);
 761                 } else {
 762                         pe_info(pe, "Assign DMA32 space\n");
 763                         segs = 0;
 764                         pnv_pci_ioda2_setup_dma_pe(phb, pe);
 765                 }
 766
 767                 remaining -= segs;
 768                 base += segs;
 769         }
 770 }
 771
 772 #ifdef CONFIG_PCI_MSI
 773 static void pnv_ioda2_msi_eoi(struct irq_data *d)
 774 {
 775         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 776         struct irq_chip *chip = irq_data_get_irq_chip(d);
 777         struct pnv_phb *phb = container_of(chip, struct pnv_phb,
 778                                            ioda.irq_chip);
 779         int64_t rc;
 780
 781         rc = opal_pci_msi_eoi(phb->opal_id, hw_irq);
 782         WARN_ON_ONCE(rc);
 783
 784         icp_native_eoi(d);
 785 }
 786
 787 static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
 788                                   unsigned int hwirq, unsigned int virq,
 789                                   unsigned int is_64, struct msi_msg *msg)
 790 {
 791         struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev);
 792         struct pci_dn *pdn = pci_get_pdn(dev);
 793         struct irq_data *idata;
 794         struct irq_chip *ichip;
 795         unsigned int xive_num = hwirq - phb->msi_base;
 796         uint64_t addr64;
 797         uint32_t addr32, data;
 798         int rc;
 799
 800         /* No PE assigned ? bail out ... no MSI for you ! */
 801         if (pe == NULL)
 802                 return -ENXIO;
 803
 804         /* Check if we have an MVE */
 805         if (pe->mve_number < 0)
 806                 return -ENXIO;
 807
 808         /* Force 32-bit MSI on some broken devices */
 809         if (pdn && pdn->force_32bit_msi)
 810                 is_64 = 0;
 811
 812         /* Assign XIVE to PE */
 813         rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
 814         if (rc) {
 815                 pr_warn("%s: OPAL error %d setting XIVE %d PE\n",
 816                         pci_name(dev), rc, xive_num);
 817                 return -EIO;
 818         }
 819
 820         if (is_64) {
 821                 rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1,
 822                                      &addr64, &data);
 823                 if (rc) {
 824                         pr_warn("%s: OPAL error %d getting 64-bit MSI data\n",
 825                                 pci_name(dev), rc);
 826                         return -EIO;
 827                 }
 828                 msg->address_hi = addr64 >> 32;
 829                 msg->address_lo = addr64 & 0xfffffffful;
 830         } else {
 831                 rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1,
 832                                      &addr32, &data);
 833                 if (rc) {
 834                         pr_warn("%s: OPAL error %d getting 32-bit MSI data\n",
 835                                 pci_name(dev), rc);
 836                         return -EIO;
 837                 }
 838                 msg->address_hi = 0;
 839                 msg->address_lo = addr32;
 840         }
 841         msg->data = data;
 842
 843         /*
 844          * Change the IRQ chip for the MSI interrupts on PHB3.
 845          * The corresponding IRQ chip should be populated for
 846          * the first time.
 847          */
 848         if (phb->type == PNV_PHB_IODA2) {
 849                 if (!phb->ioda.irq_chip_init) {
 850                         idata = irq_get_irq_data(virq);
 851                         ichip = irq_data_get_irq_chip(idata);
 852                         phb->ioda.irq_chip_init = 1;
 853                         phb->ioda.irq_chip = *ichip;
 854                         phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi;
 855                 }
 856
 857                 irq_set_chip(virq, &phb->ioda.irq_chip);
 858         }
 859
 860         pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
 861                  " address=%x_%08x data=%x PE# %d\n",
 862                  pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num,
 863                  msg->address_hi, msg->address_lo, data, pe->pe_number);
 864
 865         return 0;
 866 }
 867
 868 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb)
 869 {
 870         unsigned int count;
 871         const __be32 *prop = of_get_property(phb->hose->dn,
 872                                              "ibm,opal-msi-ranges", NULL);
 873         if (!prop) {
 874                 /* BML Fallback */
 875                 prop = of_get_property(phb->hose->dn, "msi-ranges", NULL);
 876         }
 877         if (!prop)
 878                 return;
 879
 880         phb->msi_base = be32_to_cpup(prop);
 881         count = be32_to_cpup(prop + 1);
 882         if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) {
 883                 pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
 884                        phb->hose->global_number);
 885                 return;
 886         }
 887
 888         phb->msi_setup = pnv_pci_ioda_msi_setup;
 889         phb->msi32_support = 1;
 890         pr_info("  Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
 891                 count, phb->msi_base);
 892 }
 893 #else
 894 static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { }
 895 #endif /* CONFIG_PCI_MSI */
 896
 897 /*
 898  * This function is supposed to be called on basis of PE from top
 899  * to bottom style. So the the I/O or MMIO segment assigned to
 900  * parent PE could be overrided by its child PEs if necessary.
 901  */
 902 static void pnv_ioda_setup_pe_seg(struct pci_controller *hose,
 903                                   struct pnv_ioda_pe *pe)
 904 {
 905         struct pnv_phb *phb = hose->private_data;
 906         struct pci_bus_region region;
 907         struct resource *res;
 908         int i, index;
 909         int rc;
 910
 911         /*
 912          * NOTE: We only care PCI bus based PE for now. For PCI
 913          * device based PE, for example SRIOV sensitive VF should
 914          * be figured out later.
 915          */
 916         BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)));
 917
 918         pci_bus_for_each_resource(pe->pbus, res, i) {
 919                 if (!res || !res->flags ||
 920                     res->start > res->end)
 921                         continue;
 922
 923                 if (res->flags & IORESOURCE_IO) {
 924                         region.start = res->start - phb->ioda.io_pci_base;
 925                         region.end   = res->end - phb->ioda.io_pci_base;
 926                         index = region.start / phb->ioda.io_segsize;
 927
 928                         while (index < phb->ioda.total_pe &&
 929                                region.start <= region.end) {
 930                                 phb->ioda.io_segmap[index] = pe->pe_number;
 931                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 932                                         pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index);
 933                                 if (rc != OPAL_SUCCESS) {
 934                                         pr_err("%s: OPAL error %d when mapping IO "
 935                                                "segment #%d to PE#%d\n",
 936                                                __func__, rc, index, pe->pe_number);
 937                                         break;
 938                                 }
 939
 940                                 region.start += phb->ioda.io_segsize;
 941                                 index++;
 942                         }
 943                 } else if (res->flags & IORESOURCE_MEM) {
 944                         /* WARNING: Assumes M32 is mem region 0 in PHB. We need to
 945                          * harden that algorithm when we start supporting M64
 946                          */
 947                         region.start = res->start -
 948                                        hose->mem_offset[0] -
 949                                        phb->ioda.m32_pci_base;
 950                         region.end   = res->end -
 951                                        hose->mem_offset[0] -
 952                                        phb->ioda.m32_pci_base;
 953                         index = region.start / phb->ioda.m32_segsize;
 954
 955                         while (index < phb->ioda.total_pe &&
 956                                region.start <= region.end) {
 957                                 phb->ioda.m32_segmap[index] = pe->pe_number;
 958                                 rc = opal_pci_map_pe_mmio_window(phb->opal_id,
 959                                         pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index);
 960                                 if (rc != OPAL_SUCCESS) {
 961                                         pr_err("%s: OPAL error %d when mapping M32 "
 962                                                "segment#%d to PE#%d",
 963                                                __func__, rc, index, pe->pe_number);
 964                                         break;
 965                                 }
 966
 967                                 region.start += phb->ioda.m32_segsize;
 968                                 index++;
 969                         }
 970                 }
 971         }
 972 }
 973
 974 static void pnv_pci_ioda_setup_seg(void)
 975 {
 976         struct pci_controller *tmp, *hose;
 977         struct pnv_phb *phb;
 978         struct pnv_ioda_pe *pe;
 979
 980         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 981                 phb = hose->private_data;
 982                 list_for_each_entry(pe, &phb->ioda.pe_list, list) {
 983                         pnv_ioda_setup_pe_seg(hose, pe);
 984                 }
 985         }
 986 }
 987
 988 static void pnv_pci_ioda_setup_DMA(void)
 989 {
 990         struct pci_controller *hose, *tmp;
 991         struct pnv_phb *phb;
 992
 993         list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
 994                 pnv_ioda_setup_dma(hose->private_data);
 995
 996                 /* Mark the PHB initialization done */
 997                 phb = hose->private_data;
 998                 phb->initialized = 1;
 999         }
1000 }
1001
1002 static void pnv_pci_ioda_fixup(void)
1003 {
1004         pnv_pci_ioda_setup_PEs();
1005         pnv_pci_ioda_setup_seg();
1006         pnv_pci_ioda_setup_DMA();
1007 }
1008
1009 /*
1010  * Returns the alignment for I/O or memory windows for P2P
1011  * bridges. That actually depends on how PEs are segmented.
1012  * For now, we return I/O or M32 segment size for PE sensitive
1013  * P2P bridges. Otherwise, the default values (4KiB for I/O,
1014  * 1MiB for memory) will be returned.
1015  *
1016  * The current PCI bus might be put into one PE, which was
1017  * create against the parent PCI bridge. For that case, we
1018  * needn't enlarge the alignment so that we can save some
1019  * resources.
1020  */
1021 static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus,
1022                                                 unsigned long type)
1023 {
1024         struct pci_dev *bridge;
1025         struct pci_controller *hose = pci_bus_to_host(bus);
1026         struct pnv_phb *phb = hose->private_data;
1027         int num_pci_bridges = 0;
1028
1029         bridge = bus->self;
1030         while (bridge) {
1031                 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) {
1032                         num_pci_bridges++;
1033                         if (num_pci_bridges >= 2)
1034                                 return 1;
1035                 }
1036
1037                 bridge = bridge->bus->self;
1038         }
1039
1040         /* We need support prefetchable memory window later */
1041         if (type & IORESOURCE_MEM)
1042                 return phb->ioda.m32_segsize;
1043
1044         return phb->ioda.io_segsize;
1045 }
1046
1047 /* Prevent enabling devices for which we couldn't properly
1048  * assign a PE
1049  */
1050 static int pnv_pci_enable_device_hook(struct pci_dev *dev)
1051 {
1052         struct pci_controller *hose = pci_bus_to_host(dev->bus);
1053         struct pnv_phb *phb = hose->private_data;
1054         struct pci_dn *pdn;
1055
1056         /* The function is probably called while the PEs have
1057          * not be created yet. For example, resource reassignment
1058          * during PCI probe period. We just skip the check if
1059          * PEs isn't ready.
1060          */
1061         if (!phb->initialized)
1062                 return 0;
1063
1064         pdn = pci_get_pdn(dev);
1065         if (!pdn || pdn->pe_number == IODA_INVALID_PE)
1066                 return -EINVAL;
1067
1068         return 0;
1069 }
1070
1071 static u32 pnv_ioda_bdfn_to_pe(struct pnv_phb *phb, struct pci_bus *bus,
1072                                u32 devfn)
1073 {
1074         return phb->ioda.pe_rmap[(bus->number << 8) | devfn];
1075 }
1076
1077 static void pnv_pci_ioda_shutdown(struct pnv_phb *phb)
1078 {
1079         opal_pci_reset(phb->opal_id, OPAL_PCI_IODA_TABLE_RESET,
1080                        OPAL_ASSERT_RESET);
1081 }
1082
1083 void __init pnv_pci_init_ioda_phb(struct device_node *np, int ioda_type)
1084 {
1085         struct pci_controller *hose;
1086         static int primary = 1;
1087         struct pnv_phb *phb;
1088         unsigned long size, m32map_off, iomap_off, pemap_off;
1089         const u64 *prop64;
1090         const u32 *prop32;
1091         u64 phb_id;
1092         void *aux;
1093         long rc;
1094
1095         pr_info(" Initializing IODA%d OPAL PHB %s\n", ioda_type, np->full_name);
1096
1097         prop64 = of_get_property(np, "ibm,opal-phbid", NULL);
1098         if (!prop64) {
1099                 pr_err("  Missing \"ibm,opal-phbid\" property !\n");
1100                 return;
1101         }
1102         phb_id = be64_to_cpup(prop64);
1103         pr_debug("  PHB-ID  : 0x%016llx\n", phb_id);
1104
1105         phb = alloc_bootmem(sizeof(struct pnv_phb));
1106         if (phb) {
1107                 memset(phb, 0, sizeof(struct pnv_phb));
1108                 phb->hose = hose = pcibios_alloc_controller(np);
1109         }
1110         if (!phb || !phb->hose) {
1111                 pr_err("PCI: Failed to allocate PCI controller for %s\n",
1112                        np->full_name);
1113                 return;
1114         }
1115
1116         spin_lock_init(&phb->lock);
1117         /* XXX Use device-tree */
1118         hose->first_busno = 0;
1119         hose->last_busno = 0xff;
1120         hose->private_data = phb;
1121         phb->opal_id = phb_id;
1122         phb->type = ioda_type;
1123
1124         /* Detect specific models for error handling */
1125         if (of_device_is_compatible(np, "ibm,p7ioc-pciex"))
1126                 phb->model = PNV_PHB_MODEL_P7IOC;
1127         else if (of_device_is_compatible(np, "ibm,power8-pciex"))
1128                 phb->model = PNV_PHB_MODEL_PHB3;
1129         else
1130                 phb->model = PNV_PHB_MODEL_UNKNOWN;
1131
1132         /* Parse 32-bit and IO ranges (if any) */
1133         pci_process_bridge_OF_ranges(phb->hose, np, primary);
1134         primary = 0;
1135
1136         /* Get registers */
1137         phb->regs = of_iomap(np, 0);
1138         if (phb->regs == NULL)
1139                 pr_err("  Failed to map registers !\n");
1140
1141         /* Initialize more IODA stuff */
1142         prop32 = of_get_property(np, "ibm,opal-num-pes", NULL);
1143         if (!prop32)
1144                 phb->ioda.total_pe = 1;
1145         else
1146                 phb->ioda.total_pe = *prop32;
1147
1148         phb->ioda.m32_size = resource_size(&hose->mem_resources[0]);
1149         /* FW Has already off top 64k of M32 space (MSI space) */
1150         phb->ioda.m32_size += 0x10000;
1151
1152         phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe;
1153         phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0];
1154         phb->ioda.io_size = hose->pci_io_size;
1155         phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe;
1156         phb->ioda.io_pci_base = 0; /* XXX calculate this ? */
1157
1158         /* Allocate aux data & arrays
1159          *
1160          * XXX TODO: Don't allocate io segmap on PHB3
1161          */
1162         size = _ALIGN_UP(phb->ioda.total_pe / 8, sizeof(unsigned long));
1163         m32map_off = size;
1164         size += phb->ioda.total_pe * sizeof(phb->ioda.m32_segmap[0]);
1165         iomap_off = size;
1166         size += phb->ioda.total_pe * sizeof(phb->ioda.io_segmap[0]);
1167         pemap_off = size;
1168         size += phb->ioda.total_pe * sizeof(struct pnv_ioda_pe);
1169         aux = alloc_bootmem(size);
1170         memset(aux, 0, size);
1171         phb->ioda.pe_alloc = aux;
1172         phb->ioda.m32_segmap = aux + m32map_off;
1173         phb->ioda.io_segmap = aux + iomap_off;
1174         phb->ioda.pe_array = aux + pemap_off;
1175         set_bit(0, phb->ioda.pe_alloc);
1176
1177         INIT_LIST_HEAD(&phb->ioda.pe_dma_list);
1178         INIT_LIST_HEAD(&phb->ioda.pe_list);
1179
1180         /* Calculate how many 32-bit TCE segments we have */
1181         phb->ioda.tce32_count = phb->ioda.m32_pci_base >> 28;
1182
1183         /* Clear unusable m64 */
1184         hose->mem_resources[1].flags = 0;
1185         hose->mem_resources[1].start = 0;
1186         hose->mem_resources[1].end = 0;
1187         hose->mem_resources[2].flags = 0;
1188         hose->mem_resources[2].start = 0;
1189         hose->mem_resources[2].end = 0;
1190
1191 #if 0 /* We should really do that ... */
1192         rc = opal_pci_set_phb_mem_window(opal->phb_id,
1193                                          window_type,
1194                                          window_num,
1195                                          starting_real_address,
1196                                          starting_pci_address,
1197                                          segment_size);
1198 #endif
1199
1200         pr_info("  %d PE's M32: 0x%x [segment=0x%x] IO: 0x%x [segment=0x%x]\n",
1201                 phb->ioda.total_pe,
1202                 phb->ioda.m32_size, phb->ioda.m32_segsize,
1203                 phb->ioda.io_size, phb->ioda.io_segsize);
1204
1205         phb->hose->ops = &pnv_pci_ops;
1206
1207         /* Setup RID -> PE mapping function */
1208         phb->bdfn_to_pe = pnv_ioda_bdfn_to_pe;
1209
1210         /* Setup TCEs */
1211         phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup;
1212
1213         /* Setup shutdown function for kexec */
1214         phb->shutdown = pnv_pci_ioda_shutdown;
1215
1216         /* Setup MSI support */
1217         pnv_pci_init_ioda_msis(phb);
1218
1219         /*
1220          * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here
1221          * to let the PCI core do resource assignment. It's supposed
1222          * that the PCI core will do correct I/O and MMIO alignment
1223          * for the P2P bridge bars so that each PCI bus (excluding
1224          * the child P2P bridges) can form individual PE.
1225          */
1226         ppc_md.pcibios_fixup = pnv_pci_ioda_fixup;
1227         ppc_md.pcibios_enable_device_hook = pnv_pci_enable_device_hook;
1228         ppc_md.pcibios_window_alignment = pnv_pci_window_alignment;
1229         pci_add_flags(PCI_REASSIGN_ALL_RSRC);
1230
1231         /* Reset IODA tables to a clean state */
1232         rc = opal_pci_reset(phb_id, OPAL_PCI_IODA_TABLE_RESET, OPAL_ASSERT_RESET);
1233         if (rc)
1234                 pr_warning("  OPAL Error %ld performing IODA table reset !\n", rc);
1235
1236         /*
1237          * On IODA1 map everything to PE#0, on IODA2 we assume the IODA reset
1238          * has cleared the RTT which has the same effect
1239          */
1240         if (ioda_type == PNV_PHB_IODA1)
1241                 opal_pci_set_pe(phb_id, 0, 0, 7, 1, 1 , OPAL_MAP_PE);
1242 }
1243
1244 void pnv_pci_init_ioda2_phb(struct device_node *np)
1245 {
1246         pnv_pci_init_ioda_phb(np, PNV_PHB_IODA2);
1247 }
1248
1249 void __init pnv_pci_init_ioda_hub(struct device_node *np)
1250 {
1251         struct device_node *phbn;
1252         const u64 *prop64;
1253         u64 hub_id;
1254
1255         pr_info("Probing IODA IO-Hub %s\n", np->full_name);
1256
1257         prop64 = of_get_property(np, "ibm,opal-hubid", NULL);
1258         if (!prop64) {
1259                 pr_err(" Missing \"ibm,opal-hubid\" property !\n");
1260                 return;
1261         }
1262         hub_id = be64_to_cpup(prop64);
1263         pr_devel(" HUB-ID : 0x%016llx\n", hub_id);
1264
1265         /* Count child PHBs */
1266         for_each_child_of_node(np, phbn) {
1267                 /* Look for IODA1 PHBs */
1268                 if (of_device_is_compatible(phbn, "ibm,ioda-phb"))
1269                         pnv_pci_init_ioda_phb(phbn, PNV_PHB_IODA1);
1270         }
1271 }