arch/powerpc/perf/power9-pmu.c

   1 /*
   2  * Performance counter support for POWER9 processors.
   3  *
   4  * Copyright 2009 Paul Mackerras, IBM Corporation.
   5  * Copyright 2013 Michael Ellerman, IBM Corporation.
   6  * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or later version.
  12  */
  13
  14 #define pr_fmt(fmt)     "power9-pmu: " fmt
  15
  16 #include "isa207-common.h"
  17
  18 /*
  19  * Some power9 event codes.
  20  */
  21 #define EVENT(_name, _code)     _name = _code,
  22
  23 enum {
  24 #include "power9-events-list.h"
  25 };
  26
  27 #undef EVENT
  28
  29 /* MMCRA IFM bits - POWER9 */
  30 #define POWER9_MMCRA_IFM1               0x0000000040000000UL
  31 #define POWER9_MMCRA_IFM2               0x0000000080000000UL
  32 #define POWER9_MMCRA_IFM3               0x00000000C0000000UL
  33 #define POWER9_MMCRA_BHRB_MASK          0x00000000C0000000UL
  34
  35 GENERIC_EVENT_ATTR(cpu-cycles,                  PM_CYC);
  36 GENERIC_EVENT_ATTR(stalled-cycles-frontend,     PM_ICT_NOSLOT_CYC);
  37 GENERIC_EVENT_ATTR(stalled-cycles-backend,      PM_CMPLU_STALL);
  38 GENERIC_EVENT_ATTR(instructions,                PM_INST_CMPL);
  39 GENERIC_EVENT_ATTR(branch-instructions,         PM_BRU_CMPL);
  40 GENERIC_EVENT_ATTR(branch-misses,               PM_BR_MPRED_CMPL);
  41 GENERIC_EVENT_ATTR(cache-references,            PM_LD_REF_L1);
  42 GENERIC_EVENT_ATTR(cache-misses,                PM_LD_MISS_L1_FIN);
  43
  44 CACHE_EVENT_ATTR(L1-dcache-load-misses,         PM_LD_MISS_L1_FIN);
  45 CACHE_EVENT_ATTR(L1-dcache-loads,               PM_LD_REF_L1);
  46 CACHE_EVENT_ATTR(L1-dcache-prefetches,          PM_L1_PREF);
  47 CACHE_EVENT_ATTR(L1-dcache-store-misses,        PM_ST_MISS_L1);
  48 CACHE_EVENT_ATTR(L1-icache-load-misses,         PM_L1_ICACHE_MISS);
  49 CACHE_EVENT_ATTR(L1-icache-loads,               PM_INST_FROM_L1);
  50 CACHE_EVENT_ATTR(L1-icache-prefetches,          PM_IC_PREF_WRITE);
  51 CACHE_EVENT_ATTR(LLC-load-misses,               PM_DATA_FROM_L3MISS);
  52 CACHE_EVENT_ATTR(LLC-loads,                     PM_DATA_FROM_L3);
  53 CACHE_EVENT_ATTR(LLC-prefetches,                PM_L3_PREF_ALL);
  54 CACHE_EVENT_ATTR(LLC-store-misses,              PM_L2_ST_MISS);
  55 CACHE_EVENT_ATTR(LLC-stores,                    PM_L2_ST);
  56 CACHE_EVENT_ATTR(branch-load-misses,            PM_BR_MPRED_CMPL);
  57 CACHE_EVENT_ATTR(branch-loads,                  PM_BRU_CMPL);
  58 CACHE_EVENT_ATTR(dTLB-load-misses,              PM_DTLB_MISS);
  59 CACHE_EVENT_ATTR(iTLB-load-misses,              PM_ITLB_MISS);
  60
  61 static struct attribute *power9_events_attr[] = {
  62         GENERIC_EVENT_PTR(PM_CYC),
  63         GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC),
  64         GENERIC_EVENT_PTR(PM_CMPLU_STALL),
  65         GENERIC_EVENT_PTR(PM_INST_CMPL),
  66         GENERIC_EVENT_PTR(PM_BRU_CMPL),
  67         GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
  68         GENERIC_EVENT_PTR(PM_LD_REF_L1),
  69         GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),
  70         CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN),
  71         CACHE_EVENT_PTR(PM_LD_REF_L1),
  72         CACHE_EVENT_PTR(PM_L1_PREF),
  73         CACHE_EVENT_PTR(PM_ST_MISS_L1),
  74         CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
  75         CACHE_EVENT_PTR(PM_INST_FROM_L1),
  76         CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
  77         CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
  78         CACHE_EVENT_PTR(PM_DATA_FROM_L3),
  79         CACHE_EVENT_PTR(PM_L3_PREF_ALL),
  80         CACHE_EVENT_PTR(PM_L2_ST_MISS),
  81         CACHE_EVENT_PTR(PM_L2_ST),
  82         CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
  83         CACHE_EVENT_PTR(PM_BRU_CMPL),
  84         CACHE_EVENT_PTR(PM_DTLB_MISS),
  85         CACHE_EVENT_PTR(PM_ITLB_MISS),
  86         NULL
  87 };
  88
  89 static struct attribute_group power9_pmu_events_group = {
  90         .name = "events",
  91         .attrs = power9_events_attr,
  92 };
  93
  94 PMU_FORMAT_ATTR(event,          "config:0-49");
  95 PMU_FORMAT_ATTR(pmcxsel,        "config:0-7");
  96 PMU_FORMAT_ATTR(mark,           "config:8");
  97 PMU_FORMAT_ATTR(combine,        "config:11");
  98 PMU_FORMAT_ATTR(unit,           "config:12-15");
  99 PMU_FORMAT_ATTR(pmc,            "config:16-19");
 100 PMU_FORMAT_ATTR(cache_sel,      "config:20-23");
 101 PMU_FORMAT_ATTR(sample_mode,    "config:24-28");
 102 PMU_FORMAT_ATTR(thresh_sel,     "config:29-31");
 103 PMU_FORMAT_ATTR(thresh_stop,    "config:32-35");
 104 PMU_FORMAT_ATTR(thresh_start,   "config:36-39");
 105 PMU_FORMAT_ATTR(thresh_cmp,     "config:40-49");
 106
 107 static struct attribute *power9_pmu_format_attr[] = {
 108         &format_attr_event.attr,
 109         &format_attr_pmcxsel.attr,
 110         &format_attr_mark.attr,
 111         &format_attr_combine.attr,
 112         &format_attr_unit.attr,
 113         &format_attr_pmc.attr,
 114         &format_attr_cache_sel.attr,
 115         &format_attr_sample_mode.attr,
 116         &format_attr_thresh_sel.attr,
 117         &format_attr_thresh_stop.attr,
 118         &format_attr_thresh_start.attr,
 119         &format_attr_thresh_cmp.attr,
 120         NULL,
 121 };
 122
 123 static struct attribute_group power9_pmu_format_group = {
 124         .name = "format",
 125         .attrs = power9_pmu_format_attr,
 126 };
 127
 128 static const struct attribute_group *power9_pmu_attr_groups[] = {
 129         &power9_pmu_format_group,
 130         &power9_pmu_events_group,
 131         NULL,
 132 };
 133
 134 static int power9_generic_events[] = {
 135         [PERF_COUNT_HW_CPU_CYCLES] =                    PM_CYC,
 136         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =       PM_ICT_NOSLOT_CYC,
 137         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =        PM_CMPLU_STALL,
 138         [PERF_COUNT_HW_INSTRUCTIONS] =                  PM_INST_CMPL,
 139         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =           PM_BRU_CMPL,
 140         [PERF_COUNT_HW_BRANCH_MISSES] =                 PM_BR_MPRED_CMPL,
 141         [PERF_COUNT_HW_CACHE_REFERENCES] =              PM_LD_REF_L1,
 142         [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1_FIN,
 143 };
 144
 145 static u64 power9_bhrb_filter_map(u64 branch_sample_type)
 146 {
 147         u64 pmu_bhrb_filter = 0;
 148
 149         /* BHRB and regular PMU events share the same privilege state
 150          * filter configuration. BHRB is always recorded along with a
 151          * regular PMU event. As the privilege state filter is handled
 152          * in the basic PMC configuration of the accompanying regular
 153          * PMU event, we ignore any separate BHRB specific request.
 154          */
 155
 156         /* No branch filter requested */
 157         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
 158                 return pmu_bhrb_filter;
 159
 160         /* Invalid branch filter options - HW does not support */
 161         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
 162                 return -1;
 163
 164         if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
 165                 return -1;
 166
 167         if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
 168                 return -1;
 169
 170         if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
 171                 pmu_bhrb_filter |= POWER9_MMCRA_IFM1;
 172                 return pmu_bhrb_filter;
 173         }
 174
 175         /* Every thing else is unsupported */
 176         return -1;
 177 }
 178
 179 static void power9_config_bhrb(u64 pmu_bhrb_filter)
 180 {
 181         pmu_bhrb_filter &= POWER9_MMCRA_BHRB_MASK;
 182
 183         /* Enable BHRB filter in PMU */
 184         mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
 185 }
 186
 187 #define C(x)    PERF_COUNT_HW_CACHE_##x
 188
 189 /*
 190  * Table of generalized cache-related events.
 191  * 0 means not supported, -1 means nonsensical, other values
 192  * are event codes.
 193  */
 194 static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
 195         [ C(L1D) ] = {
 196                 [ C(OP_READ) ] = {
 197                         [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
 198                         [ C(RESULT_MISS)   ] = PM_LD_MISS_L1_FIN,
 199                 },
 200                 [ C(OP_WRITE) ] = {
 201                         [ C(RESULT_ACCESS) ] = 0,
 202                         [ C(RESULT_MISS)   ] = PM_ST_MISS_L1,
 203                 },
 204                 [ C(OP_PREFETCH) ] = {
 205                         [ C(RESULT_ACCESS) ] = PM_L1_PREF,
 206                         [ C(RESULT_MISS)   ] = 0,
 207                 },
 208         },
 209         [ C(L1I) ] = {
 210                 [ C(OP_READ) ] = {
 211                         [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
 212                         [ C(RESULT_MISS)   ] = PM_L1_ICACHE_MISS,
 213                 },
 214                 [ C(OP_WRITE) ] = {
 215                         [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
 216                         [ C(RESULT_MISS)   ] = -1,
 217                 },
 218                 [ C(OP_PREFETCH) ] = {
 219                         [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
 220                         [ C(RESULT_MISS)   ] = 0,
 221                 },
 222         },
 223         [ C(LL) ] = {
 224                 [ C(OP_READ) ] = {
 225                         [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
 226                         [ C(RESULT_MISS)   ] = PM_DATA_FROM_L3MISS,
 227                 },
 228                 [ C(OP_WRITE) ] = {
 229                         [ C(RESULT_ACCESS) ] = PM_L2_ST,
 230                         [ C(RESULT_MISS)   ] = PM_L2_ST_MISS,
 231                 },
 232                 [ C(OP_PREFETCH) ] = {
 233                         [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
 234                         [ C(RESULT_MISS)   ] = 0,
 235                 },
 236         },
 237         [ C(DTLB) ] = {
 238                 [ C(OP_READ) ] = {
 239                         [ C(RESULT_ACCESS) ] = 0,
 240                         [ C(RESULT_MISS)   ] = PM_DTLB_MISS,
 241                 },
 242                 [ C(OP_WRITE) ] = {
 243                         [ C(RESULT_ACCESS) ] = -1,
 244                         [ C(RESULT_MISS)   ] = -1,
 245                 },
 246                 [ C(OP_PREFETCH) ] = {
 247                         [ C(RESULT_ACCESS) ] = -1,
 248                         [ C(RESULT_MISS)   ] = -1,
 249                 },
 250         },
 251         [ C(ITLB) ] = {
 252                 [ C(OP_READ) ] = {
 253                         [ C(RESULT_ACCESS) ] = 0,
 254                         [ C(RESULT_MISS)   ] = PM_ITLB_MISS,
 255                 },
 256                 [ C(OP_WRITE) ] = {
 257                         [ C(RESULT_ACCESS) ] = -1,
 258                         [ C(RESULT_MISS)   ] = -1,
 259                 },
 260                 [ C(OP_PREFETCH) ] = {
 261                         [ C(RESULT_ACCESS) ] = -1,
 262                         [ C(RESULT_MISS)   ] = -1,
 263                 },
 264         },
 265         [ C(BPU) ] = {
 266                 [ C(OP_READ) ] = {
 267                         [ C(RESULT_ACCESS) ] = PM_BRU_CMPL,
 268                         [ C(RESULT_MISS)   ] = PM_BR_MPRED_CMPL,
 269                 },
 270                 [ C(OP_WRITE) ] = {
 271                         [ C(RESULT_ACCESS) ] = -1,
 272                         [ C(RESULT_MISS)   ] = -1,
 273                 },
 274                 [ C(OP_PREFETCH) ] = {
 275                         [ C(RESULT_ACCESS) ] = -1,
 276                         [ C(RESULT_MISS)   ] = -1,
 277                 },
 278         },
 279         [ C(NODE) ] = {
 280                 [ C(OP_READ) ] = {
 281                         [ C(RESULT_ACCESS) ] = -1,
 282                         [ C(RESULT_MISS)   ] = -1,
 283                 },
 284                 [ C(OP_WRITE) ] = {
 285                         [ C(RESULT_ACCESS) ] = -1,
 286                         [ C(RESULT_MISS)   ] = -1,
 287                 },
 288                 [ C(OP_PREFETCH) ] = {
 289                         [ C(RESULT_ACCESS) ] = -1,
 290                         [ C(RESULT_MISS)   ] = -1,
 291                 },
 292         },
 293 };
 294
 295 #undef C
 296
 297 static struct power_pmu power9_pmu = {
 298         .name                   = "POWER9",
 299         .n_counter              = MAX_PMU_COUNTERS,
 300         .add_fields             = ISA207_ADD_FIELDS,
 301         .test_adder             = P9_DD1_TEST_ADDER,
 302         .compute_mmcr           = isa207_compute_mmcr,
 303         .config_bhrb            = power9_config_bhrb,
 304         .bhrb_filter_map        = power9_bhrb_filter_map,
 305         .get_constraint         = isa207_get_constraint,
 306         .disable_pmc            = isa207_disable_pmc,
 307         .flags                  = PPMU_HAS_SIER | PPMU_ARCH_207S,
 308         .n_generic              = ARRAY_SIZE(power9_generic_events),
 309         .generic_events         = power9_generic_events,
 310         .cache_events           = &power9_cache_events,
 311         .attr_groups            = power9_pmu_attr_groups,
 312         .bhrb_nr                = 32,
 313 };
 314
 315 static int __init init_power9_pmu(void)
 316 {
 317         int rc;
 318
 319         /* Comes from cpu_specs[] */
 320         if (!cur_cpu_spec->oprofile_cpu_type ||
 321             strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9"))
 322                 return -ENODEV;
 323
 324         rc = register_power_pmu(&power9_pmu);
 325         if (rc)
 326                 return rc;
 327
 328         /* Tell userspace that EBB is supported */
 329         cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
 330
 331         return 0;
 332 }
 333 early_initcall(init_power9_pmu);