2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 #include <linux/threads.h>
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/thread_info.h>
16 #include <asm/ppc_asm.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/ppc-opcode.h>
19 #include <asm/hw_irq.h>
20 #include <asm/kvm_book3s_asm.h>
22 #include <asm/cpuidle.h>
23 #include <asm/exception-64s.h>
24 #include <asm/book3s/64/mmu-hash.h>
30 * Use unused space in the interrupt stack to save and restore
31 * registers for winkle support.
46 #define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16
51 * Used by threads before entering deep idle states. Saves SPRs
52 * in interrupt stack frame
56 * Note all register i.e per-core, per-subcore or per-thread is saved
57 * here since any thread in the core might wake up first
61 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
71 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
89 * On POWER9, there are idle states such as stop4, invoked via cpuidle,
90 * that lose hypervisor resources. In such cases, we need to save
91 * additional SPRs before entering those idle states so that they can
92 * be restored to their older values on wakeup from the idle state.
94 * On POWER8, the only such deep idle state is winkle which is used
95 * only in the context of CPU-Hotplug, where these additional SPRs are
96 * reinitiazed to a sane value. Hence there is no need to save/restore
101 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
103 power9_save_additional_sprs:
106 std r3, STOP_PID(r13)
107 std r4, STOP_LDBAR(r13)
111 std r3, STOP_FSCR(r13)
112 std r4, STOP_HFSCR(r13)
116 std r3, STOP_MMCRA(r13)
117 std r4, STOP_MMCR1(r13)
120 std r3, STOP_MMCR2(r13)
123 power9_restore_additional_sprs:
129 ld r3, STOP_LDBAR(r13)
130 ld r4, STOP_FSCR(r13)
134 ld r3, STOP_HFSCR(r13)
135 ld r4, STOP_MMCRA(r13)
138 /* We have already restored PACA_MMCR0 */
139 ld r3, STOP_MMCR1(r13)
140 ld r4, STOP_MMCR2(r13)
143 ld r4, PACA_SPRG_VDSO(r13)
148 * Used by threads when the lock bit of core_idle_state is set.
149 * Threads will spin in HMT_LOW until the lock bit is cleared.
150 * r14 - pointer to core_idle_state
151 * r15 - used to load contents of core_idle_state
152 * r9 - used as a temporary variable
158 andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
162 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
163 bne- core_idle_lock_held
167 * Pass requested state in r3:
168 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
169 * - Requested PSSCR value in POWER9
171 * Address of idle handler to branch to in realmode in r4
173 pnv_powersave_common:
174 /* Use r3 to pass state nap/sleep/winkle */
175 /* NAP is a state loss, we create a regs frame on the
176 * stack, fill it up with the state we care about and
177 * stick a pointer to it in PACAR1. We really only
178 * need to save PC, some CR bits and the NV GPRs,
179 * but for now an interrupt frame will do.
185 stdu r1,-INT_FRAME_SIZE(r1)
189 /* We haven't lost state ... yet */
191 stb r0,PACA_NAPSTATELOST(r13)
193 /* Continue saving state */
202 * POWER9 does not require real mode to stop, and presently does not
203 * set hwthread_state for KVM (threads don't share MMU context), so
204 * we can remain in virtual mode for this.
207 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
210 * Go to real mode to do the nap, as required by the architecture.
211 * Also, we need to be in real mode before setting hwthread_state,
212 * because as soon as we do that, another thread can switch
213 * the MMU context to the guest.
215 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
220 * This is the sequence required to execute idle instructions, as
221 * specified in ISA v2.07 (and earlier). MSR[IR] and MSR[DR] must be 0.
223 #define IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST) \
224 /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
228 236: cmpd cr0,r0,r0; \
233 .globl pnv_enter_arch207_idle_mode
234 pnv_enter_arch207_idle_mode:
235 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
236 /* Tell KVM we're entering idle */
237 li r4,KVM_HWTHREAD_IN_IDLE
238 /******************************************************/
239 /* N O T E W E L L ! ! ! N O T E W E L L */
240 /* The following store to HSTATE_HWTHREAD_STATE(r13) */
241 /* MUST occur in real mode, i.e. with the MMU off, */
242 /* and the MMU must stay off until we clear this flag */
243 /* and test HSTATE_HWTHREAD_REQ(r13) in */
244 /* pnv_powersave_wakeup in this file. */
245 /* The reason is that another thread can switch the */
246 /* MMU to a guest context whenever this flag is set */
247 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
248 /* that would potentially cause this thread to start */
249 /* executing instructions from guest memory in */
250 /* hypervisor mode, leading to a host crash or data */
251 /* corruption, or worse. */
252 /******************************************************/
253 stb r4,HSTATE_HWTHREAD_STATE(r13)
255 stb r3,PACA_THREAD_IDLE_STATE(r13)
256 cmpwi cr3,r3,PNV_THREAD_SLEEP
258 IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
261 /* Sleep or winkle */
262 lbz r7,PACA_THREAD_MASK(r13)
263 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
266 lis r5,PNV_CORE_IDLE_WINKLE_COUNT@h
271 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
272 bnel- core_idle_lock_held
274 add r15,r15,r5 /* Add if winkle */
275 andc r15,r15,r7 /* Clear thread bit */
277 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
280 * If cr0 = 0, then current thread is the last thread of the core entering
281 * sleep. Last thread needs to execute the hardware bug workaround code if
282 * required by the platform.
283 * Make the workaround call unconditionally here. The below branch call is
284 * patched out when the idle states are discovered if the platform does not
287 .global pnv_fastsleep_workaround_at_entry
288 pnv_fastsleep_workaround_at_entry:
289 beq fastsleep_workaround_at_entry
295 common_enter: /* common code for all the threads entering sleep or winkle */
297 IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
299 fastsleep_workaround_at_entry:
300 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
305 /* Fast sleep workaround */
308 bl opal_config_cpu_idle_state
311 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
317 bl save_sprs_to_stack
319 IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
322 * r3 - PSSCR value corresponding to the requested stop state.
324 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
325 power_enter_stop_kvm_rm:
327 * This is currently unused because POWER9 KVM does not have to
328 * gather secondary threads into sibling mode, but the code is
329 * here in case that function is required.
331 * Tell KVM we're entering idle.
333 li r4,KVM_HWTHREAD_IN_IDLE
334 /* DO THIS IN REAL MODE! See comment above. */
335 stb r4,HSTATE_HWTHREAD_STATE(r13)
339 * Check if we are executing the lite variant with ESL=EC=0
341 andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED
342 clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */
343 bne .Lhandle_esl_ec_set
345 li r3,0 /* Since we didn't lose state, return 0 */
348 * pnv_wakeup_noloss() expects r12 to contain the SRR1 value so
349 * it can determine if the wakeup reason is an HMI in
350 * CHECK_HMI_INTERRUPT.
352 * However, when we wakeup with ESL=0, SRR1 will not contain the wakeup
353 * reason, so there is no point setting r12 to SRR1.
355 * Further, we clear r12 here, so that we don't accidentally enter the
356 * HMI in pnv_wakeup_noloss() if the value of r12[42:45] == WAKE_HMI.
363 * POWER9 DD2 can incorrectly set PMAO when waking up after a
364 * state-loss idle. Saving and restoring MMCR0 over idle is a
371 * Check if the requested state is a deep idle state.
373 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
374 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
376 bge .Lhandle_deep_stop
377 PPC_STOP /* Does not return (system reset interrupt) */
381 * Entering deep idle state.
382 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
383 * stack and enter stop
385 lbz r7,PACA_THREAD_MASK(r13)
386 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
390 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
391 bnel- core_idle_lock_held
392 andc r15,r15,r7 /* Clear thread bit */
398 bl save_sprs_to_stack
400 PPC_STOP /* Does not return (system reset interrupt) */
403 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
404 * r3 contains desired idle state (PNV_THREAD_NAP/SLEEP/WINKLE).
406 _GLOBAL(power7_idle_insn)
407 /* Now check if user or arch enabled NAP mode */
408 LOAD_REG_ADDR(r4, pnv_enter_arch207_idle_mode)
409 b pnv_powersave_common
411 #define CHECK_HMI_INTERRUPT \
412 BEGIN_FTR_SECTION_NESTED(66); \
413 rlwinm r0,r12,45-31,0xf; /* extract wake reason field (P8) */ \
414 FTR_SECTION_ELSE_NESTED(66); \
415 rlwinm r0,r12,45-31,0xe; /* P7 wake reason field is 3 bits */ \
416 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
417 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
419 /* Invoke opal call to handle hmi */ \
420 ld r2,PACATOC(r13); \
422 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
423 li r3,0; /* NULL argument */ \
424 bl hmi_exception_realmode; \
426 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
430 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
431 * r3 contains desired PSSCR register value.
433 _GLOBAL(power9_idle_stop)
434 std r3, PACA_REQ_PSSCR(r13)
436 LOAD_REG_ADDR(r4,power_enter_stop)
437 b pnv_powersave_common
441 * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1,
442 * HSPRG0 will be set to the HSPRG0 value of one of the
443 * threads in this core. Thus the value we have in r13
444 * may not be this thread's paca pointer.
446 * Fortunately, the TIR remains invariant. Since this thread's
447 * paca pointer is recorded in all its sibling's paca, we can
448 * correctly recover this thread's paca pointer if we
449 * know the index of this thread in the core.
451 * This index can be obtained from the TIR.
453 * i.e, thread's position in the core = TIR.
454 * If this value is i, then this thread's paca is
455 * paca->thread_sibling_pacas[i].
457 power9_dd1_recover_paca:
460 * Since each entry in thread_sibling_pacas is 8 bytes
461 * we need to left-shift by 3 bits. Thus r4 = i * 8
464 /* Get &paca->thread_sibling_pacas[0] in r5 */
465 ld r5, PACA_SIBLING_PACA_PTRS(r13)
466 /* Load paca->thread_sibling_pacas[i] into r13 */
470 * Indicate that we have lost NVGPR state
471 * which needs to be restored from the stack.
474 stb r3,PACA_NAPSTATELOST(r13)
478 * Called from machine check handler for powersave wakeups.
479 * Low level machine check processing has already been done. Now just
480 * go through the wake up path to get everything in order.
482 * r3 - The original SRR1 value.
483 * Original SRR[01] have been clobbered.
486 .global pnv_powersave_wakeup_mce
487 pnv_powersave_wakeup_mce:
488 /* Set cr3 for pnv_powersave_wakeup */
489 rlwinm r11,r3,47-31,30,31
493 * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake
494 * reason into r12, which allows reuse of the system reset wakeup
495 * code without being mistaken for another type of wakeup.
497 oris r12,r3,SRR1_WAKEMCE_RESVD@h
499 b pnv_powersave_wakeup
501 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
502 kvm_start_guest_check:
503 li r0,KVM_HWTHREAD_IN_KERNEL
504 stb r0,HSTATE_HWTHREAD_STATE(r13)
505 /* Order setting hwthread_state vs. testing hwthread_req */
507 lbz r0,HSTATE_HWTHREAD_REQ(r13)
514 * Called from reset vector for powersave wakeups.
515 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
518 .global pnv_powersave_wakeup
519 pnv_powersave_wakeup:
523 BEGIN_FTR_SECTION_NESTED(70)
524 bl power9_dd1_recover_paca
525 END_FTR_SECTION_NESTED_IFSET(CPU_FTR_POWER9_DD1, 70)
526 bl pnv_restore_hyp_resource_arch300
528 bl pnv_restore_hyp_resource_arch207
529 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
531 li r0,PNV_THREAD_RUNNING
532 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
536 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
538 bl kvm_start_guest_check
539 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
542 /* Return SRR1 from power7_nap() */
543 blt cr3,pnv_wakeup_noloss
547 * Check whether we have woken up with hypervisor state loss.
548 * If yes, restore hypervisor state and return back to link.
550 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
552 pnv_restore_hyp_resource_arch300:
554 * Workaround for POWER9, if we lost resources, the ERAT
555 * might have been mixed up and needs flushing. We also need
556 * to reload MMCR0 (see comment above). We also need to set
557 * then clear bit 60 in MMCRA to ensure the PMU starts running.
563 ori r4,r4,(1 << (63-60))
565 xori r4,r4,(1 << (63-60))
571 * POWER ISA 3. Use PSSCR to determine if we
572 * are waking up from deep idle state
574 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
575 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
577 BEGIN_FTR_SECTION_NESTED(71)
579 * Assume that we are waking up from the state
580 * same as the Requested Level (RL) in the PSSCR
581 * which are Bits 60-63
583 ld r5,PACA_REQ_PSSCR(r13)
585 FTR_SECTION_ELSE_NESTED(71)
587 * 0-3 bits correspond to Power-Saving Level Status
588 * which indicates the idle state we are waking up from
592 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_POWER9_DD1, 71)
594 bge cr4,pnv_wakeup_tb_loss /* returns to caller */
596 blr /* Waking up without hypervisor state loss. */
598 /* Same calling convention as arch300 */
599 pnv_restore_hyp_resource_arch207:
601 * POWER ISA 2.07 or less.
602 * Check if we slept with sleep or winkle.
604 lbz r4,PACA_THREAD_IDLE_STATE(r13)
605 cmpwi cr2,r4,PNV_THREAD_NAP
606 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
609 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
610 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
611 * indicates we are waking with hypervisor state loss from nap.
615 blr /* Waking up without hypervisor state loss */
618 * Called if waking up from idle state which can cause either partial or
619 * complete hyp state loss.
620 * In POWER8, called if waking up from fastsleep or winkle
621 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
624 * cr3 - gt if waking up with partial/complete hypervisor state loss
627 * cr4 - gt or eq if waking up from complete hypervisor state loss.
630 * r4 - PACA_THREAD_IDLE_STATE
635 * Before entering any idle state, the NVGPRs are saved in the stack.
636 * If there was a state loss, or PACA_NAPSTATELOST was set, then the
637 * NVGPRs are restored. If we are here, it is likely that state is lost,
638 * but not guaranteed -- neither ISA207 nor ISA300 tests to reach
639 * here are the same as the test to restore NVGPRS:
640 * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
641 * and SRR1 test for restoring NVGPRs.
643 * We are about to clobber NVGPRs now, so set NAPSTATELOST to
644 * guarantee they will always be restored. This might be tightened
645 * with careful reading of specs (particularly for ISA300) but this
646 * is already a slow wakeup path and it's simpler to be safe.
649 stb r0,PACA_NAPSTATELOST(r13)
653 * Save SRR1 and LR in NVGPRs as they might be clobbered in
654 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
655 * to determine the wakeup reason if we branch to kvm_start_guest. LR
656 * is required to return back to reset vector after hypervisor state
657 * restore is complete.
664 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
666 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
667 lbz r7,PACA_THREAD_MASK(r13)
670 * Take the core lock to synchronize against other threads.
672 * Lock bit is set in one of the 2 cases-
673 * a. In the sleep/winkle enter path, the last thread is executing
674 * fastsleep workaround code.
675 * b. In the wake up path, another thread is executing fastsleep
676 * workaround undo code or resyncing timebase or restoring context
677 * In either case loop until the lock bit is cleared.
681 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
682 bnel- core_idle_lock_held
683 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
688 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
693 * cr2 - eq if first thread to wakeup in core
694 * cr3- gt if waking up with partial/complete hypervisor state loss
696 * cr4 - gt or eq if waking up from complete hypervisor state loss.
702 * If yes, check if all threads were in winkle, decrement our
703 * winkle count, set all thread winkle bits if all were in winkle.
704 * Check if our thread has a winkle bit set, and set cr4 accordingly
705 * (to match ISA300, above). Pseudo-code for core idle state
706 * transitions for ISA207 is as follows (everything happens atomically
707 * due to store conditional and/or lock bit):
714 * core_idle_state &= ~thread_in_core
719 * bool first_in_core, first_in_subcore;
721 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
722 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
724 * core_idle_state |= thread_in_core;
729 * core_idle_state &= ~thread_in_core;
730 * core_idle_state += 1 << WINKLE_COUNT_SHIFT;
735 * bool first_in_core, first_in_subcore, winkle_state_lost;
737 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
738 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
740 * core_idle_state |= thread_in_core;
742 * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT))
743 * core_idle_state |= THREAD_WINKLE_BITS;
744 * core_idle_state -= 1 << WINKLE_COUNT_SHIFT;
746 * winkle_state_lost = core_idle_state &
747 * (thread_in_core << WINKLE_THREAD_SHIFT);
748 * core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT);
752 cmpwi r18,PNV_THREAD_WINKLE
754 andis. r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h
755 subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h
757 ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */
759 /* Shift thread bit to winkle mask, then test if this thread is set,
760 * and remove it from the winkle bits */
764 cmpwi cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */
766 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
768 cmpwi r4,0 /* Check if first in subcore */
770 or r15,r15,r7 /* Set thread bit */
771 beq first_thread_in_subcore
772 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
774 or r15,r15,r7 /* Set thread bit */
775 beq cr2,first_thread_in_core
777 /* Not first thread in core or subcore to wake up */
780 first_thread_in_subcore:
782 * If waking up from sleep, subcore state is not lost. Hence
783 * skip subcore state restore
785 blt cr4,subcore_state_restored
787 /* Restore per-subcore state */
796 subcore_state_restored:
798 * Check if the thread is also the first thread in the core. If not,
799 * skip to clear_lock.
803 first_thread_in_core:
806 * First thread in the core waking up from any state which can cause
807 * partial or complete hypervisor state loss. It needs to
808 * call the fastsleep workaround code if the platform requires it.
809 * Call it unconditionally here. The below branch instruction will
810 * be patched out if the platform does not have fastsleep or does not
811 * require the workaround. Patching will be performed during the
812 * discovery of idle-states.
814 .global pnv_fastsleep_workaround_at_exit
815 pnv_fastsleep_workaround_at_exit:
816 b fastsleep_workaround_at_exit
820 * Use cr3 which indicates that we are waking up with atleast partial
821 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
823 ble cr3,.Ltb_resynced
824 /* Time base re-sync */
825 bl opal_resync_timebase;
827 * If waking up from sleep (POWER8), per core state
828 * is not lost, skip to clear_lock.
834 * First thread in the core to wake up and its waking up with
835 * complete hypervisor state loss. Restore per core hypervisor
845 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
853 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
859 * Common to all threads.
861 * If waking up from sleep, hypervisor state is not lost. Hence
862 * skip hypervisor state restore.
864 blt cr4,hypervisor_state_restored
866 /* Waking up from winkle */
868 BEGIN_MMU_FTR_SECTION
870 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
871 /* Restore SLB from PACA */
872 ld r8,PACA_SLBSHADOWPTR(r13)
875 li r3, SLBSHADOW_SAVEAREA
879 andis. r7,r5,SLB_ESID_V@h
886 /* Restore per thread state */
897 /* Call cur_cpu_spec->cpu_restore() */
898 LOAD_REG_ADDR(r4, cur_cpu_spec)
900 ld r12,CPU_SPEC_RESTORE(r4)
901 #ifdef PPC64_ELF_ABI_v1
908 * On POWER9, we can come here on wakeup from a cpuidle stop state.
909 * Hence restore the additional SPRs to the saved value.
911 * On POWER8, we come here only on winkle. Since winkle is used
912 * only in the case of CPU-Hotplug, we don't need to restore
913 * the additional SPRs.
916 bl power9_restore_additional_sprs
917 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
918 hypervisor_state_restored:
922 blr /* return to pnv_powersave_wakeup */
924 fastsleep_workaround_at_exit:
927 bl opal_config_cpu_idle_state
931 * R3 here contains the value that will be returned to the caller
933 * R12 contains SRR1 for CHECK_HMI_INTERRUPT.
935 .global pnv_wakeup_loss
940 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
946 addi r1,r1,INT_FRAME_SIZE
953 * R3 here contains the value that will be returned to the caller
955 * R12 contains SRR1 for CHECK_HMI_INTERRUPT.
958 lbz r0,PACA_NAPSTATELOST(r13)
964 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
968 addi r1,r1,INT_FRAME_SIZE