arch/powerpc/boot/dts/t4240qds.dts

   1 /*
   2  * T4240QDS Device Tree Source
   3  *
   4  * Copyright 2012 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 /include/ "fsl/t4240si-pre.dtsi"
  36
  37 / {
  38         model = "fsl,T4240QDS";
  39         compatible = "fsl,T4240QDS";
  40         #address-cells = <2>;
  41         #size-cells = <2>;
  42         interrupt-parent = <&mpic>;
  43
  44         ifc: localbus@ffe124000 {
  45                 reg = <0xf 0xfe124000 0 0x2000>;
  46                 ranges = <0 0 0xf 0xe8000000 0x08000000
  47                           2 0 0xf 0xff800000 0x00010000
  48                           3 0 0xf 0xffdf0000 0x00008000>;
  49
  50                 nor@0,0 {
  51                         #address-cells = <1>;
  52                         #size-cells = <1>;
  53                         compatible = "cfi-flash";
  54                         reg = <0x0 0x0 0x8000000>;
  55
  56                         bank-width = <2>;
  57                         device-width = <1>;
  58                 };
  59
  60                 nand@2,0 {
  61                         #address-cells = <1>;
  62                         #size-cells = <1>;
  63                         compatible = "fsl,ifc-nand";
  64                         reg = <0x2 0x0 0x10000>;
  65
  66                         partition@0 {
  67                                 /* This location must not be altered  */
  68                                 /* 1MB for u-boot Bootloader Image */
  69                                 reg = <0x0 0x00100000>;
  70                                 label = "NAND U-Boot Image";
  71                                 read-only;
  72                         };
  73
  74                         partition@100000 {
  75                                 /* 1MB for DTB Image */
  76                                 reg = <0x00100000 0x00100000>;
  77                                 label = "NAND DTB Image";
  78                         };
  79
  80                         partition@200000 {
  81                                 /* 10MB for Linux Kernel Image */
  82                                 reg = <0x00200000 0x00A00000>;
  83                                 label = "NAND Linux Kernel Image";
  84                         };
  85
  86                         partition@C00000 {
  87                                 /* 500MB for Root file System Image */
  88                                 reg = <0x00c00000 0x1F400000>;
  89                                 label = "NAND RFS Image";
  90                         };
  91                 };
  92
  93                 board-control@3,0 {
  94                         compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis";
  95                         reg = <3 0 0x300>;
  96                 };
  97         };
  98
  99         memory {
 100                 device_type = "memory";
 101         };
 102
 103         dcsr: dcsr@f00000000 {
 104                 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
 105         };
 106
 107         soc: soc@ffe000000 {
 108                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
 109                 reg = <0xf 0xfe000000 0 0x00001000>;
 110                 spi@110000 {
 111                         flash@0 {
 112                                 #address-cells = <1>;
 113                                 #size-cells = <1>;
 114                                 compatible = "sst,sst25wf040";
 115                                 reg = <0>;
 116                                 spi-max-frequency = <40000000>; /* input clock */
 117                         };
 118                 };
 119
 120                 i2c@118000 {
 121                         mux@77 {
 122                                 compatible = "nxp,pca9547";
 123                                 reg = <0x77>;
 124                                 #address-cells = <1>;
 125                                 #size-cells = <0>;
 126
 127                                 i2c@0 {
 128                                         #address-cells = <1>;
 129                                         #size-cells = <0>;
 130                                         reg = <0>;
 131
 132                                         eeprom@51 {
 133                                                 compatible = "at24,24c256";
 134                                                 reg = <0x51>;
 135                                         };
 136                                         eeprom@52 {
 137                                                 compatible = "at24,24c256";
 138                                                 reg = <0x52>;
 139                                         };
 140                                         eeprom@53 {
 141                                                 compatible = "at24,24c256";
 142                                                 reg = <0x53>;
 143                                         };
 144                                         eeprom@54 {
 145                                                 compatible = "at24,24c256";
 146                                                 reg = <0x54>;
 147                                         };
 148                                         eeprom@55 {
 149                                                 compatible = "at24,24c256";
 150                                                 reg = <0x55>;
 151                                         };
 152                                         eeprom@56 {
 153                                                 compatible = "at24,24c256";
 154                                                 reg = <0x56>;
 155                                         };
 156                                         rtc@68 {
 157                                                 compatible = "dallas,ds3232";
 158                                                 reg = <0x68>;
 159                                                 interrupts = <0x1 0x1 0 0>;
 160                                         };
 161                                 };
 162
 163                                 i2c@2 {
 164                                         #address-cells = <1>;
 165                                         #size-cells = <0>;
 166                                         reg = <0x2>;
 167
 168                                         ina220@40 {
 169                                                 compatible = "ti,ina220";
 170                                                 reg = <0x40>;
 171                                                 shunt-resistor = <1000>;
 172                                         };
 173
 174                                         ina220@41 {
 175                                                 compatible = "ti,ina220";
 176                                                 reg = <0x41>;
 177                                                 shunt-resistor = <1000>;
 178                                         };
 179
 180                                         ina220@44 {
 181                                                 compatible = "ti,ina220";
 182                                                 reg = <0x44>;
 183                                                 shunt-resistor = <1000>;
 184                                         };
 185
 186                                         ina220@45 {
 187                                                 compatible = "ti,ina220";
 188                                                 reg = <0x45>;
 189                                                 shunt-resistor = <1000>;
 190                                         };
 191
 192                                         ina220@46 {
 193                                                 compatible = "ti,ina220";
 194                                                 reg = <0x46>;
 195                                                 shunt-resistor = <1000>;
 196                                         };
 197
 198                                         ina220@47 {
 199                                                 compatible = "ti,ina220";
 200                                                 reg = <0x47>;
 201                                                 shunt-resistor = <1000>;
 202                                         };
 203                                 };
 204                         };
 205                 };
 206
 207                 sdhc@114000 {
 208                         voltage-ranges = <1800 1800 3300 3300>;
 209                 };
 210         };
 211
 212         pci0: pcie@ffe240000 {
 213                 reg = <0xf 0xfe240000 0 0x10000>;
 214                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 215                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 216                 pcie@0 {
 217                         ranges = <0x02000000 0 0xe0000000
 218                                   0x02000000 0 0xe0000000
 219                                   0 0x20000000
 220
 221                                   0x01000000 0 0x00000000
 222                                   0x01000000 0 0x00000000
 223                                   0 0x00010000>;
 224                 };
 225         };
 226
 227         pci1: pcie@ffe250000 {
 228                 reg = <0xf 0xfe250000 0 0x10000>;
 229                 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
 230                           0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
 231                 pcie@0 {
 232                         ranges = <0x02000000 0 0xe0000000
 233                                   0x02000000 0 0xe0000000
 234                                   0 0x20000000
 235
 236                                   0x01000000 0 0x00000000
 237                                   0x01000000 0 0x00000000
 238                                   0 0x00010000>;
 239                 };
 240         };
 241
 242         pci2: pcie@ffe260000 {
 243                 reg = <0xf 0xfe260000 0 0x1000>;
 244                 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
 245                           0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
 246                 pcie@0 {
 247                         ranges = <0x02000000 0 0xe0000000
 248                                   0x02000000 0 0xe0000000
 249                                   0 0x20000000
 250
 251                                   0x01000000 0 0x00000000
 252                                   0x01000000 0 0x00000000
 253                                   0 0x00010000>;
 254                 };
 255         };
 256
 257         pci3: pcie@ffe270000 {
 258                 reg = <0xf 0xfe270000 0 0x10000>;
 259                 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
 260                           0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
 261                 pcie@0 {
 262                         ranges = <0x02000000 0 0xe0000000
 263                                   0x02000000 0 0xe0000000
 264                                   0 0x20000000
 265
 266                                   0x01000000 0 0x00000000
 267                                   0x01000000 0 0x00000000
 268                                   0 0x00010000>;
 269                 };
 270         };
 271         rio: rapidio@ffe0c0000 {
 272                 reg = <0xf 0xfe0c0000 0 0x11000>;
 273
 274                 port1 {
 275                         ranges = <0 0 0xc 0x20000000 0 0x10000000>;
 276                 };
 277                 port2 {
 278                         ranges = <0 0 0xc 0x30000000 0 0x10000000>;
 279                 };
 280         };
 281 };
 282
 283 /include/ "fsl/t4240si-post.dtsi"