arch/powerpc/boot/dts/kmcoge4.dts

   1 /*
   2  * Keymile kmcoge4 Device Tree Source, based on the P2041RDB DTS
   3  *
   4  * (C) Copyright 2014
   5  * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
   6  *
   7  * Copyright 2011 Freescale Semiconductor Inc.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 /include/ "fsl/p2041si-pre.dtsi"
  16
  17 / {
  18         model = "keymile,kmcoge4";
  19         compatible = "keymile,kmcoge4", "keymile,kmp204x";
  20         #address-cells = <2>;
  21         #size-cells = <2>;
  22         interrupt-parent = <&mpic>;
  23
  24         memory {
  25                 device_type = "memory";
  26         };
  27
  28         dcsr: dcsr@f00000000 {
  29                 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
  30         };
  31
  32         soc: soc@ffe000000 {
  33                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  34                 reg = <0xf 0xfe000000 0 0x00001000>;
  35                 spi@110000 {
  36                         flash@0 {
  37                                 #address-cells = <1>;
  38                                 #size-cells = <1>;
  39                                 compatible = "spansion,s25fl256s1";
  40                                 reg = <0>;
  41                                 spi-max-frequency = <20000000>; /* input clock */
  42                         };
  43
  44                         network_clock@1 {
  45                                 compatible = "zarlink,zl30343";
  46                                 reg = <1>;
  47                                 spi-max-frequency = <8000000>;
  48                         };
  49
  50                         flash@2 {
  51                                 #address-cells = <1>;
  52                                 #size-cells = <1>;
  53                                 compatible = "micron,m25p32";
  54                                 reg = <2>;
  55                                 spi-max-frequency = <15000000>;
  56                         };
  57                 };
  58
  59                 i2c@119000 {
  60                         status = "disabled";
  61                 };
  62
  63                 i2c@119100 {
  64                         status = "disabled";
  65                 };
  66
  67                 usb0: usb@210000 {
  68                         status = "disabled";
  69                 };
  70
  71                 usb1: usb@211000 {
  72                         status = "disabled";
  73                 };
  74
  75                 sata@220000 {
  76                         status = "disabled";
  77                 };
  78
  79                 sata@221000 {
  80                         status = "disabled";
  81                 };
  82         };
  83
  84         rio: rapidio@ffe0c0000 {
  85                 status = "disabled";
  86         };
  87
  88         lbc: localbus@ffe124000 {
  89                 reg = <0xf 0xfe124000 0 0x1000>;
  90                 ranges = <0 0 0xf 0xffa00000 0x00040000         /* LB 0 */
  91                           1 0 0xf 0xfb000000 0x00010000         /* LB 1 */
  92                           2 0 0xf 0xd0000000 0x10000000         /* LB 2 */
  93                           3 0 0xf 0xe0000000 0x10000000>;       /* LB 3 */
  94
  95                 nand@0,0 {
  96                         #address-cells = <1>;
  97                         #size-cells = <1>;
  98                         compatible = "fsl,elbc-fcm-nand";
  99                         reg = <0 0 0x40000>;
 100                 };
 101
 102                 board-control@1,0 {
 103                         compatible = "keymile,qriox";
 104                         reg = <1 0 0x80>;
 105                 };
 106
 107                 chassis-mgmt@3,0 {
 108                         compatible = "keymile,bfticu";
 109                         interrupt-controller;
 110                         #interrupt-cells = <2>;
 111                         reg = <3 0 0x100>;
 112                         interrupt-parent = <&mpic>;
 113                         interrupts = <6 1 0 0>;
 114                 };
 115         };
 116
 117         pci0: pcie@ffe200000 {
 118                 reg = <0xf 0xfe200000 0 0x1000>;
 119                 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
 120                           0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
 121                 pcie@0 {
 122                         ranges = <0x02000000 0 0xe0000000
 123                                   0x02000000 0 0xe0000000
 124                                   0 0x20000000
 125
 126                                   0x01000000 0 0x00000000
 127                                   0x01000000 0 0x00000000
 128                                   0 0x00010000>;
 129                 };
 130         };
 131
 132         pci1: pcie@ffe201000 {
 133                 status = "disabled";
 134         };
 135
 136         pci2: pcie@ffe202000 {
 137                 reg = <0xf 0xfe202000 0 0x1000>;
 138                 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x20000000
 139                           0x01000000 0 0x00000000 0xf 0xf8010000 0 0x00010000>;
 140                 pcie@0 {
 141                         ranges = <0x02000000 0 0xe0000000
 142                                   0x02000000 0 0xe0000000
 143                                   0 0x20000000
 144
 145                                   0x01000000 0 0x00000000
 146                                   0x01000000 0 0x00000000
 147                                   0 0x00010000>;
 148                 };
 149         };
 150 };
 151
 152 /include/ "fsl/p2041si-post.dtsi"