arch/powerpc/boot/dts/fsl/p1021si-post.dtsi

   1 /*
   2  * P1021/P1012 Silicon/SoC Device Tree Source (post include)
   3  *
   4  * Copyright 2011-2012 Freescale Semiconductor Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are met:
   8  *     * Redistributions of source code must retain the above copyright
   9  *       notice, this list of conditions and the following disclaimer.
  10  *     * Redistributions in binary form must reproduce the above copyright
  11  *       notice, this list of conditions and the following disclaimer in the
  12  *       documentation and/or other materials provided with the distribution.
  13  *     * Neither the name of Freescale Semiconductor nor the
  14  *       names of its contributors may be used to endorse or promote products
  15  *       derived from this software without specific prior written permission.
  16  *
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation, either version 2 of that License or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  24  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  25  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  27  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  28  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  29  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  30  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  32  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  */
  34
  35 &lbc {
  36         #address-cells = <2>;
  37         #size-cells = <1>;
  38         compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
  39         interrupts = <19 2 0 0>;
  40 };
  41
  42 /* controller at 0x9000 */
  43 &pci0 {
  44         compatible = "fsl,mpc8548-pcie";
  45         device_type = "pci";
  46         #size-cells = <2>;
  47         #address-cells = <3>;
  48         bus-range = <0 255>;
  49         clock-frequency = <33333333>;
  50         interrupts = <16 2 0 0>;
  51
  52         pcie@0 {
  53                 reg = <0 0 0 0 0>;
  54                 #interrupt-cells = <1>;
  55                 #size-cells = <2>;
  56                 #address-cells = <3>;
  57                 device_type = "pci";
  58                 interrupts = <16 2 0 0>;
  59                 interrupt-map-mask = <0xf800 0 0 7>;
  60                 interrupt-map = <
  61                         /* IDSEL 0x0 */
  62                         0000 0x0 0x0 0x1 &mpic 0x4 0x1 0x0 0x0
  63                         0000 0x0 0x0 0x2 &mpic 0x5 0x1 0x0 0x0
  64                         0000 0x0 0x0 0x3 &mpic 0x6 0x1 0x0 0x0
  65                         0000 0x0 0x0 0x4 &mpic 0x7 0x1 0x0 0x0
  66                         >;
  67         };
  68 };
  69
  70 /* controller at 0xa000 */
  71 &pci1 {
  72         compatible = "fsl,mpc8548-pcie";
  73         device_type = "pci";
  74         #size-cells = <2>;
  75         #address-cells = <3>;
  76         bus-range = <0 255>;
  77         clock-frequency = <33333333>;
  78         interrupts = <16 2 0 0>;
  79
  80         pcie@0 {
  81                 reg = <0 0 0 0 0>;
  82                 #interrupt-cells = <1>;
  83                 #size-cells = <2>;
  84                 #address-cells = <3>;
  85                 device_type = "pci";
  86                 interrupts = <16 2 0 0>;
  87                 interrupt-map-mask = <0xf800 0 0 7>;
  88
  89                 interrupt-map = <
  90                         /* IDSEL 0x0 */
  91                         0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0
  92                         0000 0x0 0x0 0x2 &mpic 0x1 0x1 0x0 0x0
  93                         0000 0x0 0x0 0x3 &mpic 0x2 0x1 0x0 0x0
  94                         0000 0x0 0x0 0x4 &mpic 0x3 0x1 0x0 0x0
  95                         >;
  96         };
  97 };
  98
  99 &soc {
 100         #address-cells = <1>;
 101         #size-cells = <1>;
 102         device_type = "soc";
 103         compatible = "fsl,p1021-immr", "simple-bus";
 104         bus-frequency = <0>;            // Filled out by uboot.
 105
 106         ecm-law@0 {
 107                 compatible = "fsl,ecm-law";
 108                 reg = <0x0 0x1000>;
 109                 fsl,num-laws = <12>;
 110         };
 111
 112         ecm@1000 {
 113                 compatible = "fsl,p1021-ecm", "fsl,ecm";
 114                 reg = <0x1000 0x1000>;
 115                 interrupts = <16 2 0 0>;
 116         };
 117
 118         memory-controller@2000 {
 119                 compatible = "fsl,p1021-memory-controller";
 120                 reg = <0x2000 0x1000>;
 121                 interrupts = <16 2 0 0>;
 122         };
 123
 124 /include/ "pq3-i2c-0.dtsi"
 125 /include/ "pq3-i2c-1.dtsi"
 126 /include/ "pq3-duart-0.dtsi"
 127
 128 /include/ "pq3-espi-0.dtsi"
 129         spi@7000 {
 130                 fsl,espi-num-chipselects = <4>;
 131         };
 132
 133 /include/ "pq3-gpio-0.dtsi"
 134
 135         L2: l2-cache-controller@20000 {
 136                 compatible = "fsl,p1021-l2-cache-controller";
 137                 reg = <0x20000 0x1000>;
 138                 cache-line-size = <32>; // 32 bytes
 139                 cache-size = <0x40000>; // L2,256K
 140                 interrupts = <16 2 0 0>;
 141         };
 142
 143 /include/ "pq3-dma-0.dtsi"
 144 /include/ "pq3-usb2-dr-0.dtsi"
 145         usb@22000 {
 146                 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
 147         };
 148
 149 /include/ "pq3-esdhc-0.dtsi"
 150         sdhc@2e000 {
 151                 sdhci,auto-cmd12;
 152         };
 153
 154 /include/ "pq3-sec3.3-0.dtsi"
 155
 156 /include/ "pq3-mpic.dtsi"
 157 /include/ "pq3-mpic-timer-B.dtsi"
 158
 159 /include/ "pq3-etsec2-0.dtsi"
 160         enet0: enet0_grp2: ethernet@b0000 {
 161         };
 162
 163 /include/ "pq3-etsec2-1.dtsi"
 164         enet1: enet1_grp2: ethernet@b1000 {
 165         };
 166
 167 /include/ "pq3-etsec2-2.dtsi"
 168         enet2: enet2_grp2: ethernet@b2000 {
 169         };
 170
 171         global-utilities@e0000 {
 172                 compatible = "fsl,p1021-guts";
 173                 reg = <0xe0000 0x1000>;
 174                 fsl,has-rstcr;
 175         };
 176 };
 177
 178 &qe {
 179         #address-cells = <1>;
 180         #size-cells = <1>;
 181         device_type = "qe";
 182         compatible = "fsl,qe";
 183         fsl,qe-num-riscs = <1>;
 184         fsl,qe-num-snums = <28>;
 185
 186         qeic: interrupt-controller@80 {
 187                 interrupt-controller;
 188                 compatible = "fsl,qe-ic";
 189                 #address-cells = <0>;
 190                 #interrupt-cells = <1>;
 191                 reg = <0x80 0x80>;
 192                 interrupts = <63 2 0 0 60 2 0 0>; //high:47 low:44
 193         };
 194
 195         ucc@2000 {
 196                 cell-index = <1>;
 197                 reg = <0x2000 0x200>;
 198                 interrupts = <32>;
 199                 interrupt-parent = <&qeic>;
 200         };
 201
 202         mdio@2120 {
 203                 #address-cells = <1>;
 204                 #size-cells = <0>;
 205                 reg = <0x2120 0x18>;
 206                 compatible = "fsl,ucc-mdio";
 207         };
 208
 209         ucc@2400 {
 210                 cell-index = <5>;
 211                 reg = <0x2400 0x200>;
 212                 interrupts = <40>;
 213                 interrupt-parent = <&qeic>;
 214         };
 215
 216         ucc@2600 {
 217                 cell-index = <7>;
 218                 reg = <0x2600 0x200>;
 219                 interrupts = <42>;
 220                 interrupt-parent = <&qeic>;
 221         };
 222
 223         ucc@2200 {
 224                 cell-index = <3>;
 225                 reg = <0x2200 0x200>;
 226                 interrupts = <34>;
 227                 interrupt-parent = <&qeic>;
 228         };
 229
 230         muram@10000 {
 231                 #address-cells = <1>;
 232                 #size-cells = <1>;
 233                 compatible = "fsl,qe-muram", "fsl,cpm-muram";
 234                 ranges = <0x0 0x10000 0x6000>;
 235
 236                 data-only@0 {
 237                         compatible = "fsl,qe-muram-data",
 238                         "fsl,cpm-muram-data";
 239                         reg = <0x0 0x6000>;
 240                 };
 241         };
 242 };
 243
 244 /include/ "pq3-etsec2-grp2-0.dtsi"
 245 /include/ "pq3-etsec2-grp2-1.dtsi"
 246 /include/ "pq3-etsec2-grp2-2.dtsi"