2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Main entry point for the guest, exception handling.
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
13 #include <asm/asmmacro.h>
14 #include <asm/regdef.h>
15 #include <asm/mipsregs.h>
16 #include <asm/stackframe.h>
17 #include <asm/asm-offsets.h>
20 #define MIPSX(name) mips32_ ## name
21 #define CALLFRAME_SIZ 32
25 * exception vector entrypoint
27 #define VECTOR(x, regmask) \
31 #define VECTOR_END(x) \
34 /* Overload, Danger Will Robinson!! */
35 #define PT_HOST_ASID PT_BVADDR
36 #define PT_HOST_USERLOCAL PT_EPC
38 #define CP0_DDATA_LO $28,3
39 #define CP0_EBASE $15,1
41 #define CP0_INTCTL $12,1
42 #define CP0_SRSCTL $12,2
43 #define CP0_SRSMAP $12,3
44 #define CP0_HWRENA $7,0
47 #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
49 #define RESUME_GUEST 0
50 #define RESUME_HOST RESUME_FLAG_HOST
53 * __kvm_mips_vcpu_run: entry point to the guest
60 FEXPORT(__kvm_mips_vcpu_run)
61 /* k0/k1 not being used in host kernel context */
62 INT_ADDIU k1, sp, -PT_SIZE
75 LONG_S $10, PT_R10(k1)
76 LONG_S $11, PT_R11(k1)
77 LONG_S $12, PT_R12(k1)
78 LONG_S $13, PT_R13(k1)
79 LONG_S $14, PT_R14(k1)
80 LONG_S $15, PT_R15(k1)
81 LONG_S $16, PT_R16(k1)
82 LONG_S $17, PT_R17(k1)
84 LONG_S $18, PT_R18(k1)
85 LONG_S $19, PT_R19(k1)
86 LONG_S $20, PT_R20(k1)
87 LONG_S $21, PT_R21(k1)
88 LONG_S $22, PT_R22(k1)
89 LONG_S $23, PT_R23(k1)
90 LONG_S $24, PT_R24(k1)
91 LONG_S $25, PT_R25(k1)
94 * XXXKYMA k0/k1 not saved, not being used if we got here through
98 LONG_S $28, PT_R28(k1)
99 LONG_S $29, PT_R29(k1)
100 LONG_S $30, PT_R30(k1)
101 LONG_S $31, PT_R31(k1)
109 /* Save host status */
111 LONG_S v0, PT_STATUS(k1)
113 /* Save host ASID, shove it into the BVADDR location */
116 LONG_S v1, PT_HOST_ASID(k1)
118 /* Save DDATA_LO, will be used to store pointer to vcpu */
119 mfc0 v1, CP0_DDATA_LO
120 LONG_S v1, PT_HOST_USERLOCAL(k1)
122 /* DDATA_LO has pointer to vcpu */
123 mtc0 a1, CP0_DDATA_LO
125 /* Offset into vcpu->arch */
126 INT_ADDIU k1, a1, VCPU_HOST_ARCH
129 * Save the host stack to VCPU, used for exception processing
130 * when we exit from the Guest
132 LONG_S sp, VCPU_HOST_STACK(k1)
134 /* Save the kernel gp as well */
135 LONG_S gp, VCPU_HOST_GP(k1)
138 * Setup status register for running the guest in UM, interrupts
141 li k0, (ST0_EXL | KSU_USER | ST0_BEV)
145 /* load up the new EBASE */
146 LONG_L k0, VCPU_GUEST_EBASE(k1)
150 * Now that the new EBASE has been loaded, unset BEV, set
151 * interrupt mask as it was but make sure that timer interrupts
154 li k0, (ST0_EXL | KSU_USER | ST0_IE)
161 LONG_L t0, VCPU_PC(k1)
164 FEXPORT(__kvm_mips_load_asid)
165 /* Set the ASID for the Guest Kernel */
166 INT_SLL t0, t0, 1 /* with kseg0 @ 0x40000000, kernel */
167 /* addresses shift to 0x80000000 */
168 bltz t0, 1f /* If kernel */
169 INT_ADDIU t1, k1, VCPU_GUEST_KERNEL_ASID /* (BD) */
170 INT_ADDIU t1, k1, VCPU_GUEST_USER_ASID /* else user */
172 /* t1: contains the base of the ASID array, need to get the cpu id */
173 LONG_L t2, TI_CPU($28) /* smp_processor_id */
174 INT_SLL t2, t2, 2 /* x4 */
181 /* Disable RDHWR access */
182 mtc0 zero, CP0_HWRENA
184 /* Now load up the Guest Context from VCPU */
185 LONG_L $1, VCPU_R1(k1)
186 LONG_L $2, VCPU_R2(k1)
187 LONG_L $3, VCPU_R3(k1)
189 LONG_L $4, VCPU_R4(k1)
190 LONG_L $5, VCPU_R5(k1)
191 LONG_L $6, VCPU_R6(k1)
192 LONG_L $7, VCPU_R7(k1)
194 LONG_L $8, VCPU_R8(k1)
195 LONG_L $9, VCPU_R9(k1)
196 LONG_L $10, VCPU_R10(k1)
197 LONG_L $11, VCPU_R11(k1)
198 LONG_L $12, VCPU_R12(k1)
199 LONG_L $13, VCPU_R13(k1)
200 LONG_L $14, VCPU_R14(k1)
201 LONG_L $15, VCPU_R15(k1)
202 LONG_L $16, VCPU_R16(k1)
203 LONG_L $17, VCPU_R17(k1)
204 LONG_L $18, VCPU_R18(k1)
205 LONG_L $19, VCPU_R19(k1)
206 LONG_L $20, VCPU_R20(k1)
207 LONG_L $21, VCPU_R21(k1)
208 LONG_L $22, VCPU_R22(k1)
209 LONG_L $23, VCPU_R23(k1)
210 LONG_L $24, VCPU_R24(k1)
211 LONG_L $25, VCPU_R25(k1)
213 /* k0/k1 loaded up later */
215 LONG_L $28, VCPU_R28(k1)
216 LONG_L $29, VCPU_R29(k1)
217 LONG_L $30, VCPU_R30(k1)
218 LONG_L $31, VCPU_R31(k1)
221 LONG_L k0, VCPU_LO(k1)
224 LONG_L k0, VCPU_HI(k1)
227 FEXPORT(__kvm_mips_load_k0k1)
228 /* Restore the guest's k0/k1 registers */
229 LONG_L k0, VCPU_R26(k1)
230 LONG_L k1, VCPU_R27(k1)
234 EXPORT(__kvm_mips_vcpu_run_end)
236 VECTOR(MIPSX(exception), unknown)
237 /* Find out what mode we came from and jump to the proper handler. */
238 mtc0 k0, CP0_ERROREPC #01: Save guest k0
241 mfc0 k0, CP0_EBASE #02: Get EBASE
242 INT_SRL k0, k0, 10 #03: Get rid of CPUNum
243 INT_SLL k0, k0, 10 #04
244 LONG_S k1, 0x3000(k0) #05: Save k1 @ offset 0x3000
245 INT_ADDIU k0, k0, 0x2000 #06: Exception handler is
246 # installed @ offset 0x2000
247 j k0 #07: jump to the function
248 nop #08: branch delay slot
249 VECTOR_END(MIPSX(exceptionEnd))
250 .end MIPSX(exception)
253 * Generic Guest exception handler. We end up here when the guest
254 * does something that causes a trap to kernel mode.
256 NESTED (MIPSX(GuestException), CALLFRAME_SIZ, ra)
257 /* Get the VCPU pointer from DDTATA_LO */
258 mfc0 k1, CP0_DDATA_LO
259 INT_ADDIU k1, k1, VCPU_HOST_ARCH
261 /* Start saving Guest context to VCPU */
262 LONG_S $0, VCPU_R0(k1)
263 LONG_S $1, VCPU_R1(k1)
264 LONG_S $2, VCPU_R2(k1)
265 LONG_S $3, VCPU_R3(k1)
266 LONG_S $4, VCPU_R4(k1)
267 LONG_S $5, VCPU_R5(k1)
268 LONG_S $6, VCPU_R6(k1)
269 LONG_S $7, VCPU_R7(k1)
270 LONG_S $8, VCPU_R8(k1)
271 LONG_S $9, VCPU_R9(k1)
272 LONG_S $10, VCPU_R10(k1)
273 LONG_S $11, VCPU_R11(k1)
274 LONG_S $12, VCPU_R12(k1)
275 LONG_S $13, VCPU_R13(k1)
276 LONG_S $14, VCPU_R14(k1)
277 LONG_S $15, VCPU_R15(k1)
278 LONG_S $16, VCPU_R16(k1)
279 LONG_S $17, VCPU_R17(k1)
280 LONG_S $18, VCPU_R18(k1)
281 LONG_S $19, VCPU_R19(k1)
282 LONG_S $20, VCPU_R20(k1)
283 LONG_S $21, VCPU_R21(k1)
284 LONG_S $22, VCPU_R22(k1)
285 LONG_S $23, VCPU_R23(k1)
286 LONG_S $24, VCPU_R24(k1)
287 LONG_S $25, VCPU_R25(k1)
289 /* Guest k0/k1 saved later */
291 LONG_S $28, VCPU_R28(k1)
292 LONG_S $29, VCPU_R29(k1)
293 LONG_S $30, VCPU_R30(k1)
294 LONG_S $31, VCPU_R31(k1)
296 /* We need to save hi/lo and restore them on the way out */
298 LONG_S t0, VCPU_HI(k1)
301 LONG_S t0, VCPU_LO(k1)
303 /* Finally save guest k0/k1 to VCPU */
304 mfc0 t0, CP0_ERROREPC
305 LONG_S t0, VCPU_R26(k1)
307 /* Get GUEST k1 and save it in VCPU */
311 LONG_L t0, 0x3000(t0)
312 LONG_S t0, VCPU_R27(k1)
314 /* Now that context has been saved, we can use other registers */
317 mfc0 a1, CP0_DDATA_LO
320 /* Restore run (vcpu->run) */
321 LONG_L a0, VCPU_RUN(a1)
322 /* Save pointer to run in s0, will be saved by the compiler */
326 * Save Host level EPC, BadVaddr and Cause to VCPU, useful to
327 * process the exception
330 LONG_S k0, VCPU_PC(k1)
332 mfc0 k0, CP0_BADVADDR
333 LONG_S k0, VCPU_HOST_CP0_BADVADDR(k1)
336 LONG_S k0, VCPU_HOST_CP0_CAUSE(k1)
339 LONG_S k0, VCPU_HOST_ENTRYHI(k1)
341 /* Now restore the host state just enough to run the handlers */
343 /* Swtich EBASE to the one used by Linux */
344 /* load up the host EBASE */
354 LONG_L k0, VCPU_HOST_EBASE(k1)
357 /* Now that the new EBASE has been loaded, unset BEV and KSU_USER */
359 and v0, v0, ~(ST0_EXL | KSU_USER | ST0_IE)
365 /* Load up host GP */
366 LONG_L gp, VCPU_HOST_GP(k1)
368 /* Need a stack before we can jump to "C" */
369 LONG_L sp, VCPU_HOST_STACK(k1)
371 /* Saved host state */
372 INT_ADDIU sp, sp, -PT_SIZE
375 * XXXKYMA do we need to load the host ASID, maybe not because the
376 * kernel entries are marked GLOBAL, need to verify
379 /* Restore host DDATA_LO */
380 LONG_L k0, PT_HOST_USERLOCAL(sp)
381 mtc0 k0, CP0_DDATA_LO
383 /* Restore RDHWR access */
384 PTR_LI k0, 0x2000000F
387 /* Jump to handler */
388 FEXPORT(__kvm_mips_jump_to_handler)
390 * XXXKYMA: not sure if this is safe, how large is the stack??
391 * Now jump to the kvm_mips_handle_exit() to see if we can deal
392 * with this in the kernel
394 PTR_LA t9, kvm_mips_handle_exit
396 INT_ADDIU sp, sp, -CALLFRAME_SIZ /* BD Slot */
398 /* Return from handler Make sure interrupts are disabled */
403 * XXXKYMA: k0/k1 could have been blown away if we processed
404 * an exception while we were handling the exception from the
409 INT_ADDIU k1, k1, VCPU_HOST_ARCH
412 * Check return value, should tell us if we are returning to the
413 * host (handle I/O etc)or resuming the guest
415 andi t0, v0, RESUME_HOST
416 bnez t0, __kvm_mips_return_to_host
419 __kvm_mips_return_to_guest:
420 /* Put the saved pointer to vcpu (s1) back into the DDATA_LO Register */
421 mtc0 s1, CP0_DDATA_LO
423 /* Load up the Guest EBASE to minimize the window where BEV is set */
424 LONG_L t0, VCPU_GUEST_EBASE(k1)
426 /* Switch EBASE back to the one used by KVM */
435 /* Setup status register for running guest in UM */
437 or v1, v1, (ST0_EXL | KSU_USER | ST0_IE)
438 and v1, v1, ~(ST0_CU0 | ST0_MX)
444 LONG_L t0, VCPU_PC(k1)
447 /* Set the ASID for the Guest Kernel */
448 INT_SLL t0, t0, 1 /* with kseg0 @ 0x40000000, kernel */
449 /* addresses shift to 0x80000000 */
450 bltz t0, 1f /* If kernel */
451 INT_ADDIU t1, k1, VCPU_GUEST_KERNEL_ASID /* (BD) */
452 INT_ADDIU t1, k1, VCPU_GUEST_USER_ASID /* else user */
454 /* t1: contains the base of the ASID array, need to get the cpu id */
455 LONG_L t2, TI_CPU($28) /* smp_processor_id */
456 INT_SLL t2, t2, 2 /* x4 */
463 /* Disable RDHWR access */
464 mtc0 zero, CP0_HWRENA
466 /* load the guest context from VCPU and return */
467 LONG_L $0, VCPU_R0(k1)
468 LONG_L $1, VCPU_R1(k1)
469 LONG_L $2, VCPU_R2(k1)
470 LONG_L $3, VCPU_R3(k1)
471 LONG_L $4, VCPU_R4(k1)
472 LONG_L $5, VCPU_R5(k1)
473 LONG_L $6, VCPU_R6(k1)
474 LONG_L $7, VCPU_R7(k1)
475 LONG_L $8, VCPU_R8(k1)
476 LONG_L $9, VCPU_R9(k1)
477 LONG_L $10, VCPU_R10(k1)
478 LONG_L $11, VCPU_R11(k1)
479 LONG_L $12, VCPU_R12(k1)
480 LONG_L $13, VCPU_R13(k1)
481 LONG_L $14, VCPU_R14(k1)
482 LONG_L $15, VCPU_R15(k1)
483 LONG_L $16, VCPU_R16(k1)
484 LONG_L $17, VCPU_R17(k1)
485 LONG_L $18, VCPU_R18(k1)
486 LONG_L $19, VCPU_R19(k1)
487 LONG_L $20, VCPU_R20(k1)
488 LONG_L $21, VCPU_R21(k1)
489 LONG_L $22, VCPU_R22(k1)
490 LONG_L $23, VCPU_R23(k1)
491 LONG_L $24, VCPU_R24(k1)
492 LONG_L $25, VCPU_R25(k1)
494 /* $/k1 loaded later */
495 LONG_L $28, VCPU_R28(k1)
496 LONG_L $29, VCPU_R29(k1)
497 LONG_L $30, VCPU_R30(k1)
498 LONG_L $31, VCPU_R31(k1)
500 FEXPORT(__kvm_mips_skip_guest_restore)
501 LONG_L k0, VCPU_HI(k1)
504 LONG_L k0, VCPU_LO(k1)
507 LONG_L k0, VCPU_R26(k1)
508 LONG_L k1, VCPU_R27(k1)
512 __kvm_mips_return_to_host:
513 /* EBASE is already pointing to Linux */
514 LONG_L k1, VCPU_HOST_STACK(k1)
515 INT_ADDIU k1,k1, -PT_SIZE
517 /* Restore host DDATA_LO */
518 LONG_L k0, PT_HOST_USERLOCAL(k1)
519 mtc0 k0, CP0_DDATA_LO
521 /* Restore host ASID */
522 LONG_L k0, PT_HOST_ASID(sp)
527 /* Load context saved on the host stack */
532 * r2/v0 is the return code, shift it down by 2 (arithmetic)
533 * to recover the err code
545 LONG_L $10, PT_R10(k1)
546 LONG_L $11, PT_R11(k1)
547 LONG_L $12, PT_R12(k1)
548 LONG_L $13, PT_R13(k1)
549 LONG_L $14, PT_R14(k1)
550 LONG_L $15, PT_R15(k1)
551 LONG_L $16, PT_R16(k1)
552 LONG_L $17, PT_R17(k1)
553 LONG_L $18, PT_R18(k1)
554 LONG_L $19, PT_R19(k1)
555 LONG_L $20, PT_R20(k1)
556 LONG_L $21, PT_R21(k1)
557 LONG_L $22, PT_R22(k1)
558 LONG_L $23, PT_R23(k1)
559 LONG_L $24, PT_R24(k1)
560 LONG_L $25, PT_R25(k1)
562 /* Host k0/k1 were not saved */
564 LONG_L $28, PT_R28(k1)
565 LONG_L $29, PT_R29(k1)
566 LONG_L $30, PT_R30(k1)
574 /* Restore RDHWR access */
575 PTR_LI k0, 0x2000000F
578 /* Restore RA, which is the address we will return to */
579 LONG_L ra, PT_R31(k1)
583 VECTOR_END(MIPSX(GuestExceptionEnd))
584 .end MIPSX(GuestException)
588 ##### The exception handlers.
590 .word _C_LABEL(MIPSX(GuestException)) # 0
591 .word _C_LABEL(MIPSX(GuestException)) # 1
592 .word _C_LABEL(MIPSX(GuestException)) # 2
593 .word _C_LABEL(MIPSX(GuestException)) # 3
594 .word _C_LABEL(MIPSX(GuestException)) # 4
595 .word _C_LABEL(MIPSX(GuestException)) # 5
596 .word _C_LABEL(MIPSX(GuestException)) # 6
597 .word _C_LABEL(MIPSX(GuestException)) # 7
598 .word _C_LABEL(MIPSX(GuestException)) # 8
599 .word _C_LABEL(MIPSX(GuestException)) # 9
600 .word _C_LABEL(MIPSX(GuestException)) # 10
601 .word _C_LABEL(MIPSX(GuestException)) # 11
602 .word _C_LABEL(MIPSX(GuestException)) # 12
603 .word _C_LABEL(MIPSX(GuestException)) # 13
604 .word _C_LABEL(MIPSX(GuestException)) # 14
605 .word _C_LABEL(MIPSX(GuestException)) # 15
606 .word _C_LABEL(MIPSX(GuestException)) # 16
607 .word _C_LABEL(MIPSX(GuestException)) # 17
608 .word _C_LABEL(MIPSX(GuestException)) # 18
609 .word _C_LABEL(MIPSX(GuestException)) # 19
610 .word _C_LABEL(MIPSX(GuestException)) # 20
611 .word _C_LABEL(MIPSX(GuestException)) # 21
612 .word _C_LABEL(MIPSX(GuestException)) # 22
613 .word _C_LABEL(MIPSX(GuestException)) # 23
614 .word _C_LABEL(MIPSX(GuestException)) # 24
615 .word _C_LABEL(MIPSX(GuestException)) # 25
616 .word _C_LABEL(MIPSX(GuestException)) # 26
617 .word _C_LABEL(MIPSX(GuestException)) # 27
618 .word _C_LABEL(MIPSX(GuestException)) # 28
619 .word _C_LABEL(MIPSX(GuestException)) # 29
620 .word _C_LABEL(MIPSX(GuestException)) # 30
621 .word _C_LABEL(MIPSX(GuestException)) # 31