arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cpu-type.h>
  24 #include <asm/fpu.h>
  25 #include <asm/mipsregs.h>
  26 #include <asm/watch.h>
  27 #include <asm/elf.h>
  28 #include <asm/spram.h>
  29 #include <asm/uaccess.h>
  30
  31 static int mips_fpu_disabled;
  32
  33 static int __init fpu_disable(char *s)
  34 {
  35         cpu_data[0].options &= ~MIPS_CPU_FPU;
  36         mips_fpu_disabled = 1;
  37
  38         return 1;
  39 }
  40
  41 __setup("nofpu", fpu_disable);
  42
  43 int mips_dsp_disabled;
  44
  45 static int __init dsp_disable(char *s)
  46 {
  47         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
  48         mips_dsp_disabled = 1;
  49
  50         return 1;
  51 }
  52
  53 __setup("nodsp", dsp_disable);
  54
  55 static inline void check_errata(void)
  56 {
  57         struct cpuinfo_mips *c = &current_cpu_data;
  58
  59         switch (current_cpu_type()) {
  60         case CPU_34K:
  61                 /*
  62                  * Erratum "RPS May Cause Incorrect Instruction Execution"
  63                  * This code only handles VPE0, any SMP/SMTC/RTOS code
  64                  * making use of VPE1 will be responsable for that VPE.
  65                  */
  66                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
  67                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
  68                 break;
  69         default:
  70                 break;
  71         }
  72 }
  73
  74 void __init check_bugs32(void)
  75 {
  76         check_errata();
  77 }
  78
  79 /*
  80  * Probe whether cpu has config register by trying to play with
  81  * alternate cache bit and see whether it matters.
  82  * It's used by cpu_probe to distinguish between R3000A and R3081.
  83  */
  84 static inline int cpu_has_confreg(void)
  85 {
  86 #ifdef CONFIG_CPU_R3000
  87         extern unsigned long r3k_cache_size(unsigned long);
  88         unsigned long size1, size2;
  89         unsigned long cfg = read_c0_conf();
  90
  91         size1 = r3k_cache_size(ST0_ISC);
  92         write_c0_conf(cfg ^ R30XX_CONF_AC);
  93         size2 = r3k_cache_size(ST0_ISC);
  94         write_c0_conf(cfg);
  95         return size1 != size2;
  96 #else
  97         return 0;
  98 #endif
  99 }
 100
 101 static inline void set_elf_platform(int cpu, const char *plat)
 102 {
 103         if (cpu == 0)
 104                 __elf_platform = plat;
 105 }
 106
 107 /*
 108  * Get the FPU Implementation/Revision.
 109  */
 110 static inline unsigned long cpu_get_fpu_id(void)
 111 {
 112         unsigned long tmp, fpu_id;
 113
 114         tmp = read_c0_status();
 115         __enable_fpu();
 116         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 117         write_c0_status(tmp);
 118         return fpu_id;
 119 }
 120
 121 /*
 122  * Check the CPU has an FPU the official way.
 123  */
 124 static inline int __cpu_has_fpu(void)
 125 {
 126         return ((cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE);
 127 }
 128
 129 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 130 {
 131 #ifdef __NEED_VMBITS_PROBE
 132         write_c0_entryhi(0x3fffffffffffe000ULL);
 133         back_to_back_c0_hazard();
 134         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 135 #endif
 136 }
 137
 138 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 139 {
 140         switch (isa) {
 141         case MIPS_CPU_ISA_M64R2:
 142                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 143         case MIPS_CPU_ISA_M64R1:
 144                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 145         case MIPS_CPU_ISA_V:
 146                 c->isa_level |= MIPS_CPU_ISA_V;
 147         case MIPS_CPU_ISA_IV:
 148                 c->isa_level |= MIPS_CPU_ISA_IV;
 149         case MIPS_CPU_ISA_III:
 150                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
 151                 break;
 152
 153         case MIPS_CPU_ISA_M32R2:
 154                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 155         case MIPS_CPU_ISA_M32R1:
 156                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 157         case MIPS_CPU_ISA_II:
 158                 c->isa_level |= MIPS_CPU_ISA_II;
 159                 break;
 160         }
 161 }
 162
 163 static char unknown_isa[] = KERN_ERR \
 164         "Unsupported ISA type, c0.config0: %d.";
 165
 166 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 167 {
 168         unsigned int config0;
 169         int isa;
 170
 171         config0 = read_c0_config();
 172
 173         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 174                 c->options |= MIPS_CPU_TLB;
 175         isa = (config0 & MIPS_CONF_AT) >> 13;
 176         switch (isa) {
 177         case 0:
 178                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 179                 case 0:
 180                         set_isa(c, MIPS_CPU_ISA_M32R1);
 181                         break;
 182                 case 1:
 183                         set_isa(c, MIPS_CPU_ISA_M32R2);
 184                         break;
 185                 default:
 186                         goto unknown;
 187                 }
 188                 break;
 189         case 2:
 190                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 191                 case 0:
 192                         set_isa(c, MIPS_CPU_ISA_M64R1);
 193                         break;
 194                 case 1:
 195                         set_isa(c, MIPS_CPU_ISA_M64R2);
 196                         break;
 197                 default:
 198                         goto unknown;
 199                 }
 200                 break;
 201         default:
 202                 goto unknown;
 203         }
 204
 205         return config0 & MIPS_CONF_M;
 206
 207 unknown:
 208         panic(unknown_isa, config0);
 209 }
 210
 211 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 212 {
 213         unsigned int config1;
 214
 215         config1 = read_c0_config1();
 216
 217         if (config1 & MIPS_CONF1_MD)
 218                 c->ases |= MIPS_ASE_MDMX;
 219         if (config1 & MIPS_CONF1_WR)
 220                 c->options |= MIPS_CPU_WATCH;
 221         if (config1 & MIPS_CONF1_CA)
 222                 c->ases |= MIPS_ASE_MIPS16;
 223         if (config1 & MIPS_CONF1_EP)
 224                 c->options |= MIPS_CPU_EJTAG;
 225         if (config1 & MIPS_CONF1_FP) {
 226                 c->options |= MIPS_CPU_FPU;
 227                 c->options |= MIPS_CPU_32FPR;
 228         }
 229         if (cpu_has_tlb)
 230                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 231
 232         return config1 & MIPS_CONF_M;
 233 }
 234
 235 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 236 {
 237         unsigned int config2;
 238
 239         config2 = read_c0_config2();
 240
 241         if (config2 & MIPS_CONF2_SL)
 242                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 243
 244         return config2 & MIPS_CONF_M;
 245 }
 246
 247 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 248 {
 249         unsigned int config3;
 250
 251         config3 = read_c0_config3();
 252
 253         if (config3 & MIPS_CONF3_SM) {
 254                 c->ases |= MIPS_ASE_SMARTMIPS;
 255                 c->options |= MIPS_CPU_RIXI;
 256         }
 257         if (config3 & MIPS_CONF3_RXI)
 258                 c->options |= MIPS_CPU_RIXI;
 259         if (config3 & MIPS_CONF3_DSP)
 260                 c->ases |= MIPS_ASE_DSP;
 261         if (config3 & MIPS_CONF3_DSP2P)
 262                 c->ases |= MIPS_ASE_DSP2P;
 263         if (config3 & MIPS_CONF3_VINT)
 264                 c->options |= MIPS_CPU_VINT;
 265         if (config3 & MIPS_CONF3_VEIC)
 266                 c->options |= MIPS_CPU_VEIC;
 267         if (config3 & MIPS_CONF3_MT)
 268                 c->ases |= MIPS_ASE_MIPSMT;
 269         if (config3 & MIPS_CONF3_ULRI)
 270                 c->options |= MIPS_CPU_ULRI;
 271         if (config3 & MIPS_CONF3_ISA)
 272                 c->options |= MIPS_CPU_MICROMIPS;
 273         if (config3 & MIPS_CONF3_VZ)
 274                 c->ases |= MIPS_ASE_VZ;
 275
 276         return config3 & MIPS_CONF_M;
 277 }
 278
 279 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 280 {
 281         unsigned int config4;
 282
 283         config4 = read_c0_config4();
 284
 285         if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
 286             && cpu_has_tlb)
 287                 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 288
 289         c->kscratch_mask = (config4 >> 16) & 0xff;
 290
 291         return config4 & MIPS_CONF_M;
 292 }
 293
 294 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 295 {
 296         unsigned int config5;
 297
 298         config5 = read_c0_config5();
 299         config5 &= ~MIPS_CONF5_UFR;
 300         write_c0_config5(config5);
 301
 302         return config5 & MIPS_CONF_M;
 303 }
 304
 305 static void decode_configs(struct cpuinfo_mips *c)
 306 {
 307         int ok;
 308
 309         /* MIPS32 or MIPS64 compliant CPU.  */
 310         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 311                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 312
 313         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 314
 315         ok = decode_config0(c);                 /* Read Config registers.  */
 316         BUG_ON(!ok);                            /* Arch spec violation!  */
 317         if (ok)
 318                 ok = decode_config1(c);
 319         if (ok)
 320                 ok = decode_config2(c);
 321         if (ok)
 322                 ok = decode_config3(c);
 323         if (ok)
 324                 ok = decode_config4(c);
 325         if (ok)
 326                 ok = decode_config5(c);
 327
 328         mips_probe_watch_registers(c);
 329
 330         if (cpu_has_mips_r2)
 331                 c->core = read_c0_ebase() & 0x3ff;
 332 }
 333
 334 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 335                 | MIPS_CPU_COUNTER)
 336
 337 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 338 {
 339         switch (c->processor_id & PRID_IMP_MASK) {
 340         case PRID_IMP_R2000:
 341                 c->cputype = CPU_R2000;
 342                 __cpu_name[cpu] = "R2000";
 343                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 344                              MIPS_CPU_NOFPUEX;
 345                 if (__cpu_has_fpu())
 346                         c->options |= MIPS_CPU_FPU;
 347                 c->tlbsize = 64;
 348                 break;
 349         case PRID_IMP_R3000:
 350                 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
 351                         if (cpu_has_confreg()) {
 352                                 c->cputype = CPU_R3081E;
 353                                 __cpu_name[cpu] = "R3081";
 354                         } else {
 355                                 c->cputype = CPU_R3000A;
 356                                 __cpu_name[cpu] = "R3000A";
 357                         }
 358                 } else {
 359                         c->cputype = CPU_R3000;
 360                         __cpu_name[cpu] = "R3000";
 361                 }
 362                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 363                              MIPS_CPU_NOFPUEX;
 364                 if (__cpu_has_fpu())
 365                         c->options |= MIPS_CPU_FPU;
 366                 c->tlbsize = 64;
 367                 break;
 368         case PRID_IMP_R4000:
 369                 if (read_c0_config() & CONF_SC) {
 370                         if ((c->processor_id & PRID_REV_MASK) >=
 371                             PRID_REV_R4400) {
 372                                 c->cputype = CPU_R4400PC;
 373                                 __cpu_name[cpu] = "R4400PC";
 374                         } else {
 375                                 c->cputype = CPU_R4000PC;
 376                                 __cpu_name[cpu] = "R4000PC";
 377                         }
 378                 } else {
 379                         if ((c->processor_id & PRID_REV_MASK) >=
 380                             PRID_REV_R4400) {
 381                                 c->cputype = CPU_R4400SC;
 382                                 __cpu_name[cpu] = "R4400SC";
 383                         } else {
 384                                 c->cputype = CPU_R4000SC;
 385                                 __cpu_name[cpu] = "R4000SC";
 386                         }
 387                 }
 388
 389                 set_isa(c, MIPS_CPU_ISA_III);
 390                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 391                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 392                              MIPS_CPU_LLSC;
 393                 c->tlbsize = 48;
 394                 break;
 395         case PRID_IMP_VR41XX:
 396                 set_isa(c, MIPS_CPU_ISA_III);
 397                 c->options = R4K_OPTS;
 398                 c->tlbsize = 32;
 399                 switch (c->processor_id & 0xf0) {
 400                 case PRID_REV_VR4111:
 401                         c->cputype = CPU_VR4111;
 402                         __cpu_name[cpu] = "NEC VR4111";
 403                         break;
 404                 case PRID_REV_VR4121:
 405                         c->cputype = CPU_VR4121;
 406                         __cpu_name[cpu] = "NEC VR4121";
 407                         break;
 408                 case PRID_REV_VR4122:
 409                         if ((c->processor_id & 0xf) < 0x3) {
 410                                 c->cputype = CPU_VR4122;
 411                                 __cpu_name[cpu] = "NEC VR4122";
 412                         } else {
 413                                 c->cputype = CPU_VR4181A;
 414                                 __cpu_name[cpu] = "NEC VR4181A";
 415                         }
 416                         break;
 417                 case PRID_REV_VR4130:
 418                         if ((c->processor_id & 0xf) < 0x4) {
 419                                 c->cputype = CPU_VR4131;
 420                                 __cpu_name[cpu] = "NEC VR4131";
 421                         } else {
 422                                 c->cputype = CPU_VR4133;
 423                                 c->options |= MIPS_CPU_LLSC;
 424                                 __cpu_name[cpu] = "NEC VR4133";
 425                         }
 426                         break;
 427                 default:
 428                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 429                         c->cputype = CPU_VR41XX;
 430                         __cpu_name[cpu] = "NEC Vr41xx";
 431                         break;
 432                 }
 433                 break;
 434         case PRID_IMP_R4300:
 435                 c->cputype = CPU_R4300;
 436                 __cpu_name[cpu] = "R4300";
 437                 set_isa(c, MIPS_CPU_ISA_III);
 438                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 439                              MIPS_CPU_LLSC;
 440                 c->tlbsize = 32;
 441                 break;
 442         case PRID_IMP_R4600:
 443                 c->cputype = CPU_R4600;
 444                 __cpu_name[cpu] = "R4600";
 445                 set_isa(c, MIPS_CPU_ISA_III);
 446                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 447                              MIPS_CPU_LLSC;
 448                 c->tlbsize = 48;
 449                 break;
 450         #if 0
 451         case PRID_IMP_R4650:
 452                 /*
 453                  * This processor doesn't have an MMU, so it's not
 454                  * "real easy" to run Linux on it. It is left purely
 455                  * for documentation.  Commented out because it shares
 456                  * it's c0_prid id number with the TX3900.
 457                  */
 458                 c->cputype = CPU_R4650;
 459                 __cpu_name[cpu] = "R4650";
 460                 set_isa(c, MIPS_CPU_ISA_III);
 461                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 462                 c->tlbsize = 48;
 463                 break;
 464         #endif
 465         case PRID_IMP_TX39:
 466                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 467
 468                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 469                         c->cputype = CPU_TX3927;
 470                         __cpu_name[cpu] = "TX3927";
 471                         c->tlbsize = 64;
 472                 } else {
 473                         switch (c->processor_id & PRID_REV_MASK) {
 474                         case PRID_REV_TX3912:
 475                                 c->cputype = CPU_TX3912;
 476                                 __cpu_name[cpu] = "TX3912";
 477                                 c->tlbsize = 32;
 478                                 break;
 479                         case PRID_REV_TX3922:
 480                                 c->cputype = CPU_TX3922;
 481                                 __cpu_name[cpu] = "TX3922";
 482                                 c->tlbsize = 64;
 483                                 break;
 484                         }
 485                 }
 486                 break;
 487         case PRID_IMP_R4700:
 488                 c->cputype = CPU_R4700;
 489                 __cpu_name[cpu] = "R4700";
 490                 set_isa(c, MIPS_CPU_ISA_III);
 491                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 492                              MIPS_CPU_LLSC;
 493                 c->tlbsize = 48;
 494                 break;
 495         case PRID_IMP_TX49:
 496                 c->cputype = CPU_TX49XX;
 497                 __cpu_name[cpu] = "R49XX";
 498                 set_isa(c, MIPS_CPU_ISA_III);
 499                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 500                 if (!(c->processor_id & 0x08))
 501                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 502                 c->tlbsize = 48;
 503                 break;
 504         case PRID_IMP_R5000:
 505                 c->cputype = CPU_R5000;
 506                 __cpu_name[cpu] = "R5000";
 507                 set_isa(c, MIPS_CPU_ISA_IV);
 508                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 509                              MIPS_CPU_LLSC;
 510                 c->tlbsize = 48;
 511                 break;
 512         case PRID_IMP_R5432:
 513                 c->cputype = CPU_R5432;
 514                 __cpu_name[cpu] = "R5432";
 515                 set_isa(c, MIPS_CPU_ISA_IV);
 516                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 517                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 518                 c->tlbsize = 48;
 519                 break;
 520         case PRID_IMP_R5500:
 521                 c->cputype = CPU_R5500;
 522                 __cpu_name[cpu] = "R5500";
 523                 set_isa(c, MIPS_CPU_ISA_IV);
 524                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 525                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 526                 c->tlbsize = 48;
 527                 break;
 528         case PRID_IMP_NEVADA:
 529                 c->cputype = CPU_NEVADA;
 530                 __cpu_name[cpu] = "Nevada";
 531                 set_isa(c, MIPS_CPU_ISA_IV);
 532                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 533                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 534                 c->tlbsize = 48;
 535                 break;
 536         case PRID_IMP_R6000:
 537                 c->cputype = CPU_R6000;
 538                 __cpu_name[cpu] = "R6000";
 539                 set_isa(c, MIPS_CPU_ISA_II);
 540                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 541                              MIPS_CPU_LLSC;
 542                 c->tlbsize = 32;
 543                 break;
 544         case PRID_IMP_R6000A:
 545                 c->cputype = CPU_R6000A;
 546                 __cpu_name[cpu] = "R6000A";
 547                 set_isa(c, MIPS_CPU_ISA_II);
 548                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 549                              MIPS_CPU_LLSC;
 550                 c->tlbsize = 32;
 551                 break;
 552         case PRID_IMP_RM7000:
 553                 c->cputype = CPU_RM7000;
 554                 __cpu_name[cpu] = "RM7000";
 555                 set_isa(c, MIPS_CPU_ISA_IV);
 556                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 557                              MIPS_CPU_LLSC;
 558                 /*
 559                  * Undocumented RM7000:  Bit 29 in the info register of
 560                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 561                  * entries.
 562                  *
 563                  * 29      1 =>    64 entry JTLB
 564                  *         0 =>    48 entry JTLB
 565                  */
 566                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 567                 break;
 568         case PRID_IMP_RM9000:
 569                 c->cputype = CPU_RM9000;
 570                 __cpu_name[cpu] = "RM9000";
 571                 set_isa(c, MIPS_CPU_ISA_IV);
 572                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 573                              MIPS_CPU_LLSC;
 574                 /*
 575                  * Bit 29 in the info register of the RM9000
 576                  * indicates if the TLB has 48 or 64 entries.
 577                  *
 578                  * 29      1 =>    64 entry JTLB
 579                  *         0 =>    48 entry JTLB
 580                  */
 581                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 582                 break;
 583         case PRID_IMP_R8000:
 584                 c->cputype = CPU_R8000;
 585                 __cpu_name[cpu] = "RM8000";
 586                 set_isa(c, MIPS_CPU_ISA_IV);
 587                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 588                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 589                              MIPS_CPU_LLSC;
 590                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 591                 break;
 592         case PRID_IMP_R10000:
 593                 c->cputype = CPU_R10000;
 594                 __cpu_name[cpu] = "R10000";
 595                 set_isa(c, MIPS_CPU_ISA_IV);
 596                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 597                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 598                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 599                              MIPS_CPU_LLSC;
 600                 c->tlbsize = 64;
 601                 break;
 602         case PRID_IMP_R12000:
 603                 c->cputype = CPU_R12000;
 604                 __cpu_name[cpu] = "R12000";
 605                 set_isa(c, MIPS_CPU_ISA_IV);
 606                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 607                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 608                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 609                              MIPS_CPU_LLSC;
 610                 c->tlbsize = 64;
 611                 break;
 612         case PRID_IMP_R14000:
 613                 c->cputype = CPU_R14000;
 614                 __cpu_name[cpu] = "R14000";
 615                 set_isa(c, MIPS_CPU_ISA_IV);
 616                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 617                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 618                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 619                              MIPS_CPU_LLSC;
 620                 c->tlbsize = 64;
 621                 break;
 622         case PRID_IMP_LOONGSON2:
 623                 c->cputype = CPU_LOONGSON2;
 624                 __cpu_name[cpu] = "ICT Loongson-2";
 625
 626                 switch (c->processor_id & PRID_REV_MASK) {
 627                 case PRID_REV_LOONGSON2E:
 628                         set_elf_platform(cpu, "loongson2e");
 629                         break;
 630                 case PRID_REV_LOONGSON2F:
 631                         set_elf_platform(cpu, "loongson2f");
 632                         break;
 633                 }
 634
 635                 set_isa(c, MIPS_CPU_ISA_III);
 636                 c->options = R4K_OPTS |
 637                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 638                              MIPS_CPU_32FPR;
 639                 c->tlbsize = 64;
 640                 break;
 641         case PRID_IMP_LOONGSON1:
 642                 decode_configs(c);
 643
 644                 c->cputype = CPU_LOONGSON1;
 645
 646                 switch (c->processor_id & PRID_REV_MASK) {
 647                 case PRID_REV_LOONGSON1B:
 648                         __cpu_name[cpu] = "Loongson 1B";
 649                         break;
 650                 }
 651
 652                 break;
 653         }
 654 }
 655
 656 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 657 {
 658         decode_configs(c);
 659         switch (c->processor_id & PRID_IMP_MASK) {
 660         case PRID_IMP_4KC:
 661                 c->cputype = CPU_4KC;
 662                 __cpu_name[cpu] = "MIPS 4Kc";
 663                 break;
 664         case PRID_IMP_4KEC:
 665         case PRID_IMP_4KECR2:
 666                 c->cputype = CPU_4KEC;
 667                 __cpu_name[cpu] = "MIPS 4KEc";
 668                 break;
 669         case PRID_IMP_4KSC:
 670         case PRID_IMP_4KSD:
 671                 c->cputype = CPU_4KSC;
 672                 __cpu_name[cpu] = "MIPS 4KSc";
 673                 break;
 674         case PRID_IMP_5KC:
 675                 c->cputype = CPU_5KC;
 676                 __cpu_name[cpu] = "MIPS 5Kc";
 677                 break;
 678         case PRID_IMP_5KE:
 679                 c->cputype = CPU_5KE;
 680                 __cpu_name[cpu] = "MIPS 5KE";
 681                 break;
 682         case PRID_IMP_20KC:
 683                 c->cputype = CPU_20KC;
 684                 __cpu_name[cpu] = "MIPS 20Kc";
 685                 break;
 686         case PRID_IMP_24K:
 687                 c->cputype = CPU_24K;
 688                 __cpu_name[cpu] = "MIPS 24Kc";
 689                 break;
 690         case PRID_IMP_24KE:
 691                 c->cputype = CPU_24K;
 692                 __cpu_name[cpu] = "MIPS 24KEc";
 693                 break;
 694         case PRID_IMP_25KF:
 695                 c->cputype = CPU_25KF;
 696                 __cpu_name[cpu] = "MIPS 25Kc";
 697                 break;
 698         case PRID_IMP_34K:
 699                 c->cputype = CPU_34K;
 700                 __cpu_name[cpu] = "MIPS 34Kc";
 701                 break;
 702         case PRID_IMP_74K:
 703                 c->cputype = CPU_74K;
 704                 __cpu_name[cpu] = "MIPS 74Kc";
 705                 break;
 706         case PRID_IMP_M14KC:
 707                 c->cputype = CPU_M14KC;
 708                 __cpu_name[cpu] = "MIPS M14Kc";
 709                 break;
 710         case PRID_IMP_M14KEC:
 711                 c->cputype = CPU_M14KEC;
 712                 __cpu_name[cpu] = "MIPS M14KEc";
 713                 break;
 714         case PRID_IMP_1004K:
 715                 c->cputype = CPU_1004K;
 716                 __cpu_name[cpu] = "MIPS 1004Kc";
 717                 break;
 718         case PRID_IMP_1074K:
 719                 c->cputype = CPU_74K;
 720                 __cpu_name[cpu] = "MIPS 1074Kc";
 721                 break;
 722         }
 723
 724         spram_config();
 725 }
 726
 727 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 728 {
 729         decode_configs(c);
 730         switch (c->processor_id & PRID_IMP_MASK) {
 731         case PRID_IMP_AU1_REV1:
 732         case PRID_IMP_AU1_REV2:
 733                 c->cputype = CPU_ALCHEMY;
 734                 switch ((c->processor_id >> 24) & 0xff) {
 735                 case 0:
 736                         __cpu_name[cpu] = "Au1000";
 737                         break;
 738                 case 1:
 739                         __cpu_name[cpu] = "Au1500";
 740                         break;
 741                 case 2:
 742                         __cpu_name[cpu] = "Au1100";
 743                         break;
 744                 case 3:
 745                         __cpu_name[cpu] = "Au1550";
 746                         break;
 747                 case 4:
 748                         __cpu_name[cpu] = "Au1200";
 749                         if ((c->processor_id & PRID_REV_MASK) == 2)
 750                                 __cpu_name[cpu] = "Au1250";
 751                         break;
 752                 case 5:
 753                         __cpu_name[cpu] = "Au1210";
 754                         break;
 755                 default:
 756                         __cpu_name[cpu] = "Au1xxx";
 757                         break;
 758                 }
 759                 break;
 760         }
 761 }
 762
 763 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 764 {
 765         decode_configs(c);
 766
 767         switch (c->processor_id & PRID_IMP_MASK) {
 768         case PRID_IMP_SB1:
 769                 c->cputype = CPU_SB1;
 770                 __cpu_name[cpu] = "SiByte SB1";
 771                 /* FPU in pass1 is known to have issues. */
 772                 if ((c->processor_id & PRID_REV_MASK) < 0x02)
 773                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 774                 break;
 775         case PRID_IMP_SB1A:
 776                 c->cputype = CPU_SB1A;
 777                 __cpu_name[cpu] = "SiByte SB1A";
 778                 break;
 779         }
 780 }
 781
 782 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 783 {
 784         decode_configs(c);
 785         switch (c->processor_id & PRID_IMP_MASK) {
 786         case PRID_IMP_SR71000:
 787                 c->cputype = CPU_SR71000;
 788                 __cpu_name[cpu] = "Sandcraft SR71000";
 789                 c->scache.ways = 8;
 790                 c->tlbsize = 64;
 791                 break;
 792         }
 793 }
 794
 795 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 796 {
 797         decode_configs(c);
 798         switch (c->processor_id & PRID_IMP_MASK) {
 799         case PRID_IMP_PR4450:
 800                 c->cputype = CPU_PR4450;
 801                 __cpu_name[cpu] = "Philips PR4450";
 802                 set_isa(c, MIPS_CPU_ISA_M32R1);
 803                 break;
 804         }
 805 }
 806
 807 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 808 {
 809         decode_configs(c);
 810         switch (c->processor_id & PRID_IMP_MASK) {
 811         case PRID_IMP_BMIPS32_REV4:
 812         case PRID_IMP_BMIPS32_REV8:
 813                 c->cputype = CPU_BMIPS32;
 814                 __cpu_name[cpu] = "Broadcom BMIPS32";
 815                 set_elf_platform(cpu, "bmips32");
 816                 break;
 817         case PRID_IMP_BMIPS3300:
 818         case PRID_IMP_BMIPS3300_ALT:
 819         case PRID_IMP_BMIPS3300_BUG:
 820                 c->cputype = CPU_BMIPS3300;
 821                 __cpu_name[cpu] = "Broadcom BMIPS3300";
 822                 set_elf_platform(cpu, "bmips3300");
 823                 break;
 824         case PRID_IMP_BMIPS43XX: {
 825                 int rev = c->processor_id & PRID_REV_MASK;
 826
 827                 if (rev >= PRID_REV_BMIPS4380_LO &&
 828                                 rev <= PRID_REV_BMIPS4380_HI) {
 829                         c->cputype = CPU_BMIPS4380;
 830                         __cpu_name[cpu] = "Broadcom BMIPS4380";
 831                         set_elf_platform(cpu, "bmips4380");
 832                 } else {
 833                         c->cputype = CPU_BMIPS4350;
 834                         __cpu_name[cpu] = "Broadcom BMIPS4350";
 835                         set_elf_platform(cpu, "bmips4350");
 836                 }
 837                 break;
 838         }
 839         case PRID_IMP_BMIPS5000:
 840                 c->cputype = CPU_BMIPS5000;
 841                 __cpu_name[cpu] = "Broadcom BMIPS5000";
 842                 set_elf_platform(cpu, "bmips5000");
 843                 c->options |= MIPS_CPU_ULRI;
 844                 break;
 845         }
 846 }
 847
 848 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 849 {
 850         decode_configs(c);
 851         switch (c->processor_id & PRID_IMP_MASK) {
 852         case PRID_IMP_CAVIUM_CN38XX:
 853         case PRID_IMP_CAVIUM_CN31XX:
 854         case PRID_IMP_CAVIUM_CN30XX:
 855                 c->cputype = CPU_CAVIUM_OCTEON;
 856                 __cpu_name[cpu] = "Cavium Octeon";
 857                 goto platform;
 858         case PRID_IMP_CAVIUM_CN58XX:
 859         case PRID_IMP_CAVIUM_CN56XX:
 860         case PRID_IMP_CAVIUM_CN50XX:
 861         case PRID_IMP_CAVIUM_CN52XX:
 862                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
 863                 __cpu_name[cpu] = "Cavium Octeon+";
 864 platform:
 865                 set_elf_platform(cpu, "octeon");
 866                 break;
 867         case PRID_IMP_CAVIUM_CN61XX:
 868         case PRID_IMP_CAVIUM_CN63XX:
 869         case PRID_IMP_CAVIUM_CN66XX:
 870         case PRID_IMP_CAVIUM_CN68XX:
 871         case PRID_IMP_CAVIUM_CNF71XX:
 872                 c->cputype = CPU_CAVIUM_OCTEON2;
 873                 __cpu_name[cpu] = "Cavium Octeon II";
 874                 set_elf_platform(cpu, "octeon2");
 875                 break;
 876         case PRID_IMP_CAVIUM_CN70XX:
 877         case PRID_IMP_CAVIUM_CN78XX:
 878                 c->cputype = CPU_CAVIUM_OCTEON3;
 879                 __cpu_name[cpu] = "Cavium Octeon III";
 880                 set_elf_platform(cpu, "octeon3");
 881                 break;
 882         default:
 883                 printk(KERN_INFO "Unknown Octeon chip!\n");
 884                 c->cputype = CPU_UNKNOWN;
 885                 break;
 886         }
 887 }
 888
 889 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 890 {
 891         decode_configs(c);
 892         /* JZRISC does not implement the CP0 counter. */
 893         c->options &= ~MIPS_CPU_COUNTER;
 894         switch (c->processor_id & PRID_IMP_MASK) {
 895         case PRID_IMP_JZRISC:
 896                 c->cputype = CPU_JZRISC;
 897                 __cpu_name[cpu] = "Ingenic JZRISC";
 898                 break;
 899         default:
 900                 panic("Unknown Ingenic Processor ID!");
 901                 break;
 902         }
 903 }
 904
 905 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
 906 {
 907         decode_configs(c);
 908
 909         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
 910                 c->cputype = CPU_ALCHEMY;
 911                 __cpu_name[cpu] = "Au1300";
 912                 /* following stuff is not for Alchemy */
 913                 return;
 914         }
 915
 916         c->options = (MIPS_CPU_TLB       |
 917                         MIPS_CPU_4KEX    |
 918                         MIPS_CPU_COUNTER |
 919                         MIPS_CPU_DIVEC   |
 920                         MIPS_CPU_WATCH   |
 921                         MIPS_CPU_EJTAG   |
 922                         MIPS_CPU_LLSC);
 923
 924         switch (c->processor_id & PRID_IMP_MASK) {
 925         case PRID_IMP_NETLOGIC_XLP2XX:
 926                 c->cputype = CPU_XLP;
 927                 __cpu_name[cpu] = "Broadcom XLPII";
 928                 break;
 929
 930         case PRID_IMP_NETLOGIC_XLP8XX:
 931         case PRID_IMP_NETLOGIC_XLP3XX:
 932                 c->cputype = CPU_XLP;
 933                 __cpu_name[cpu] = "Netlogic XLP";
 934                 break;
 935
 936         case PRID_IMP_NETLOGIC_XLR732:
 937         case PRID_IMP_NETLOGIC_XLR716:
 938         case PRID_IMP_NETLOGIC_XLR532:
 939         case PRID_IMP_NETLOGIC_XLR308:
 940         case PRID_IMP_NETLOGIC_XLR532C:
 941         case PRID_IMP_NETLOGIC_XLR516C:
 942         case PRID_IMP_NETLOGIC_XLR508C:
 943         case PRID_IMP_NETLOGIC_XLR308C:
 944                 c->cputype = CPU_XLR;
 945                 __cpu_name[cpu] = "Netlogic XLR";
 946                 break;
 947
 948         case PRID_IMP_NETLOGIC_XLS608:
 949         case PRID_IMP_NETLOGIC_XLS408:
 950         case PRID_IMP_NETLOGIC_XLS404:
 951         case PRID_IMP_NETLOGIC_XLS208:
 952         case PRID_IMP_NETLOGIC_XLS204:
 953         case PRID_IMP_NETLOGIC_XLS108:
 954         case PRID_IMP_NETLOGIC_XLS104:
 955         case PRID_IMP_NETLOGIC_XLS616B:
 956         case PRID_IMP_NETLOGIC_XLS608B:
 957         case PRID_IMP_NETLOGIC_XLS416B:
 958         case PRID_IMP_NETLOGIC_XLS412B:
 959         case PRID_IMP_NETLOGIC_XLS408B:
 960         case PRID_IMP_NETLOGIC_XLS404B:
 961                 c->cputype = CPU_XLR;
 962                 __cpu_name[cpu] = "Netlogic XLS";
 963                 break;
 964
 965         default:
 966                 pr_info("Unknown Netlogic chip id [%02x]!\n",
 967                        c->processor_id);
 968                 c->cputype = CPU_XLR;
 969                 break;
 970         }
 971
 972         if (c->cputype == CPU_XLP) {
 973                 set_isa(c, MIPS_CPU_ISA_M64R2);
 974                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
 975                 /* This will be updated again after all threads are woken up */
 976                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
 977         } else {
 978                 set_isa(c, MIPS_CPU_ISA_M64R1);
 979                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
 980         }
 981         c->kscratch_mask = 0xf;
 982 }
 983
 984 #ifdef CONFIG_64BIT
 985 /* For use by uaccess.h */
 986 u64 __ua_limit;
 987 EXPORT_SYMBOL(__ua_limit);
 988 #endif
 989
 990 const char *__cpu_name[NR_CPUS];
 991 const char *__elf_platform;
 992
 993 void cpu_probe(void)
 994 {
 995         struct cpuinfo_mips *c = &current_cpu_data;
 996         unsigned int cpu = smp_processor_id();
 997
 998         c->processor_id = PRID_IMP_UNKNOWN;
 999         c->fpu_id       = FPIR_IMP_NONE;
1000         c->cputype      = CPU_UNKNOWN;
1001
1002         c->processor_id = read_c0_prid();
1003         switch (c->processor_id & PRID_COMP_MASK) {
1004         case PRID_COMP_LEGACY:
1005                 cpu_probe_legacy(c, cpu);
1006                 break;
1007         case PRID_COMP_MIPS:
1008                 cpu_probe_mips(c, cpu);
1009                 break;
1010         case PRID_COMP_ALCHEMY:
1011                 cpu_probe_alchemy(c, cpu);
1012                 break;
1013         case PRID_COMP_SIBYTE:
1014                 cpu_probe_sibyte(c, cpu);
1015                 break;
1016         case PRID_COMP_BROADCOM:
1017                 cpu_probe_broadcom(c, cpu);
1018                 break;
1019         case PRID_COMP_SANDCRAFT:
1020                 cpu_probe_sandcraft(c, cpu);
1021                 break;
1022         case PRID_COMP_NXP:
1023                 cpu_probe_nxp(c, cpu);
1024                 break;
1025         case PRID_COMP_CAVIUM:
1026                 cpu_probe_cavium(c, cpu);
1027                 break;
1028         case PRID_COMP_INGENIC:
1029                 cpu_probe_ingenic(c, cpu);
1030                 break;
1031         case PRID_COMP_NETLOGIC:
1032                 cpu_probe_netlogic(c, cpu);
1033                 break;
1034         }
1035
1036         BUG_ON(!__cpu_name[cpu]);
1037         BUG_ON(c->cputype == CPU_UNKNOWN);
1038
1039         /*
1040          * Platform code can force the cpu type to optimize code
1041          * generation. In that case be sure the cpu type is correctly
1042          * manually setup otherwise it could trigger some nasty bugs.
1043          */
1044         BUG_ON(current_cpu_type() != c->cputype);
1045
1046         if (mips_fpu_disabled)
1047                 c->options &= ~MIPS_CPU_FPU;
1048
1049         if (mips_dsp_disabled)
1050                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1051
1052         if (c->options & MIPS_CPU_FPU) {
1053                 c->fpu_id = cpu_get_fpu_id();
1054
1055                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1056                                     MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1057                         if (c->fpu_id & MIPS_FPIR_3D)
1058                                 c->ases |= MIPS_ASE_MIPS3D;
1059                 }
1060         }
1061
1062         if (cpu_has_mips_r2) {
1063                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1064                 /* R2 has Performance Counter Interrupt indicator */
1065                 c->options |= MIPS_CPU_PCI;
1066         }
1067         else
1068                 c->srsets = 1;
1069
1070         cpu_probe_vmbits(c);
1071
1072 #ifdef CONFIG_64BIT
1073         if (cpu == 0)
1074                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1075 #endif
1076 }
1077
1078 void cpu_report(void)
1079 {
1080         struct cpuinfo_mips *c = &current_cpu_data;
1081
1082         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1083                c->processor_id, cpu_name_string());
1084         if (c->options & MIPS_CPU_FPU)
1085                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1086 }