arch/mips/include/asm/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000, 07 MIPS Technologies, Inc.
  11  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  12  */
  13 #ifndef _ASM_MIPSREGS_H
  14 #define _ASM_MIPSREGS_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/types.h>
  18 #include <asm/hazards.h>
  19 #include <asm/isa-rev.h>
  20 #include <asm/war.h>
  21
  22 /*
  23  * The following macros are especially useful for __asm__
  24  * inline assembler.
  25  */
  26 #ifndef __STR
  27 #define __STR(x) #x
  28 #endif
  29 #ifndef STR
  30 #define STR(x) __STR(x)
  31 #endif
  32
  33 /*
  34  *  Configure language
  35  */
  36 #ifdef __ASSEMBLY__
  37 #define _ULCAST_
  38 #define _U64CAST_
  39 #else
  40 #define _ULCAST_ (unsigned long)
  41 #define _U64CAST_ (u64)
  42 #endif
  43
  44 /*
  45  * Coprocessor 0 register names
  46  */
  47 #define CP0_INDEX $0
  48 #define CP0_RANDOM $1
  49 #define CP0_ENTRYLO0 $2
  50 #define CP0_ENTRYLO1 $3
  51 #define CP0_CONF $3
  52 #define CP0_GLOBALNUMBER $3, 1
  53 #define CP0_CONTEXT $4
  54 #define CP0_PAGEMASK $5
  55 #define CP0_PAGEGRAIN $5, 1
  56 #define CP0_SEGCTL0 $5, 2
  57 #define CP0_SEGCTL1 $5, 3
  58 #define CP0_SEGCTL2 $5, 4
  59 #define CP0_WIRED $6
  60 #define CP0_INFO $7
  61 #define CP0_HWRENA $7
  62 #define CP0_BADVADDR $8
  63 #define CP0_BADINSTR $8, 1
  64 #define CP0_COUNT $9
  65 #define CP0_ENTRYHI $10
  66 #define CP0_GUESTCTL1 $10, 4
  67 #define CP0_GUESTCTL2 $10, 5
  68 #define CP0_GUESTCTL3 $10, 6
  69 #define CP0_COMPARE $11
  70 #define CP0_GUESTCTL0EXT $11, 4
  71 #define CP0_STATUS $12
  72 #define CP0_GUESTCTL0 $12, 6
  73 #define CP0_GTOFFSET $12, 7
  74 #define CP0_CAUSE $13
  75 #define CP0_EPC $14
  76 #define CP0_PRID $15
  77 #define CP0_EBASE $15, 1
  78 #define CP0_CMGCRBASE $15, 3
  79 #define CP0_CONFIG $16
  80 #define CP0_CONFIG3 $16, 3
  81 #define CP0_CONFIG5 $16, 5
  82 #define CP0_CONFIG6 $16, 6
  83 #define CP0_LLADDR $17
  84 #define CP0_WATCHLO $18
  85 #define CP0_WATCHHI $19
  86 #define CP0_XCONTEXT $20
  87 #define CP0_FRAMEMASK $21
  88 #define CP0_DIAGNOSTIC $22
  89 #define CP0_DEBUG $23
  90 #define CP0_DEPC $24
  91 #define CP0_PERFORMANCE $25
  92 #define CP0_ECC $26
  93 #define CP0_CACHEERR $27
  94 #define CP0_TAGLO $28
  95 #define CP0_TAGHI $29
  96 #define CP0_ERROREPC $30
  97 #define CP0_DESAVE $31
  98
  99 /*
 100  * R4640/R4650 cp0 register names.  These registers are listed
 101  * here only for completeness; without MMU these CPUs are not useable
 102  * by Linux.  A future ELKS port might take make Linux run on them
 103  * though ...
 104  */
 105 #define CP0_IBASE $0
 106 #define CP0_IBOUND $1
 107 #define CP0_DBASE $2
 108 #define CP0_DBOUND $3
 109 #define CP0_CALG $17
 110 #define CP0_IWATCH $18
 111 #define CP0_DWATCH $19
 112
 113 /*
 114  * Coprocessor 0 Set 1 register names
 115  */
 116 #define CP0_S1_DERRADDR0  $26
 117 #define CP0_S1_DERRADDR1  $27
 118 #define CP0_S1_INTCONTROL $20
 119
 120 /*
 121  * Coprocessor 0 Set 2 register names
 122  */
 123 #define CP0_S2_SRSCTL     $12   /* MIPSR2 */
 124
 125 /*
 126  * Coprocessor 0 Set 3 register names
 127  */
 128 #define CP0_S3_SRSMAP     $12   /* MIPSR2 */
 129
 130 /*
 131  *  TX39 Series
 132  */
 133 #define CP0_TX39_CACHE  $7
 134
 135
 136 /* Generic EntryLo bit definitions */
 137 #define ENTRYLO_G               (_ULCAST_(1) << 0)
 138 #define ENTRYLO_V               (_ULCAST_(1) << 1)
 139 #define ENTRYLO_D               (_ULCAST_(1) << 2)
 140 #define ENTRYLO_C_SHIFT         3
 141 #define ENTRYLO_C               (_ULCAST_(7) << ENTRYLO_C_SHIFT)
 142
 143 /* R3000 EntryLo bit definitions */
 144 #define R3K_ENTRYLO_G           (_ULCAST_(1) << 8)
 145 #define R3K_ENTRYLO_V           (_ULCAST_(1) << 9)
 146 #define R3K_ENTRYLO_D           (_ULCAST_(1) << 10)
 147 #define R3K_ENTRYLO_N           (_ULCAST_(1) << 11)
 148
 149 /* MIPS32/64 EntryLo bit definitions */
 150 #define MIPS_ENTRYLO_PFN_SHIFT  6
 151 #define MIPS_ENTRYLO_XI         (_ULCAST_(1) << (BITS_PER_LONG - 2))
 152 #define MIPS_ENTRYLO_RI         (_ULCAST_(1) << (BITS_PER_LONG - 1))
 153
 154 /*
 155  * MIPSr6+ GlobalNumber register definitions
 156  */
 157 #define MIPS_GLOBALNUMBER_VP_SHF        0
 158 #define MIPS_GLOBALNUMBER_VP            (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_VP_SHF)
 159 #define MIPS_GLOBALNUMBER_CORE_SHF      8
 160 #define MIPS_GLOBALNUMBER_CORE          (_ULCAST_(0xff) << MIPS_GLOBALNUMBER_CORE_SHF)
 161 #define MIPS_GLOBALNUMBER_CLUSTER_SHF   16
 162 #define MIPS_GLOBALNUMBER_CLUSTER       (_ULCAST_(0xf) << MIPS_GLOBALNUMBER_CLUSTER_SHF)
 163
 164 /*
 165  * Values for PageMask register
 166  */
 167 #ifdef CONFIG_CPU_VR41XX
 168
 169 /* Why doesn't stupidity hurt ... */
 170
 171 #define PM_1K           0x00000000
 172 #define PM_4K           0x00001800
 173 #define PM_16K          0x00007800
 174 #define PM_64K          0x0001f800
 175 #define PM_256K         0x0007f800
 176
 177 #else
 178
 179 #define PM_4K           0x00000000
 180 #define PM_8K           0x00002000
 181 #define PM_16K          0x00006000
 182 #define PM_32K          0x0000e000
 183 #define PM_64K          0x0001e000
 184 #define PM_128K         0x0003e000
 185 #define PM_256K         0x0007e000
 186 #define PM_512K         0x000fe000
 187 #define PM_1M           0x001fe000
 188 #define PM_2M           0x003fe000
 189 #define PM_4M           0x007fe000
 190 #define PM_8M           0x00ffe000
 191 #define PM_16M          0x01ffe000
 192 #define PM_32M          0x03ffe000
 193 #define PM_64M          0x07ffe000
 194 #define PM_256M         0x1fffe000
 195 #define PM_1G           0x7fffe000
 196
 197 #endif
 198
 199 /*
 200  * Default page size for a given kernel configuration
 201  */
 202 #ifdef CONFIG_PAGE_SIZE_4KB
 203 #define PM_DEFAULT_MASK PM_4K
 204 #elif defined(CONFIG_PAGE_SIZE_8KB)
 205 #define PM_DEFAULT_MASK PM_8K
 206 #elif defined(CONFIG_PAGE_SIZE_16KB)
 207 #define PM_DEFAULT_MASK PM_16K
 208 #elif defined(CONFIG_PAGE_SIZE_32KB)
 209 #define PM_DEFAULT_MASK PM_32K
 210 #elif defined(CONFIG_PAGE_SIZE_64KB)
 211 #define PM_DEFAULT_MASK PM_64K
 212 #else
 213 #error Bad page size configuration!
 214 #endif
 215
 216 /*
 217  * Default huge tlb size for a given kernel configuration
 218  */
 219 #ifdef CONFIG_PAGE_SIZE_4KB
 220 #define PM_HUGE_MASK    PM_1M
 221 #elif defined(CONFIG_PAGE_SIZE_8KB)
 222 #define PM_HUGE_MASK    PM_4M
 223 #elif defined(CONFIG_PAGE_SIZE_16KB)
 224 #define PM_HUGE_MASK    PM_16M
 225 #elif defined(CONFIG_PAGE_SIZE_32KB)
 226 #define PM_HUGE_MASK    PM_64M
 227 #elif defined(CONFIG_PAGE_SIZE_64KB)
 228 #define PM_HUGE_MASK    PM_256M
 229 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
 230 #error Bad page size configuration for hugetlbfs!
 231 #endif
 232
 233 /*
 234  * Wired register bits
 235  */
 236 #define MIPSR6_WIRED_LIMIT_SHIFT 16
 237 #define MIPSR6_WIRED_LIMIT      (_ULCAST_(0xffff) << MIPSR6_WIRED_LIMIT_SHIFT)
 238 #define MIPSR6_WIRED_WIRED_SHIFT 0
 239 #define MIPSR6_WIRED_WIRED      (_ULCAST_(0xffff) << MIPSR6_WIRED_WIRED_SHIFT)
 240
 241 /*
 242  * Values used for computation of new tlb entries
 243  */
 244 #define PL_4K           12
 245 #define PL_16K          14
 246 #define PL_64K          16
 247 #define PL_256K         18
 248 #define PL_1M           20
 249 #define PL_4M           22
 250 #define PL_16M          24
 251 #define PL_64M          26
 252 #define PL_256M         28
 253
 254 /*
 255  * PageGrain bits
 256  */
 257 #define PG_RIE          (_ULCAST_(1) <<  31)
 258 #define PG_XIE          (_ULCAST_(1) <<  30)
 259 #define PG_ELPA         (_ULCAST_(1) <<  29)
 260 #define PG_ESP          (_ULCAST_(1) <<  28)
 261 #define PG_IEC          (_ULCAST_(1) <<  27)
 262
 263 /* MIPS32/64 EntryHI bit definitions */
 264 #define MIPS_ENTRYHI_EHINV      (_ULCAST_(1) << 10)
 265 #define MIPS_ENTRYHI_ASIDX      (_ULCAST_(0x3) << 8)
 266 #define MIPS_ENTRYHI_ASID       (_ULCAST_(0xff) << 0)
 267
 268 /*
 269  * R4x00 interrupt enable / cause bits
 270  */
 271 #define IE_SW0          (_ULCAST_(1) <<  8)
 272 #define IE_SW1          (_ULCAST_(1) <<  9)
 273 #define IE_IRQ0         (_ULCAST_(1) << 10)
 274 #define IE_IRQ1         (_ULCAST_(1) << 11)
 275 #define IE_IRQ2         (_ULCAST_(1) << 12)
 276 #define IE_IRQ3         (_ULCAST_(1) << 13)
 277 #define IE_IRQ4         (_ULCAST_(1) << 14)
 278 #define IE_IRQ5         (_ULCAST_(1) << 15)
 279
 280 /*
 281  * R4x00 interrupt cause bits
 282  */
 283 #define C_SW0           (_ULCAST_(1) <<  8)
 284 #define C_SW1           (_ULCAST_(1) <<  9)
 285 #define C_IRQ0          (_ULCAST_(1) << 10)
 286 #define C_IRQ1          (_ULCAST_(1) << 11)
 287 #define C_IRQ2          (_ULCAST_(1) << 12)
 288 #define C_IRQ3          (_ULCAST_(1) << 13)
 289 #define C_IRQ4          (_ULCAST_(1) << 14)
 290 #define C_IRQ5          (_ULCAST_(1) << 15)
 291
 292 /*
 293  * Bitfields in the R4xx0 cp0 status register
 294  */
 295 #define ST0_IE                  0x00000001
 296 #define ST0_EXL                 0x00000002
 297 #define ST0_ERL                 0x00000004
 298 #define ST0_KSU                 0x00000018
 299 #  define KSU_USER              0x00000010
 300 #  define KSU_SUPERVISOR        0x00000008
 301 #  define KSU_KERNEL            0x00000000
 302 #define ST0_UX                  0x00000020
 303 #define ST0_SX                  0x00000040
 304 #define ST0_KX                  0x00000080
 305 #define ST0_DE                  0x00010000
 306 #define ST0_CE                  0x00020000
 307
 308 /*
 309  * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
 310  * cacheops in userspace.  This bit exists only on RM7000 and RM9000
 311  * processors.
 312  */
 313 #define ST0_CO                  0x08000000
 314
 315 /*
 316  * Bitfields in the R[23]000 cp0 status register.
 317  */
 318 #define ST0_IEC                 0x00000001
 319 #define ST0_KUC                 0x00000002
 320 #define ST0_IEP                 0x00000004
 321 #define ST0_KUP                 0x00000008
 322 #define ST0_IEO                 0x00000010
 323 #define ST0_KUO                 0x00000020
 324 /* bits 6 & 7 are reserved on R[23]000 */
 325 #define ST0_ISC                 0x00010000
 326 #define ST0_SWC                 0x00020000
 327 #define ST0_CM                  0x00080000
 328
 329 /*
 330  * Bits specific to the R4640/R4650
 331  */
 332 #define ST0_UM                  (_ULCAST_(1) <<  4)
 333 #define ST0_IL                  (_ULCAST_(1) << 23)
 334 #define ST0_DL                  (_ULCAST_(1) << 24)
 335
 336 /*
 337  * Enable the MIPS MDMX and DSP ASEs
 338  */
 339 #define ST0_MX                  0x01000000
 340
 341 /*
 342  * Status register bits available in all MIPS CPUs.
 343  */
 344 #define ST0_IM                  0x0000ff00
 345 #define  STATUSB_IP0            8
 346 #define  STATUSF_IP0            (_ULCAST_(1) <<  8)
 347 #define  STATUSB_IP1            9
 348 #define  STATUSF_IP1            (_ULCAST_(1) <<  9)
 349 #define  STATUSB_IP2            10
 350 #define  STATUSF_IP2            (_ULCAST_(1) << 10)
 351 #define  STATUSB_IP3            11
 352 #define  STATUSF_IP3            (_ULCAST_(1) << 11)
 353 #define  STATUSB_IP4            12
 354 #define  STATUSF_IP4            (_ULCAST_(1) << 12)
 355 #define  STATUSB_IP5            13
 356 #define  STATUSF_IP5            (_ULCAST_(1) << 13)
 357 #define  STATUSB_IP6            14
 358 #define  STATUSF_IP6            (_ULCAST_(1) << 14)
 359 #define  STATUSB_IP7            15
 360 #define  STATUSF_IP7            (_ULCAST_(1) << 15)
 361 #define  STATUSB_IP8            0
 362 #define  STATUSF_IP8            (_ULCAST_(1) <<  0)
 363 #define  STATUSB_IP9            1
 364 #define  STATUSF_IP9            (_ULCAST_(1) <<  1)
 365 #define  STATUSB_IP10           2
 366 #define  STATUSF_IP10           (_ULCAST_(1) <<  2)
 367 #define  STATUSB_IP11           3
 368 #define  STATUSF_IP11           (_ULCAST_(1) <<  3)
 369 #define  STATUSB_IP12           4
 370 #define  STATUSF_IP12           (_ULCAST_(1) <<  4)
 371 #define  STATUSB_IP13           5
 372 #define  STATUSF_IP13           (_ULCAST_(1) <<  5)
 373 #define  STATUSB_IP14           6
 374 #define  STATUSF_IP14           (_ULCAST_(1) <<  6)
 375 #define  STATUSB_IP15           7
 376 #define  STATUSF_IP15           (_ULCAST_(1) <<  7)
 377 #define ST0_CH                  0x00040000
 378 #define ST0_NMI                 0x00080000
 379 #define ST0_SR                  0x00100000
 380 #define ST0_TS                  0x00200000
 381 #define ST0_BEV                 0x00400000
 382 #define ST0_RE                  0x02000000
 383 #define ST0_FR                  0x04000000
 384 #define ST0_CU                  0xf0000000
 385 #define ST0_CU0                 0x10000000
 386 #define ST0_CU1                 0x20000000
 387 #define ST0_CU2                 0x40000000
 388 #define ST0_CU3                 0x80000000
 389 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 390
 391 /*
 392  * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
 393  */
 394 #define INTCTLB_IPFDC           23
 395 #define INTCTLF_IPFDC           (_ULCAST_(7) << INTCTLB_IPFDC)
 396 #define INTCTLB_IPPCI           26
 397 #define INTCTLF_IPPCI           (_ULCAST_(7) << INTCTLB_IPPCI)
 398 #define INTCTLB_IPTI            29
 399 #define INTCTLF_IPTI            (_ULCAST_(7) << INTCTLB_IPTI)
 400
 401 /*
 402  * Bitfields and bit numbers in the coprocessor 0 cause register.
 403  *
 404  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 405  */
 406 #define CAUSEB_EXCCODE          2
 407 #define CAUSEF_EXCCODE          (_ULCAST_(31)  <<  2)
 408 #define CAUSEB_IP               8
 409 #define CAUSEF_IP               (_ULCAST_(255) <<  8)
 410 #define  CAUSEB_IP0             8
 411 #define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
 412 #define  CAUSEB_IP1             9
 413 #define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
 414 #define  CAUSEB_IP2             10
 415 #define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
 416 #define  CAUSEB_IP3             11
 417 #define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
 418 #define  CAUSEB_IP4             12
 419 #define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
 420 #define  CAUSEB_IP5             13
 421 #define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
 422 #define  CAUSEB_IP6             14
 423 #define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
 424 #define  CAUSEB_IP7             15
 425 #define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
 426 #define CAUSEB_FDCI             21
 427 #define CAUSEF_FDCI             (_ULCAST_(1)   << 21)
 428 #define CAUSEB_WP               22
 429 #define CAUSEF_WP               (_ULCAST_(1)   << 22)
 430 #define CAUSEB_IV               23
 431 #define CAUSEF_IV               (_ULCAST_(1)   << 23)
 432 #define CAUSEB_PCI              26
 433 #define CAUSEF_PCI              (_ULCAST_(1)   << 26)
 434 #define CAUSEB_DC               27
 435 #define CAUSEF_DC               (_ULCAST_(1)   << 27)
 436 #define CAUSEB_CE               28
 437 #define CAUSEF_CE               (_ULCAST_(3)   << 28)
 438 #define CAUSEB_TI               30
 439 #define CAUSEF_TI               (_ULCAST_(1)   << 30)
 440 #define CAUSEB_BD               31
 441 #define CAUSEF_BD               (_ULCAST_(1)   << 31)
 442
 443 /*
 444  * Cause.ExcCode trap codes.
 445  */
 446 #define EXCCODE_INT             0       /* Interrupt pending */
 447 #define EXCCODE_MOD             1       /* TLB modified fault */
 448 #define EXCCODE_TLBL            2       /* TLB miss on load or ifetch */
 449 #define EXCCODE_TLBS            3       /* TLB miss on a store */
 450 #define EXCCODE_ADEL            4       /* Address error on a load or ifetch */
 451 #define EXCCODE_ADES            5       /* Address error on a store */
 452 #define EXCCODE_IBE             6       /* Bus error on an ifetch */
 453 #define EXCCODE_DBE             7       /* Bus error on a load or store */
 454 #define EXCCODE_SYS             8       /* System call */
 455 #define EXCCODE_BP              9       /* Breakpoint */
 456 #define EXCCODE_RI              10      /* Reserved instruction exception */
 457 #define EXCCODE_CPU             11      /* Coprocessor unusable */
 458 #define EXCCODE_OV              12      /* Arithmetic overflow */
 459 #define EXCCODE_TR              13      /* Trap instruction */
 460 #define EXCCODE_MSAFPE          14      /* MSA floating point exception */
 461 #define EXCCODE_FPE             15      /* Floating point exception */
 462 #define EXCCODE_TLBRI           19      /* TLB Read-Inhibit exception */
 463 #define EXCCODE_TLBXI           20      /* TLB Execution-Inhibit exception */
 464 #define EXCCODE_MSADIS          21      /* MSA disabled exception */
 465 #define EXCCODE_MDMX            22      /* MDMX unusable exception */
 466 #define EXCCODE_WATCH           23      /* Watch address reference */
 467 #define EXCCODE_MCHECK          24      /* Machine check */
 468 #define EXCCODE_THREAD          25      /* Thread exceptions (MT) */
 469 #define EXCCODE_DSPDIS          26      /* DSP disabled exception */
 470 #define EXCCODE_GE              27      /* Virtualized guest exception (VZ) */
 471
 472 /* Implementation specific trap codes used by MIPS cores */
 473 #define MIPS_EXCCODE_TLBPAR     16      /* TLB parity error exception */
 474
 475 /*
 476  * Bits in the coprocessor 0 config register.
 477  */
 478 /* Generic bits.  */
 479 #define CONF_CM_CACHABLE_NO_WA          0
 480 #define CONF_CM_CACHABLE_WA             1
 481 #define CONF_CM_UNCACHED                2
 482 #define CONF_CM_CACHABLE_NONCOHERENT    3
 483 #define CONF_CM_CACHABLE_CE             4
 484 #define CONF_CM_CACHABLE_COW            5
 485 #define CONF_CM_CACHABLE_CUW            6
 486 #define CONF_CM_CACHABLE_ACCELERATED    7
 487 #define CONF_CM_CMASK                   7
 488 #define CONF_BE                 (_ULCAST_(1) << 15)
 489
 490 /* Bits common to various processors.  */
 491 #define CONF_CU                 (_ULCAST_(1) <<  3)
 492 #define CONF_DB                 (_ULCAST_(1) <<  4)
 493 #define CONF_IB                 (_ULCAST_(1) <<  5)
 494 #define CONF_DC                 (_ULCAST_(7) <<  6)
 495 #define CONF_IC                 (_ULCAST_(7) <<  9)
 496 #define CONF_EB                 (_ULCAST_(1) << 13)
 497 #define CONF_EM                 (_ULCAST_(1) << 14)
 498 #define CONF_SM                 (_ULCAST_(1) << 16)
 499 #define CONF_SC                 (_ULCAST_(1) << 17)
 500 #define CONF_EW                 (_ULCAST_(3) << 18)
 501 #define CONF_EP                 (_ULCAST_(15)<< 24)
 502 #define CONF_EC                 (_ULCAST_(7) << 28)
 503 #define CONF_CM                 (_ULCAST_(1) << 31)
 504
 505 /* Bits specific to the R4xx0.  */
 506 #define R4K_CONF_SW             (_ULCAST_(1) << 20)
 507 #define R4K_CONF_SS             (_ULCAST_(1) << 21)
 508 #define R4K_CONF_SB             (_ULCAST_(3) << 22)
 509
 510 /* Bits specific to the R5000.  */
 511 #define R5K_CONF_SE             (_ULCAST_(1) << 12)
 512 #define R5K_CONF_SS             (_ULCAST_(3) << 20)
 513
 514 /* Bits specific to the RM7000.  */
 515 #define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
 516 #define RM7K_CONF_TE            (_ULCAST_(1) << 12)
 517 #define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
 518 #define RM7K_CONF_TC            (_ULCAST_(1) << 17)
 519 #define RM7K_CONF_SI            (_ULCAST_(3) << 20)
 520 #define RM7K_CONF_SC            (_ULCAST_(1) << 31)
 521
 522 /* Bits specific to the R10000.  */
 523 #define R10K_CONF_DN            (_ULCAST_(3) <<  3)
 524 #define R10K_CONF_CT            (_ULCAST_(1) <<  5)
 525 #define R10K_CONF_PE            (_ULCAST_(1) <<  6)
 526 #define R10K_CONF_PM            (_ULCAST_(3) <<  7)
 527 #define R10K_CONF_EC            (_ULCAST_(15)<<  9)
 528 #define R10K_CONF_SB            (_ULCAST_(1) << 13)
 529 #define R10K_CONF_SK            (_ULCAST_(1) << 14)
 530 #define R10K_CONF_SS            (_ULCAST_(7) << 16)
 531 #define R10K_CONF_SC            (_ULCAST_(7) << 19)
 532 #define R10K_CONF_DC            (_ULCAST_(7) << 26)
 533 #define R10K_CONF_IC            (_ULCAST_(7) << 29)
 534
 535 /* Bits specific to the VR41xx.  */
 536 #define VR41_CONF_CS            (_ULCAST_(1) << 12)
 537 #define VR41_CONF_P4K           (_ULCAST_(1) << 13)
 538 #define VR41_CONF_BP            (_ULCAST_(1) << 16)
 539 #define VR41_CONF_M16           (_ULCAST_(1) << 20)
 540 #define VR41_CONF_AD            (_ULCAST_(1) << 23)
 541
 542 /* Bits specific to the R30xx.  */
 543 #define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
 544 #define R30XX_CONF_REV          (_ULCAST_(1) << 22)
 545 #define R30XX_CONF_AC           (_ULCAST_(1) << 23)
 546 #define R30XX_CONF_RF           (_ULCAST_(1) << 24)
 547 #define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
 548 #define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
 549 #define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
 550 #define R30XX_CONF_SB           (_ULCAST_(1) << 30)
 551 #define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
 552
 553 /* Bits specific to the TX49.  */
 554 #define TX49_CONF_DC            (_ULCAST_(1) << 16)
 555 #define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
 556 #define TX49_CONF_HALT          (_ULCAST_(1) << 18)
 557 #define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
 558
 559 /* Bits specific to the MIPS32/64 PRA.  */
 560 #define MIPS_CONF_VI            (_ULCAST_(1) <<  3)
 561 #define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
 562 #define MIPS_CONF_MT_TLB        (_ULCAST_(1) <<  7)
 563 #define MIPS_CONF_MT_FTLB       (_ULCAST_(4) <<  7)
 564 #define MIPS_CONF_AR            (_ULCAST_(7) << 10)
 565 #define MIPS_CONF_AT            (_ULCAST_(3) << 13)
 566 #define MIPS_CONF_M             (_ULCAST_(1) << 31)
 567
 568 /*
 569  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
 570  */
 571 #define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
 572 #define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
 573 #define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
 574 #define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
 575 #define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
 576 #define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
 577 #define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
 578 #define MIPS_CONF1_DA_SHF       7
 579 #define MIPS_CONF1_DA_SZ        3
 580 #define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
 581 #define MIPS_CONF1_DL_SHF       10
 582 #define MIPS_CONF1_DL_SZ        3
 583 #define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
 584 #define MIPS_CONF1_DS_SHF       13
 585 #define MIPS_CONF1_DS_SZ        3
 586 #define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
 587 #define MIPS_CONF1_IA_SHF       16
 588 #define MIPS_CONF1_IA_SZ        3
 589 #define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
 590 #define MIPS_CONF1_IL_SHF       19
 591 #define MIPS_CONF1_IL_SZ        3
 592 #define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
 593 #define MIPS_CONF1_IS_SHF       22
 594 #define MIPS_CONF1_IS_SZ        3
 595 #define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
 596 #define MIPS_CONF1_TLBS_SHIFT   (25)
 597 #define MIPS_CONF1_TLBS_SIZE    (6)
 598 #define MIPS_CONF1_TLBS         (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
 599
 600 #define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
 601 #define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
 602 #define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
 603 #define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
 604 #define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
 605 #define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
 606 #define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
 607 #define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
 608
 609 #define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
 610 #define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
 611 #define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
 612 #define MIPS_CONF3_CDMM         (_ULCAST_(1) <<  3)
 613 #define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
 614 #define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
 615 #define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
 616 #define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
 617 #define MIPS_CONF3_ITL          (_ULCAST_(1) <<  8)
 618 #define MIPS_CONF3_CTXTC        (_ULCAST_(1) <<  9)
 619 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 620 #define MIPS_CONF3_DSP2P        (_ULCAST_(1) << 11)
 621 #define MIPS_CONF3_RXI          (_ULCAST_(1) << 12)
 622 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 623 #define MIPS_CONF3_ISA          (_ULCAST_(3) << 14)
 624 #define MIPS_CONF3_ISA_OE       (_ULCAST_(1) << 16)
 625 #define MIPS_CONF3_MCU          (_ULCAST_(1) << 17)
 626 #define MIPS_CONF3_MMAR         (_ULCAST_(7) << 18)
 627 #define MIPS_CONF3_IPLW         (_ULCAST_(3) << 21)
 628 #define MIPS_CONF3_VZ           (_ULCAST_(1) << 23)
 629 #define MIPS_CONF3_PW           (_ULCAST_(1) << 24)
 630 #define MIPS_CONF3_SC           (_ULCAST_(1) << 25)
 631 #define MIPS_CONF3_BI           (_ULCAST_(1) << 26)
 632 #define MIPS_CONF3_BP           (_ULCAST_(1) << 27)
 633 #define MIPS_CONF3_MSA          (_ULCAST_(1) << 28)
 634 #define MIPS_CONF3_CMGCR        (_ULCAST_(1) << 29)
 635 #define MIPS_CONF3_BPG          (_ULCAST_(1) << 30)
 636
 637 #define MIPS_CONF4_MMUSIZEEXT_SHIFT     (0)
 638 #define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
 639 #define MIPS_CONF4_FTLBSETS_SHIFT       (0)
 640 #define MIPS_CONF4_FTLBSETS     (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
 641 #define MIPS_CONF4_FTLBWAYS_SHIFT       (4)
 642 #define MIPS_CONF4_FTLBWAYS     (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
 643 #define MIPS_CONF4_FTLBPAGESIZE_SHIFT   (8)
 644 /* bits 10:8 in FTLB-only configurations */
 645 #define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 646 /* bits 12:8 in VTLB-FTLB only configurations */
 647 #define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
 648 #define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
 649 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
 650 #define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT        (_ULCAST_(2) << 14)
 651 #define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT        (_ULCAST_(3) << 14)
 652 #define MIPS_CONF4_KSCREXIST_SHIFT      (16)
 653 #define MIPS_CONF4_KSCREXIST    (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
 654 #define MIPS_CONF4_VTLBSIZEEXT_SHIFT    (24)
 655 #define MIPS_CONF4_VTLBSIZEEXT  (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
 656 #define MIPS_CONF4_AE           (_ULCAST_(1) << 28)
 657 #define MIPS_CONF4_IE           (_ULCAST_(3) << 29)
 658 #define MIPS_CONF4_TLBINV       (_ULCAST_(2) << 29)
 659
 660 #define MIPS_CONF5_NF           (_ULCAST_(1) << 0)
 661 #define MIPS_CONF5_UFR          (_ULCAST_(1) << 2)
 662 #define MIPS_CONF5_MRP          (_ULCAST_(1) << 3)
 663 #define MIPS_CONF5_LLB          (_ULCAST_(1) << 4)
 664 #define MIPS_CONF5_MVH          (_ULCAST_(1) << 5)
 665 #define MIPS_CONF5_VP           (_ULCAST_(1) << 7)
 666 #define MIPS_CONF5_SBRI         (_ULCAST_(1) << 6)
 667 #define MIPS_CONF5_FRE          (_ULCAST_(1) << 8)
 668 #define MIPS_CONF5_UFE          (_ULCAST_(1) << 9)
 669 #define MIPS_CONF5_CA2          (_ULCAST_(1) << 14)
 670 #define MIPS_CONF5_MI           (_ULCAST_(1) << 17)
 671 #define MIPS_CONF5_CRCP         (_ULCAST_(1) << 18)
 672 #define MIPS_CONF5_MSAEN        (_ULCAST_(1) << 27)
 673 #define MIPS_CONF5_EVA          (_ULCAST_(1) << 28)
 674 #define MIPS_CONF5_CV           (_ULCAST_(1) << 29)
 675 #define MIPS_CONF5_K            (_ULCAST_(1) << 30)
 676
 677 #define MIPS_CONF6_SYND         (_ULCAST_(1) << 13)
 678 /* proAptiv FTLB on/off bit */
 679 #define MIPS_CONF6_FTLBEN       (_ULCAST_(1) << 15)
 680 /* Loongson-3 FTLB on/off bit */
 681 #define MIPS_CONF6_FTLBDIS      (_ULCAST_(1) << 22)
 682 /* FTLB probability bits */
 683 #define MIPS_CONF6_FTLBP_SHIFT  (16)
 684
 685 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 686
 687 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
 688
 689 #define MIPS_CONF7_IAR          (_ULCAST_(1) << 10)
 690 #define MIPS_CONF7_AR           (_ULCAST_(1) << 16)
 691
 692 /* Ingenic HPTLB off bits */
 693 #define XBURST_PAGECTRL_HPTLB_DIS 0xa9000000
 694
 695 /* Ingenic Config7 bits */
 696 #define MIPS_CONF7_BTB_LOOP_EN  (_ULCAST_(1) << 4)
 697
 698 /* Config7 Bits specific to MIPS Technologies. */
 699
 700 /* Performance counters implemented Per TC */
 701 #define MTI_CONF7_PTC           (_ULCAST_(1) << 19)
 702
 703 /* WatchLo* register definitions */
 704 #define MIPS_WATCHLO_IRW        (_ULCAST_(0x7) << 0)
 705
 706 /* WatchHi* register definitions */
 707 #define MIPS_WATCHHI_M          (_ULCAST_(1) << 31)
 708 #define MIPS_WATCHHI_G          (_ULCAST_(1) << 30)
 709 #define MIPS_WATCHHI_WM         (_ULCAST_(0x3) << 28)
 710 #define MIPS_WATCHHI_WM_R_RVA   (_ULCAST_(0) << 28)
 711 #define MIPS_WATCHHI_WM_R_GPA   (_ULCAST_(1) << 28)
 712 #define MIPS_WATCHHI_WM_G_GVA   (_ULCAST_(2) << 28)
 713 #define MIPS_WATCHHI_EAS        (_ULCAST_(0x3) << 24)
 714 #define MIPS_WATCHHI_ASID       (_ULCAST_(0xff) << 16)
 715 #define MIPS_WATCHHI_MASK       (_ULCAST_(0x1ff) << 3)
 716 #define MIPS_WATCHHI_I          (_ULCAST_(1) << 2)
 717 #define MIPS_WATCHHI_R          (_ULCAST_(1) << 1)
 718 #define MIPS_WATCHHI_W          (_ULCAST_(1) << 0)
 719 #define MIPS_WATCHHI_IRW        (_ULCAST_(0x7) << 0)
 720
 721 /* PerfCnt control register definitions */
 722 #define MIPS_PERFCTRL_EXL       (_ULCAST_(1) << 0)
 723 #define MIPS_PERFCTRL_K         (_ULCAST_(1) << 1)
 724 #define MIPS_PERFCTRL_S         (_ULCAST_(1) << 2)
 725 #define MIPS_PERFCTRL_U         (_ULCAST_(1) << 3)
 726 #define MIPS_PERFCTRL_IE        (_ULCAST_(1) << 4)
 727 #define MIPS_PERFCTRL_EVENT_S   5
 728 #define MIPS_PERFCTRL_EVENT     (_ULCAST_(0x3ff) << MIPS_PERFCTRL_EVENT_S)
 729 #define MIPS_PERFCTRL_PCTD      (_ULCAST_(1) << 15)
 730 #define MIPS_PERFCTRL_EC        (_ULCAST_(0x3) << 23)
 731 #define MIPS_PERFCTRL_EC_R      (_ULCAST_(0) << 23)
 732 #define MIPS_PERFCTRL_EC_RI     (_ULCAST_(1) << 23)
 733 #define MIPS_PERFCTRL_EC_G      (_ULCAST_(2) << 23)
 734 #define MIPS_PERFCTRL_EC_GRI    (_ULCAST_(3) << 23)
 735 #define MIPS_PERFCTRL_W         (_ULCAST_(1) << 30)
 736 #define MIPS_PERFCTRL_M         (_ULCAST_(1) << 31)
 737
 738 /* PerfCnt control register MT extensions used by MIPS cores */
 739 #define MIPS_PERFCTRL_VPEID_S   16
 740 #define MIPS_PERFCTRL_VPEID     (_ULCAST_(0xf) << MIPS_PERFCTRL_VPEID_S)
 741 #define MIPS_PERFCTRL_TCID_S    22
 742 #define MIPS_PERFCTRL_TCID      (_ULCAST_(0xff) << MIPS_PERFCTRL_TCID_S)
 743 #define MIPS_PERFCTRL_MT_EN     (_ULCAST_(0x3) << 20)
 744 #define MIPS_PERFCTRL_MT_EN_ALL (_ULCAST_(0) << 20)
 745 #define MIPS_PERFCTRL_MT_EN_VPE (_ULCAST_(1) << 20)
 746 #define MIPS_PERFCTRL_MT_EN_TC  (_ULCAST_(2) << 20)
 747
 748 /* PerfCnt control register MT extensions used by BMIPS5000 */
 749 #define BRCM_PERFCTRL_TC        (_ULCAST_(1) << 30)
 750
 751 /* PerfCnt control register MT extensions used by Netlogic XLR */
 752 #define XLR_PERFCTRL_ALLTHREADS (_ULCAST_(1) << 13)
 753
 754 /* MAAR bit definitions */
 755 #define MIPS_MAAR_VH            (_U64CAST_(1) << 63)
 756 #define MIPS_MAAR_ADDR          ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
 757 #define MIPS_MAAR_ADDR_SHIFT    12
 758 #define MIPS_MAAR_S             (_ULCAST_(1) << 1)
 759 #define MIPS_MAAR_VL            (_ULCAST_(1) << 0)
 760
 761 /* MAARI bit definitions */
 762 #define MIPS_MAARI_INDEX        (_ULCAST_(0x3f) << 0)
 763
 764 /* EBase bit definitions */
 765 #define MIPS_EBASE_CPUNUM_SHIFT 0
 766 #define MIPS_EBASE_CPUNUM       (_ULCAST_(0x3ff) << 0)
 767 #define MIPS_EBASE_WG_SHIFT     11
 768 #define MIPS_EBASE_WG           (_ULCAST_(1) << 11)
 769 #define MIPS_EBASE_BASE_SHIFT   12
 770 #define MIPS_EBASE_BASE         (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
 771
 772 /* CMGCRBase bit definitions */
 773 #define MIPS_CMGCRB_BASE        11
 774 #define MIPS_CMGCRF_BASE        (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 775
 776 /* LLAddr bit definitions */
 777 #define MIPS_LLADDR_LLB_SHIFT   0
 778 #define MIPS_LLADDR_LLB         (_ULCAST_(1) << MIPS_LLADDR_LLB_SHIFT)
 779
 780 /*
 781  * Bits in the MIPS32 Memory Segmentation registers.
 782  */
 783 #define MIPS_SEGCFG_PA_SHIFT    9
 784 #define MIPS_SEGCFG_PA          (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
 785 #define MIPS_SEGCFG_AM_SHIFT    4
 786 #define MIPS_SEGCFG_AM          (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
 787 #define MIPS_SEGCFG_EU_SHIFT    3
 788 #define MIPS_SEGCFG_EU          (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
 789 #define MIPS_SEGCFG_C_SHIFT     0
 790 #define MIPS_SEGCFG_C           (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
 791
 792 #define MIPS_SEGCFG_UUSK        _ULCAST_(7)
 793 #define MIPS_SEGCFG_USK         _ULCAST_(5)
 794 #define MIPS_SEGCFG_MUSUK       _ULCAST_(4)
 795 #define MIPS_SEGCFG_MUSK        _ULCAST_(3)
 796 #define MIPS_SEGCFG_MSK         _ULCAST_(2)
 797 #define MIPS_SEGCFG_MK          _ULCAST_(1)
 798 #define MIPS_SEGCFG_UK          _ULCAST_(0)
 799
 800 #define MIPS_PWFIELD_GDI_SHIFT  24
 801 #define MIPS_PWFIELD_GDI_MASK   0x3f000000
 802 #define MIPS_PWFIELD_UDI_SHIFT  18
 803 #define MIPS_PWFIELD_UDI_MASK   0x00fc0000
 804 #define MIPS_PWFIELD_MDI_SHIFT  12
 805 #define MIPS_PWFIELD_MDI_MASK   0x0003f000
 806 #define MIPS_PWFIELD_PTI_SHIFT  6
 807 #define MIPS_PWFIELD_PTI_MASK   0x00000fc0
 808 #define MIPS_PWFIELD_PTEI_SHIFT 0
 809 #define MIPS_PWFIELD_PTEI_MASK  0x0000003f
 810
 811 #define MIPS_PWSIZE_PS_SHIFT    30
 812 #define MIPS_PWSIZE_PS_MASK     0x40000000
 813 #define MIPS_PWSIZE_GDW_SHIFT   24
 814 #define MIPS_PWSIZE_GDW_MASK    0x3f000000
 815 #define MIPS_PWSIZE_UDW_SHIFT   18
 816 #define MIPS_PWSIZE_UDW_MASK    0x00fc0000
 817 #define MIPS_PWSIZE_MDW_SHIFT   12
 818 #define MIPS_PWSIZE_MDW_MASK    0x0003f000
 819 #define MIPS_PWSIZE_PTW_SHIFT   6
 820 #define MIPS_PWSIZE_PTW_MASK    0x00000fc0
 821 #define MIPS_PWSIZE_PTEW_SHIFT  0
 822 #define MIPS_PWSIZE_PTEW_MASK   0x0000003f
 823
 824 #define MIPS_PWCTL_PWEN_SHIFT   31
 825 #define MIPS_PWCTL_PWEN_MASK    0x80000000
 826 #define MIPS_PWCTL_XK_SHIFT     28
 827 #define MIPS_PWCTL_XK_MASK      0x10000000
 828 #define MIPS_PWCTL_XS_SHIFT     27
 829 #define MIPS_PWCTL_XS_MASK      0x08000000
 830 #define MIPS_PWCTL_XU_SHIFT     26
 831 #define MIPS_PWCTL_XU_MASK      0x04000000
 832 #define MIPS_PWCTL_DPH_SHIFT    7
 833 #define MIPS_PWCTL_DPH_MASK     0x00000080
 834 #define MIPS_PWCTL_HUGEPG_SHIFT 6
 835 #define MIPS_PWCTL_HUGEPG_MASK  0x00000060
 836 #define MIPS_PWCTL_PSN_SHIFT    0
 837 #define MIPS_PWCTL_PSN_MASK     0x0000003f
 838
 839 /* GuestCtl0 fields */
 840 #define MIPS_GCTL0_GM_SHIFT     31
 841 #define MIPS_GCTL0_GM           (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
 842 #define MIPS_GCTL0_RI_SHIFT     30
 843 #define MIPS_GCTL0_RI           (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
 844 #define MIPS_GCTL0_MC_SHIFT     29
 845 #define MIPS_GCTL0_MC           (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
 846 #define MIPS_GCTL0_CP0_SHIFT    28
 847 #define MIPS_GCTL0_CP0          (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
 848 #define MIPS_GCTL0_AT_SHIFT     26
 849 #define MIPS_GCTL0_AT           (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
 850 #define MIPS_GCTL0_GT_SHIFT     25
 851 #define MIPS_GCTL0_GT           (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
 852 #define MIPS_GCTL0_CG_SHIFT     24
 853 #define MIPS_GCTL0_CG           (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
 854 #define MIPS_GCTL0_CF_SHIFT     23
 855 #define MIPS_GCTL0_CF           (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
 856 #define MIPS_GCTL0_G1_SHIFT     22
 857 #define MIPS_GCTL0_G1           (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
 858 #define MIPS_GCTL0_G0E_SHIFT    19
 859 #define MIPS_GCTL0_G0E          (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
 860 #define MIPS_GCTL0_PT_SHIFT     18
 861 #define MIPS_GCTL0_PT           (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
 862 #define MIPS_GCTL0_RAD_SHIFT    9
 863 #define MIPS_GCTL0_RAD          (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
 864 #define MIPS_GCTL0_DRG_SHIFT    8
 865 #define MIPS_GCTL0_DRG          (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
 866 #define MIPS_GCTL0_G2_SHIFT     7
 867 #define MIPS_GCTL0_G2           (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
 868 #define MIPS_GCTL0_GEXC_SHIFT   2
 869 #define MIPS_GCTL0_GEXC         (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
 870 #define MIPS_GCTL0_SFC2_SHIFT   1
 871 #define MIPS_GCTL0_SFC2         (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
 872 #define MIPS_GCTL0_SFC1_SHIFT   0
 873 #define MIPS_GCTL0_SFC1         (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
 874
 875 /* GuestCtl0.AT Guest address translation control */
 876 #define MIPS_GCTL0_AT_ROOT      1  /* Guest MMU under Root control */
 877 #define MIPS_GCTL0_AT_GUEST     3  /* Guest MMU under Guest control */
 878
 879 /* GuestCtl0.GExcCode Hypervisor exception cause codes */
 880 #define MIPS_GCTL0_GEXC_GPSI    0  /* Guest Privileged Sensitive Instruction */
 881 #define MIPS_GCTL0_GEXC_GSFC    1  /* Guest Software Field Change */
 882 #define MIPS_GCTL0_GEXC_HC      2  /* Hypercall */
 883 #define MIPS_GCTL0_GEXC_GRR     3  /* Guest Reserved Instruction Redirect */
 884 #define MIPS_GCTL0_GEXC_GVA     8  /* Guest Virtual Address available */
 885 #define MIPS_GCTL0_GEXC_GHFC    9  /* Guest Hardware Field Change */
 886 #define MIPS_GCTL0_GEXC_GPA     10 /* Guest Physical Address available */
 887
 888 /* GuestCtl0Ext fields */
 889 #define MIPS_GCTL0EXT_RPW_SHIFT 8
 890 #define MIPS_GCTL0EXT_RPW       (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
 891 #define MIPS_GCTL0EXT_NCC_SHIFT 6
 892 #define MIPS_GCTL0EXT_NCC       (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
 893 #define MIPS_GCTL0EXT_CGI_SHIFT 4
 894 #define MIPS_GCTL0EXT_CGI       (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
 895 #define MIPS_GCTL0EXT_FCD_SHIFT 3
 896 #define MIPS_GCTL0EXT_FCD       (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
 897 #define MIPS_GCTL0EXT_OG_SHIFT  2
 898 #define MIPS_GCTL0EXT_OG        (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
 899 #define MIPS_GCTL0EXT_BG_SHIFT  1
 900 #define MIPS_GCTL0EXT_BG        (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
 901 #define MIPS_GCTL0EXT_MG_SHIFT  0
 902 #define MIPS_GCTL0EXT_MG        (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
 903
 904 /* GuestCtl0Ext.RPW Root page walk configuration */
 905 #define MIPS_GCTL0EXT_RPW_BOTH  0  /* Root PW for GPA->RPA and RVA->RPA */
 906 #define MIPS_GCTL0EXT_RPW_GPA   2  /* Root PW for GPA->RPA */
 907 #define MIPS_GCTL0EXT_RPW_RVA   3  /* Root PW for RVA->RPA */
 908
 909 /* GuestCtl0Ext.NCC Nested cache coherency attributes */
 910 #define MIPS_GCTL0EXT_NCC_IND   0  /* Guest CCA independent of Root CCA */
 911 #define MIPS_GCTL0EXT_NCC_MOD   1  /* Guest CCA modified by Root CCA */
 912
 913 /* GuestCtl1 fields */
 914 #define MIPS_GCTL1_ID_SHIFT     0
 915 #define MIPS_GCTL1_ID_WIDTH     8
 916 #define MIPS_GCTL1_ID           (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
 917 #define MIPS_GCTL1_RID_SHIFT    16
 918 #define MIPS_GCTL1_RID_WIDTH    8
 919 #define MIPS_GCTL1_RID          (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
 920 #define MIPS_GCTL1_EID_SHIFT    24
 921 #define MIPS_GCTL1_EID_WIDTH    8
 922 #define MIPS_GCTL1_EID          (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
 923
 924 /* GuestID reserved for root context */
 925 #define MIPS_GCTL1_ROOT_GUESTID 0
 926
 927 /* CDMMBase register bit definitions */
 928 #define MIPS_CDMMBASE_SIZE_SHIFT 0
 929 #define MIPS_CDMMBASE_SIZE      (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
 930 #define MIPS_CDMMBASE_CI        (_ULCAST_(1) << 9)
 931 #define MIPS_CDMMBASE_EN        (_ULCAST_(1) << 10)
 932 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 933 #define MIPS_CDMMBASE_ADDR_START 15
 934
 935 /* RDHWR register numbers */
 936 #define MIPS_HWR_CPUNUM         0       /* CPU number */
 937 #define MIPS_HWR_SYNCISTEP      1       /* SYNCI step size */
 938 #define MIPS_HWR_CC             2       /* Cycle counter */
 939 #define MIPS_HWR_CCRES          3       /* Cycle counter resolution */
 940 #define MIPS_HWR_ULR            29      /* UserLocal */
 941 #define MIPS_HWR_IMPL1          30      /* Implementation dependent */
 942 #define MIPS_HWR_IMPL2          31      /* Implementation dependent */
 943
 944 /* Bits in HWREna register */
 945 #define MIPS_HWRENA_CPUNUM      (_ULCAST_(1) << MIPS_HWR_CPUNUM)
 946 #define MIPS_HWRENA_SYNCISTEP   (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
 947 #define MIPS_HWRENA_CC          (_ULCAST_(1) << MIPS_HWR_CC)
 948 #define MIPS_HWRENA_CCRES       (_ULCAST_(1) << MIPS_HWR_CCRES)
 949 #define MIPS_HWRENA_ULR         (_ULCAST_(1) << MIPS_HWR_ULR)
 950 #define MIPS_HWRENA_IMPL1       (_ULCAST_(1) << MIPS_HWR_IMPL1)
 951 #define MIPS_HWRENA_IMPL2       (_ULCAST_(1) << MIPS_HWR_IMPL2)
 952
 953 /*
 954  * Bitfields in the TX39 family CP0 Configuration Register 3
 955  */
 956 #define TX39_CONF_ICS_SHIFT     19
 957 #define TX39_CONF_ICS_MASK      0x00380000
 958 #define TX39_CONF_ICS_1KB       0x00000000
 959 #define TX39_CONF_ICS_2KB       0x00080000
 960 #define TX39_CONF_ICS_4KB       0x00100000
 961 #define TX39_CONF_ICS_8KB       0x00180000
 962 #define TX39_CONF_ICS_16KB      0x00200000
 963
 964 #define TX39_CONF_DCS_SHIFT     16
 965 #define TX39_CONF_DCS_MASK      0x00070000
 966 #define TX39_CONF_DCS_1KB       0x00000000
 967 #define TX39_CONF_DCS_2KB       0x00010000
 968 #define TX39_CONF_DCS_4KB       0x00020000
 969 #define TX39_CONF_DCS_8KB       0x00030000
 970 #define TX39_CONF_DCS_16KB      0x00040000
 971
 972 #define TX39_CONF_CWFON         0x00004000
 973 #define TX39_CONF_WBON          0x00002000
 974 #define TX39_CONF_RF_SHIFT      10
 975 #define TX39_CONF_RF_MASK       0x00000c00
 976 #define TX39_CONF_DOZE          0x00000200
 977 #define TX39_CONF_HALT          0x00000100
 978 #define TX39_CONF_LOCK          0x00000080
 979 #define TX39_CONF_ICE           0x00000020
 980 #define TX39_CONF_DCE           0x00000010
 981 #define TX39_CONF_IRSIZE_SHIFT  2
 982 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 983 #define TX39_CONF_DRSIZE_SHIFT  0
 984 #define TX39_CONF_DRSIZE_MASK   0x00000003
 985
 986 /*
 987  * Interesting Bits in the R10K CP0 Branch Diagnostic Register
 988  */
 989 /* Disable Branch Target Address Cache */
 990 #define R10K_DIAG_D_BTAC        (_ULCAST_(1) << 27)
 991 /* Enable Branch Prediction Global History */
 992 #define R10K_DIAG_E_GHIST       (_ULCAST_(1) << 26)
 993 /* Disable Branch Return Cache */
 994 #define R10K_DIAG_D_BRC         (_ULCAST_(1) << 22)
 995
 996 /* Flush ITLB */
 997 #define LOONGSON_DIAG_ITLB      (_ULCAST_(1) << 2)
 998 /* Flush DTLB */
 999 #define LOONGSON_DIAG_DTLB      (_ULCAST_(1) << 3)
1000 /* Flush VTLB */
1001 #define LOONGSON_DIAG_VTLB      (_ULCAST_(1) << 12)
1002 /* Flush FTLB */
1003 #define LOONGSON_DIAG_FTLB      (_ULCAST_(1) << 13)
1004
1005 /* CvmCtl register field definitions */
1006 #define CVMCTL_IPPCI_SHIFT      7
1007 #define CVMCTL_IPPCI            (_U64CAST_(0x7) << CVMCTL_IPPCI_SHIFT)
1008 #define CVMCTL_IPTI_SHIFT       4
1009 #define CVMCTL_IPTI             (_U64CAST_(0x7) << CVMCTL_IPTI_SHIFT)
1010
1011 /* CvmMemCtl2 register field definitions */
1012 #define CVMMEMCTL2_INHIBITTS    (_U64CAST_(1) << 17)
1013
1014 /* CvmVMConfig register field definitions */
1015 #define CVMVMCONF_DGHT          (_U64CAST_(1) << 60)
1016 #define CVMVMCONF_MMUSIZEM1_S   12
1017 #define CVMVMCONF_MMUSIZEM1     (_U64CAST_(0xff) << CVMVMCONF_MMUSIZEM1_S)
1018 #define CVMVMCONF_RMMUSIZEM1_S  0
1019 #define CVMVMCONF_RMMUSIZEM1    (_U64CAST_(0xff) << CVMVMCONF_RMMUSIZEM1_S)
1020
1021 /*
1022  * Coprocessor 1 (FPU) register names
1023  */
1024 #define CP1_REVISION    $0
1025 #define CP1_UFR         $1
1026 #define CP1_UNFR        $4
1027 #define CP1_FCCR        $25
1028 #define CP1_FEXR        $26
1029 #define CP1_FENR        $28
1030 #define CP1_STATUS      $31
1031
1032
1033 /*
1034  * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
1035  */
1036 #define MIPS_FPIR_S             (_ULCAST_(1) << 16)
1037 #define MIPS_FPIR_D             (_ULCAST_(1) << 17)
1038 #define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
1039 #define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
1040 #define MIPS_FPIR_W             (_ULCAST_(1) << 20)
1041 #define MIPS_FPIR_L             (_ULCAST_(1) << 21)
1042 #define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
1043 #define MIPS_FPIR_HAS2008       (_ULCAST_(1) << 23)
1044 #define MIPS_FPIR_UFRP          (_ULCAST_(1) << 28)
1045 #define MIPS_FPIR_FREP          (_ULCAST_(1) << 29)
1046
1047 /*
1048  * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
1049  */
1050 #define MIPS_FCCR_CONDX_S       0
1051 #define MIPS_FCCR_CONDX         (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
1052 #define MIPS_FCCR_COND0_S       0
1053 #define MIPS_FCCR_COND0         (_ULCAST_(1) << MIPS_FCCR_COND0_S)
1054 #define MIPS_FCCR_COND1_S       1
1055 #define MIPS_FCCR_COND1         (_ULCAST_(1) << MIPS_FCCR_COND1_S)
1056 #define MIPS_FCCR_COND2_S       2
1057 #define MIPS_FCCR_COND2         (_ULCAST_(1) << MIPS_FCCR_COND2_S)
1058 #define MIPS_FCCR_COND3_S       3
1059 #define MIPS_FCCR_COND3         (_ULCAST_(1) << MIPS_FCCR_COND3_S)
1060 #define MIPS_FCCR_COND4_S       4
1061 #define MIPS_FCCR_COND4         (_ULCAST_(1) << MIPS_FCCR_COND4_S)
1062 #define MIPS_FCCR_COND5_S       5
1063 #define MIPS_FCCR_COND5         (_ULCAST_(1) << MIPS_FCCR_COND5_S)
1064 #define MIPS_FCCR_COND6_S       6
1065 #define MIPS_FCCR_COND6         (_ULCAST_(1) << MIPS_FCCR_COND6_S)
1066 #define MIPS_FCCR_COND7_S       7
1067 #define MIPS_FCCR_COND7         (_ULCAST_(1) << MIPS_FCCR_COND7_S)
1068
1069 /*
1070  * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
1071  */
1072 #define MIPS_FENR_FS_S          2
1073 #define MIPS_FENR_FS            (_ULCAST_(1) << MIPS_FENR_FS_S)
1074
1075 /*
1076  * FPU Status Register Values
1077  */
1078 #define FPU_CSR_COND_S  23                                      /* $fcc0 */
1079 #define FPU_CSR_COND    (_ULCAST_(1) << FPU_CSR_COND_S)
1080
1081 #define FPU_CSR_FS_S    24              /* flush denormalised results to 0 */
1082 #define FPU_CSR_FS      (_ULCAST_(1) << FPU_CSR_FS_S)
1083
1084 #define FPU_CSR_CONDX_S 25                                      /* $fcc[7:1] */
1085 #define FPU_CSR_CONDX   (_ULCAST_(127) << FPU_CSR_CONDX_S)
1086 #define FPU_CSR_COND1_S 25                                      /* $fcc1 */
1087 #define FPU_CSR_COND1   (_ULCAST_(1) << FPU_CSR_COND1_S)
1088 #define FPU_CSR_COND2_S 26                                      /* $fcc2 */
1089 #define FPU_CSR_COND2   (_ULCAST_(1) << FPU_CSR_COND2_S)
1090 #define FPU_CSR_COND3_S 27                                      /* $fcc3 */
1091 #define FPU_CSR_COND3   (_ULCAST_(1) << FPU_CSR_COND3_S)
1092 #define FPU_CSR_COND4_S 28                                      /* $fcc4 */
1093 #define FPU_CSR_COND4   (_ULCAST_(1) << FPU_CSR_COND4_S)
1094 #define FPU_CSR_COND5_S 29                                      /* $fcc5 */
1095 #define FPU_CSR_COND5   (_ULCAST_(1) << FPU_CSR_COND5_S)
1096 #define FPU_CSR_COND6_S 30                                      /* $fcc6 */
1097 #define FPU_CSR_COND6   (_ULCAST_(1) << FPU_CSR_COND6_S)
1098 #define FPU_CSR_COND7_S 31                                      /* $fcc7 */
1099 #define FPU_CSR_COND7   (_ULCAST_(1) << FPU_CSR_COND7_S)
1100
1101 /*
1102  * Bits 22:20 of the FPU Status Register will be read as 0,
1103  * and should be written as zero.
1104  * MAC2008 was removed in Release 5 so we still treat it as
1105  * reserved.
1106  */
1107 #define FPU_CSR_RSVD    (_ULCAST_(7) << 20)
1108
1109 #define FPU_CSR_MAC2008 (_ULCAST_(1) << 20)
1110 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1111 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1112
1113 /*
1114  * X the exception cause indicator
1115  * E the exception enable
1116  * S the sticky/flag bit
1117 */
1118 #define FPU_CSR_ALL_X   0x0003f000
1119 #define FPU_CSR_UNI_X   0x00020000
1120 #define FPU_CSR_INV_X   0x00010000
1121 #define FPU_CSR_DIV_X   0x00008000
1122 #define FPU_CSR_OVF_X   0x00004000
1123 #define FPU_CSR_UDF_X   0x00002000
1124 #define FPU_CSR_INE_X   0x00001000
1125
1126 #define FPU_CSR_ALL_E   0x00000f80
1127 #define FPU_CSR_INV_E   0x00000800
1128 #define FPU_CSR_DIV_E   0x00000400
1129 #define FPU_CSR_OVF_E   0x00000200
1130 #define FPU_CSR_UDF_E   0x00000100
1131 #define FPU_CSR_INE_E   0x00000080
1132
1133 #define FPU_CSR_ALL_S   0x0000007c
1134 #define FPU_CSR_INV_S   0x00000040
1135 #define FPU_CSR_DIV_S   0x00000020
1136 #define FPU_CSR_OVF_S   0x00000010
1137 #define FPU_CSR_UDF_S   0x00000008
1138 #define FPU_CSR_INE_S   0x00000004
1139
1140 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1141 #define FPU_CSR_RM      0x00000003
1142 #define FPU_CSR_RN      0x0     /* nearest */
1143 #define FPU_CSR_RZ      0x1     /* towards zero */
1144 #define FPU_CSR_RU      0x2     /* towards +Infinity */
1145 #define FPU_CSR_RD      0x3     /* towards -Infinity */
1146
1147
1148 #ifndef __ASSEMBLY__
1149
1150 /*
1151  * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1152  */
1153 #if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1154     defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1155 #define get_isa16_mode(x)               ((x) & 0x1)
1156 #define msk_isa16_mode(x)               ((x) & ~0x1)
1157 #define set_isa16_mode(x)               do { (x) |= 0x1; } while(0)
1158 #else
1159 #define get_isa16_mode(x)               0
1160 #define msk_isa16_mode(x)               (x)
1161 #define set_isa16_mode(x)               do { } while(0)
1162 #endif
1163
1164 /*
1165  * microMIPS instructions can be 16-bit or 32-bit in length. This
1166  * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1167  */
1168 static inline int mm_insn_16bit(u16 insn)
1169 {
1170         u16 opcode = (insn >> 10) & 0x7;
1171
1172         return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1173 }
1174
1175 /*
1176  * Helper macros for generating raw instruction encodings in inline asm.
1177  */
1178 #ifdef CONFIG_CPU_MICROMIPS
1179 #define _ASM_INSN16_IF_MM(_enc)                 \
1180         ".insn\n\t"                             \
1181         ".hword (" #_enc ")\n\t"
1182 #define _ASM_INSN32_IF_MM(_enc)                 \
1183         ".insn\n\t"                             \
1184         ".hword ((" #_enc ") >> 16)\n\t"        \
1185         ".hword ((" #_enc ") & 0xffff)\n\t"
1186 #else
1187 #define _ASM_INSN_IF_MIPS(_enc)                 \
1188         ".insn\n\t"                             \
1189         ".word (" #_enc ")\n\t"
1190 #endif
1191
1192 #ifndef _ASM_INSN16_IF_MM
1193 #define _ASM_INSN16_IF_MM(_enc)
1194 #endif
1195 #ifndef _ASM_INSN32_IF_MM
1196 #define _ASM_INSN32_IF_MM(_enc)
1197 #endif
1198 #ifndef _ASM_INSN_IF_MIPS
1199 #define _ASM_INSN_IF_MIPS(_enc)
1200 #endif
1201
1202 /*
1203  * parse_r var, r - Helper assembler macro for parsing register names.
1204  *
1205  * This converts the register name in $n form provided in \r to the
1206  * corresponding register number, which is assigned to the variable \var. It is
1207  * needed to allow explicit encoding of instructions in inline assembly where
1208  * registers are chosen by the compiler in $n form, allowing us to avoid using
1209  * fixed register numbers.
1210  *
1211  * It also allows newer instructions (not implemented by the assembler) to be
1212  * transparently implemented using assembler macros, instead of needing separate
1213  * cases depending on toolchain support.
1214  *
1215  * Simple usage example:
1216  * __asm__ __volatile__("parse_r __rt, %0\n\t"
1217  *                      ".insn\n\t"
1218  *                      "# di    %0\n\t"
1219  *                      ".word   (0x41606000 | (__rt << 16))"
1220  *                      : "=r" (status);
1221  */
1222
1223 /* Match an individual register number and assign to \var */
1224 #define _IFC_REG(n)                             \
1225         ".ifc   \\r, $" #n "\n\t"               \
1226         "\\var  = " #n "\n\t"                   \
1227         ".endif\n\t"
1228
1229 __asm__(".macro parse_r var r\n\t"
1230         "\\var  = -1\n\t"
1231         _IFC_REG(0)  _IFC_REG(1)  _IFC_REG(2)  _IFC_REG(3)
1232         _IFC_REG(4)  _IFC_REG(5)  _IFC_REG(6)  _IFC_REG(7)
1233         _IFC_REG(8)  _IFC_REG(9)  _IFC_REG(10) _IFC_REG(11)
1234         _IFC_REG(12) _IFC_REG(13) _IFC_REG(14) _IFC_REG(15)
1235         _IFC_REG(16) _IFC_REG(17) _IFC_REG(18) _IFC_REG(19)
1236         _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23)
1237         _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27)
1238         _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31)
1239         ".iflt  \\var\n\t"
1240         ".error \"Unable to parse register name \\r\"\n\t"
1241         ".endif\n\t"
1242         ".endm");
1243
1244 #undef _IFC_REG
1245
1246 /*
1247  * C macros for generating assembler macros for common instruction formats.
1248  *
1249  * The names of the operands can be chosen by the caller, and the encoding of
1250  * register operand \<Rn> is assigned to __<Rn> where it can be accessed from
1251  * the ENC encodings.
1252  */
1253
1254 /* Instructions with no operands */
1255 #define _ASM_MACRO_0(OP, ENC)                                           \
1256         __asm__(".macro " #OP "\n\t"                                    \
1257                 ENC                                                     \
1258                 ".endm")
1259
1260 /* Instructions with 1 register operand & 1 immediate operand */
1261 #define _ASM_MACRO_1R1I(OP, R1, I2, ENC)                                \
1262         __asm__(".macro " #OP " " #R1 ", " #I2 "\n\t"                   \
1263                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1264                 ENC                                                     \
1265                 ".endm")
1266
1267 /* Instructions with 2 register operands */
1268 #define _ASM_MACRO_2R(OP, R1, R2, ENC)                                  \
1269         __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t"                   \
1270                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1271                 "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
1272                 ENC                                                     \
1273                 ".endm")
1274
1275 /* Instructions with 3 register operands */
1276 #define _ASM_MACRO_3R(OP, R1, R2, R3, ENC)                              \
1277         __asm__(".macro " #OP " " #R1 ", " #R2 ", " #R3 "\n\t"          \
1278                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1279                 "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
1280                 "parse_r __" #R3 ", \\" #R3 "\n\t"                      \
1281                 ENC                                                     \
1282                 ".endm")
1283
1284 /* Instructions with 2 register operands and 1 optional select operand */
1285 #define _ASM_MACRO_2R_1S(OP, R1, R2, SEL3, ENC)                         \
1286         __asm__(".macro " #OP " " #R1 ", " #R2 ", " #SEL3 " = 0\n\t"    \
1287                 "parse_r __" #R1 ", \\" #R1 "\n\t"                      \
1288                 "parse_r __" #R2 ", \\" #R2 "\n\t"                      \
1289                 ENC                                                     \
1290                 ".endm")
1291
1292 /*
1293  * TLB Invalidate Flush
1294  */
1295 static inline void tlbinvf(void)
1296 {
1297         __asm__ __volatile__(
1298                 ".set push\n\t"
1299                 ".set noreorder\n\t"
1300                 "# tlbinvf\n\t"
1301                 _ASM_INSN_IF_MIPS(0x42000004)
1302                 _ASM_INSN32_IF_MM(0x0000537c)
1303                 ".set pop");
1304 }
1305
1306
1307 /*
1308  * Functions to access the R10000 performance counters.  These are basically
1309  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1310  * performance counter number encoded into bits 1 ... 5 of the instruction.
1311  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1312  * disassembler these will look like an access to sel 0 or 1.
1313  */
1314 #define read_r10k_perf_cntr(counter)                            \
1315 ({                                                              \
1316         unsigned int __res;                                     \
1317         __asm__ __volatile__(                                   \
1318         "mfpc\t%0, %1"                                          \
1319         : "=r" (__res)                                          \
1320         : "i" (counter));                                       \
1321                                                                 \
1322         __res;                                                  \
1323 })
1324
1325 #define write_r10k_perf_cntr(counter,val)                       \
1326 do {                                                            \
1327         __asm__ __volatile__(                                   \
1328         "mtpc\t%0, %1"                                          \
1329         :                                                       \
1330         : "r" (val), "i" (counter));                            \
1331 } while (0)
1332
1333 #define read_r10k_perf_event(counter)                           \
1334 ({                                                              \
1335         unsigned int __res;                                     \
1336         __asm__ __volatile__(                                   \
1337         "mfps\t%0, %1"                                          \
1338         : "=r" (__res)                                          \
1339         : "i" (counter));                                       \
1340                                                                 \
1341         __res;                                                  \
1342 })
1343
1344 #define write_r10k_perf_cntl(counter,val)                       \
1345 do {                                                            \
1346         __asm__ __volatile__(                                   \
1347         "mtps\t%0, %1"                                          \
1348         :                                                       \
1349         : "r" (val), "i" (counter));                            \
1350 } while (0)
1351
1352
1353 /*
1354  * Macros to access the system control coprocessor
1355  */
1356
1357 #define ___read_32bit_c0_register(source, sel, vol)                     \
1358 ({ unsigned int __res;                                                  \
1359         if (sel == 0)                                                   \
1360                 __asm__ vol(                                            \
1361                         "mfc0\t%0, " #source "\n\t"                     \
1362                         : "=r" (__res));                                \
1363         else                                                            \
1364                 __asm__ vol(                                            \
1365                         ".set\tpush\n\t"                                \
1366                         ".set\tmips32\n\t"                              \
1367                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
1368                         ".set\tpop\n\t"                                 \
1369                         : "=r" (__res));                                \
1370         __res;                                                          \
1371 })
1372
1373 #define ___read_64bit_c0_register(source, sel, vol)                     \
1374 ({ unsigned long long __res;                                            \
1375         if (sizeof(unsigned long) == 4)                                 \
1376                 __res = __read_64bit_c0_split(source, sel, vol);        \
1377         else if (sel == 0)                                              \
1378                 __asm__ vol(                                            \
1379                         ".set\tpush\n\t"                                \
1380                         ".set\tmips3\n\t"                               \
1381                         "dmfc0\t%0, " #source "\n\t"                    \
1382                         ".set\tpop"                                     \
1383                         : "=r" (__res));                                \
1384         else                                                            \
1385                 __asm__ vol(                                            \
1386                         ".set\tpush\n\t"                                \
1387                         ".set\tmips64\n\t"                              \
1388                         "dmfc0\t%0, " #source ", " #sel "\n\t"          \
1389                         ".set\tpop"                                     \
1390                         : "=r" (__res));                                \
1391         __res;                                                          \
1392 })
1393
1394 #define __read_32bit_c0_register(source, sel)                           \
1395         ___read_32bit_c0_register(source, sel, __volatile__)
1396
1397 #define __read_const_32bit_c0_register(source, sel)                     \
1398         ___read_32bit_c0_register(source, sel,)
1399
1400 #define __read_64bit_c0_register(source, sel)                           \
1401         ___read_64bit_c0_register(source, sel, __volatile__)
1402
1403 #define __read_const_64bit_c0_register(source, sel)                     \
1404         ___read_64bit_c0_register(source, sel,)
1405
1406 #define __write_32bit_c0_register(register, sel, value)                 \
1407 do {                                                                    \
1408         if (sel == 0)                                                   \
1409                 __asm__ __volatile__(                                   \
1410                         "mtc0\t%z0, " #register "\n\t"                  \
1411                         : : "Jr" ((unsigned int)(value)));              \
1412         else                                                            \
1413                 __asm__ __volatile__(                                   \
1414                         ".set\tpush\n\t"                                \
1415                         ".set\tmips32\n\t"                              \
1416                         "mtc0\t%z0, " #register ", " #sel "\n\t"        \
1417                         ".set\tpop"                                     \
1418                         : : "Jr" ((unsigned int)(value)));              \
1419 } while (0)
1420
1421 #define __write_64bit_c0_register(register, sel, value)                 \
1422 do {                                                                    \
1423         if (sizeof(unsigned long) == 4)                                 \
1424                 __write_64bit_c0_split(register, sel, value);           \
1425         else if (sel == 0)                                              \
1426                 __asm__ __volatile__(                                   \
1427                         ".set\tpush\n\t"                                \
1428                         ".set\tmips3\n\t"                               \
1429                         "dmtc0\t%z0, " #register "\n\t"                 \
1430                         ".set\tpop"                                     \
1431                         : : "Jr" (value));                              \
1432         else                                                            \
1433                 __asm__ __volatile__(                                   \
1434                         ".set\tpush\n\t"                                \
1435                         ".set\tmips64\n\t"                              \
1436                         "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
1437                         ".set\tpop"                                     \
1438                         : : "Jr" (value));                              \
1439 } while (0)
1440
1441 #define __read_ulong_c0_register(reg, sel)                              \
1442         ((sizeof(unsigned long) == 4) ?                                 \
1443         (unsigned long) __read_32bit_c0_register(reg, sel) :            \
1444         (unsigned long) __read_64bit_c0_register(reg, sel))
1445
1446 #define __read_const_ulong_c0_register(reg, sel)                        \
1447         ((sizeof(unsigned long) == 4) ?                                 \
1448         (unsigned long) __read_const_32bit_c0_register(reg, sel) :      \
1449         (unsigned long) __read_const_64bit_c0_register(reg, sel))
1450
1451 #define __write_ulong_c0_register(reg, sel, val)                        \
1452 do {                                                                    \
1453         if (sizeof(unsigned long) == 4)                                 \
1454                 __write_32bit_c0_register(reg, sel, val);               \
1455         else                                                            \
1456                 __write_64bit_c0_register(reg, sel, val);               \
1457 } while (0)
1458
1459 /*
1460  * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1461  */
1462 #define __read_32bit_c0_ctrl_register(source)                           \
1463 ({ unsigned int __res;                                                  \
1464         __asm__ __volatile__(                                           \
1465                 "cfc0\t%0, " #source "\n\t"                             \
1466                 : "=r" (__res));                                        \
1467         __res;                                                          \
1468 })
1469
1470 #define __write_32bit_c0_ctrl_register(register, value)                 \
1471 do {                                                                    \
1472         __asm__ __volatile__(                                           \
1473                 "ctc0\t%z0, " #register "\n\t"                          \
1474                 : : "Jr" ((unsigned int)(value)));                      \
1475 } while (0)
1476
1477 /*
1478  * These versions are only needed for systems with more than 38 bits of
1479  * physical address space running the 32-bit kernel.  That's none atm :-)
1480  */
1481 #define __read_64bit_c0_split(source, sel, vol)                         \
1482 ({                                                                      \
1483         unsigned long long __val;                                       \
1484         unsigned long __flags;                                          \
1485                                                                         \
1486         local_irq_save(__flags);                                        \
1487         if (sel == 0)                                                   \
1488                 __asm__ vol(                                            \
1489                         ".set\tpush\n\t"                                \
1490                         ".set\tmips64\n\t"                              \
1491                         "dmfc0\t%L0, " #source "\n\t"                   \
1492                         "dsra\t%M0, %L0, 32\n\t"                        \
1493                         "sll\t%L0, %L0, 0\n\t"                          \
1494                         ".set\tpop"                                     \
1495                         : "=r" (__val));                                \
1496         else                                                            \
1497                 __asm__ vol(                                            \
1498                         ".set\tpush\n\t"                                \
1499                         ".set\tmips64\n\t"                              \
1500                         "dmfc0\t%L0, " #source ", " #sel "\n\t"         \
1501                         "dsra\t%M0, %L0, 32\n\t"                        \
1502                         "sll\t%L0, %L0, 0\n\t"                          \
1503                         ".set\tpop"                                     \
1504                         : "=r" (__val));                                \
1505         local_irq_restore(__flags);                                     \
1506                                                                         \
1507         __val;                                                          \
1508 })
1509
1510 #define __write_64bit_c0_split(source, sel, val)                        \
1511 do {                                                                    \
1512         unsigned long long __tmp = (val);                               \
1513         unsigned long __flags;                                          \
1514                                                                         \
1515         local_irq_save(__flags);                                        \
1516         if (MIPS_ISA_REV >= 2)                                          \
1517                 __asm__ __volatile__(                                   \
1518                         ".set\tpush\n\t"                                \
1519                         ".set\t" MIPS_ISA_LEVEL "\n\t"                  \
1520                         "dins\t%L0, %M0, 32, 32\n\t"                    \
1521                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1522                         ".set\tpop"                                     \
1523                         : "+r" (__tmp));                                \
1524         else if (sel == 0)                                              \
1525                 __asm__ __volatile__(                                   \
1526                         ".set\tpush\n\t"                                \
1527                         ".set\tmips64\n\t"                              \
1528                         "dsll\t%L0, %L0, 32\n\t"                        \
1529                         "dsrl\t%L0, %L0, 32\n\t"                        \
1530                         "dsll\t%M0, %M0, 32\n\t"                        \
1531                         "or\t%L0, %L0, %M0\n\t"                         \
1532                         "dmtc0\t%L0, " #source "\n\t"                   \
1533                         ".set\tpop"                                     \
1534                         : "+r" (__tmp));                                \
1535         else                                                            \
1536                 __asm__ __volatile__(                                   \
1537                         ".set\tpush\n\t"                                \
1538                         ".set\tmips64\n\t"                              \
1539                         "dsll\t%L0, %L0, 32\n\t"                        \
1540                         "dsrl\t%L0, %L0, 32\n\t"                        \
1541                         "dsll\t%M0, %M0, 32\n\t"                        \
1542                         "or\t%L0, %L0, %M0\n\t"                         \
1543                         "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
1544                         ".set\tpop"                                     \
1545                         : "+r" (__tmp));                                \
1546         local_irq_restore(__flags);                                     \
1547 } while (0)
1548
1549 #ifndef TOOLCHAIN_SUPPORTS_XPA
1550 _ASM_MACRO_2R_1S(mfhc0, rt, rs, sel,
1551         _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel)
1552         _ASM_INSN32_IF_MM(0x000000f4 | __rt << 21 | __rs << 16 | \\sel << 11));
1553 _ASM_MACRO_2R_1S(mthc0, rt, rd, sel,
1554         _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel)
1555         _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11));
1556 #define _ASM_SET_XPA ""
1557 #else   /* !TOOLCHAIN_SUPPORTS_XPA */
1558 #define _ASM_SET_XPA ".set\txpa\n\t"
1559 #endif
1560
1561 #define __readx_32bit_c0_register(source, sel)                          \
1562 ({                                                                      \
1563         unsigned int __res;                                             \
1564                                                                         \
1565         __asm__ __volatile__(                                           \
1566         "       .set    push                                    \n"     \
1567         "       .set    mips32r2                                \n"     \
1568         _ASM_SET_XPA                                                    \
1569         "       mfhc0   %0, " #source ", %1                     \n"     \
1570         "       .set    pop                                     \n"     \
1571         : "=r" (__res)                                                  \
1572         : "i" (sel));                                                   \
1573         __res;                                                          \
1574 })
1575
1576 #define __writex_32bit_c0_register(register, sel, value)                \
1577 do {                                                                    \
1578         __asm__ __volatile__(                                           \
1579         "       .set    push                                    \n"     \
1580         "       .set    mips32r2                                \n"     \
1581         _ASM_SET_XPA                                                    \
1582         "       mthc0   %z0, " #register ", %1                  \n"     \
1583         "       .set    pop                                     \n"     \
1584         :                                                               \
1585         : "Jr" (value), "i" (sel));                                     \
1586 } while (0)
1587
1588 #define read_c0_index()         __read_32bit_c0_register($0, 0)
1589 #define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
1590
1591 #define read_c0_random()        __read_32bit_c0_register($1, 0)
1592 #define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
1593
1594 #define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
1595 #define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
1596
1597 #define readx_c0_entrylo0()     __readx_32bit_c0_register($2, 0)
1598 #define writex_c0_entrylo0(val) __writex_32bit_c0_register($2, 0, val)
1599
1600 #define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
1601 #define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
1602
1603 #define readx_c0_entrylo1()     __readx_32bit_c0_register($3, 0)
1604 #define writex_c0_entrylo1(val) __writex_32bit_c0_register($3, 0, val)
1605
1606 #define read_c0_conf()          __read_32bit_c0_register($3, 0)
1607 #define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
1608
1609 #define read_c0_globalnumber()  __read_32bit_c0_register($3, 1)
1610
1611 #define read_c0_context()       __read_ulong_c0_register($4, 0)
1612 #define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
1613
1614 #define read_c0_contextconfig()         __read_32bit_c0_register($4, 1)
1615 #define write_c0_contextconfig(val)     __write_32bit_c0_register($4, 1, val)
1616
1617 #define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
1618 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1619
1620 #define read_c0_xcontextconfig()        __read_ulong_c0_register($4, 3)
1621 #define write_c0_xcontextconfig(val)    __write_ulong_c0_register($4, 3, val)
1622
1623 #define read_c0_memorymapid()           __read_32bit_c0_register($4, 5)
1624 #define write_c0_memorymapid(val)       __write_32bit_c0_register($4, 5, val)
1625
1626 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
1627 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
1628
1629 #define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
1630 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1631
1632 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
1633 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
1634
1635 #define read_c0_info()          __read_32bit_c0_register($7, 0)
1636
1637 #define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
1638 #define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
1639
1640 #define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
1641 #define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
1642
1643 #define read_c0_badinstr()      __read_32bit_c0_register($8, 1)
1644 #define read_c0_badinstrp()     __read_32bit_c0_register($8, 2)
1645
1646 #define read_c0_count()         __read_32bit_c0_register($9, 0)
1647 #define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
1648
1649 #define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
1650 #define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
1651
1652 #define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
1653 #define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
1654
1655 #define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
1656 #define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
1657
1658 #define read_c0_guestctl1()     __read_32bit_c0_register($10, 4)
1659 #define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1660
1661 #define read_c0_guestctl2()     __read_32bit_c0_register($10, 5)
1662 #define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1663
1664 #define read_c0_guestctl3()     __read_32bit_c0_register($10, 6)
1665 #define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1666
1667 #define read_c0_compare()       __read_32bit_c0_register($11, 0)
1668 #define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
1669
1670 #define read_c0_guestctl0ext()  __read_32bit_c0_register($11, 4)
1671 #define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1672
1673 #define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
1674 #define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
1675
1676 #define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
1677 #define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
1678
1679 #define read_c0_status()        __read_32bit_c0_register($12, 0)
1680
1681 #define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
1682
1683 #define read_c0_guestctl0()     __read_32bit_c0_register($12, 6)
1684 #define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1685
1686 #define read_c0_gtoffset()      __read_32bit_c0_register($12, 7)
1687 #define write_c0_gtoffset(val)  __write_32bit_c0_register($12, 7, val)
1688
1689 #define read_c0_cause()         __read_32bit_c0_register($13, 0)
1690 #define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
1691
1692 #define read_c0_epc()           __read_ulong_c0_register($14, 0)
1693 #define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
1694
1695 #define read_c0_prid()          __read_const_32bit_c0_register($15, 0)
1696
1697 #define read_c0_cmgcrbase()     __read_ulong_c0_register($15, 3)
1698
1699 #define read_c0_config()        __read_32bit_c0_register($16, 0)
1700 #define read_c0_config1()       __read_32bit_c0_register($16, 1)
1701 #define read_c0_config2()       __read_32bit_c0_register($16, 2)
1702 #define read_c0_config3()       __read_32bit_c0_register($16, 3)
1703 #define read_c0_config4()       __read_32bit_c0_register($16, 4)
1704 #define read_c0_config5()       __read_32bit_c0_register($16, 5)
1705 #define read_c0_config6()       __read_32bit_c0_register($16, 6)
1706 #define read_c0_config7()       __read_32bit_c0_register($16, 7)
1707 #define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
1708 #define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
1709 #define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
1710 #define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
1711 #define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
1712 #define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
1713 #define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
1714 #define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
1715
1716 #define read_c0_lladdr()        __read_ulong_c0_register($17, 0)
1717 #define write_c0_lladdr(val)    __write_ulong_c0_register($17, 0, val)
1718 #define read_c0_maar()          __read_ulong_c0_register($17, 1)
1719 #define write_c0_maar(val)      __write_ulong_c0_register($17, 1, val)
1720 #define read_c0_maari()         __read_32bit_c0_register($17, 2)
1721 #define write_c0_maari(val)     __write_32bit_c0_register($17, 2, val)
1722
1723 /*
1724  * The WatchLo register.  There may be up to 8 of them.
1725  */
1726 #define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
1727 #define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
1728 #define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
1729 #define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
1730 #define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
1731 #define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
1732 #define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
1733 #define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
1734 #define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
1735 #define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
1736 #define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
1737 #define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
1738 #define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
1739 #define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
1740 #define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
1741 #define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
1742
1743 /*
1744  * The WatchHi register.  There may be up to 8 of them.
1745  */
1746 #define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
1747 #define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
1748 #define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
1749 #define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
1750 #define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
1751 #define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
1752 #define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
1753 #define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
1754
1755 #define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
1756 #define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
1757 #define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
1758 #define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
1759 #define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
1760 #define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
1761 #define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
1762 #define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
1763
1764 #define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
1765 #define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
1766
1767 #define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
1768 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1769
1770 #define read_c0_framemask()     __read_32bit_c0_register($21, 0)
1771 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1772
1773 #define read_c0_diag()          __read_32bit_c0_register($22, 0)
1774 #define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
1775
1776 /* R10K CP0 Branch Diagnostic register is 64bits wide */
1777 #define read_c0_r10k_diag()     __read_64bit_c0_register($22, 0)
1778 #define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1779
1780 #define read_c0_diag1()         __read_32bit_c0_register($22, 1)
1781 #define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
1782
1783 #define read_c0_diag2()         __read_32bit_c0_register($22, 2)
1784 #define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
1785
1786 #define read_c0_diag3()         __read_32bit_c0_register($22, 3)
1787 #define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
1788
1789 #define read_c0_diag4()         __read_32bit_c0_register($22, 4)
1790 #define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
1791
1792 #define read_c0_diag5()         __read_32bit_c0_register($22, 5)
1793 #define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
1794
1795 #define read_c0_debug()         __read_32bit_c0_register($23, 0)
1796 #define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
1797
1798 #define read_c0_depc()          __read_ulong_c0_register($24, 0)
1799 #define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
1800
1801 /*
1802  * MIPS32 / MIPS64 performance counters
1803  */
1804 #define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
1805 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1806 #define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
1807 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1808 #define read_c0_perfcntr0_64()  __read_64bit_c0_register($25, 1)
1809 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1810 #define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
1811 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1812 #define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
1813 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1814 #define read_c0_perfcntr1_64()  __read_64bit_c0_register($25, 3)
1815 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1816 #define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
1817 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1818 #define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
1819 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1820 #define read_c0_perfcntr2_64()  __read_64bit_c0_register($25, 5)
1821 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1822 #define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
1823 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1824 #define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
1825 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1826 #define read_c0_perfcntr3_64()  __read_64bit_c0_register($25, 7)
1827 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1828
1829 #define read_c0_ecc()           __read_32bit_c0_register($26, 0)
1830 #define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
1831
1832 #define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
1833 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1834
1835 #define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
1836
1837 #define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
1838 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1839
1840 #define read_c0_taglo()         __read_32bit_c0_register($28, 0)
1841 #define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
1842
1843 #define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
1844 #define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
1845
1846 #define read_c0_ddatalo()       __read_32bit_c0_register($28, 3)
1847 #define write_c0_ddatalo(val)   __write_32bit_c0_register($28, 3, val)
1848
1849 #define read_c0_staglo()        __read_32bit_c0_register($28, 4)
1850 #define write_c0_staglo(val)    __write_32bit_c0_register($28, 4, val)
1851
1852 #define read_c0_taghi()         __read_32bit_c0_register($29, 0)
1853 #define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
1854
1855 #define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
1856 #define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
1857
1858 /* MIPSR2 */
1859 #define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
1860 #define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
1861
1862 #define read_c0_intctl()        __read_32bit_c0_register($12, 1)
1863 #define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
1864
1865 #define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
1866 #define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
1867
1868 #define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
1869 #define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
1870
1871 #define read_c0_ebase()         __read_32bit_c0_register($15, 1)
1872 #define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
1873
1874 #define read_c0_ebase_64()      __read_64bit_c0_register($15, 1)
1875 #define write_c0_ebase_64(val)  __write_64bit_c0_register($15, 1, val)
1876
1877 #define read_c0_cdmmbase()      __read_ulong_c0_register($15, 2)
1878 #define write_c0_cdmmbase(val)  __write_ulong_c0_register($15, 2, val)
1879
1880 /* MIPSR3 */
1881 #define read_c0_segctl0()       __read_32bit_c0_register($5, 2)
1882 #define write_c0_segctl0(val)   __write_32bit_c0_register($5, 2, val)
1883
1884 #define read_c0_segctl1()       __read_32bit_c0_register($5, 3)
1885 #define write_c0_segctl1(val)   __write_32bit_c0_register($5, 3, val)
1886
1887 #define read_c0_segctl2()       __read_32bit_c0_register($5, 4)
1888 #define write_c0_segctl2(val)   __write_32bit_c0_register($5, 4, val)
1889
1890 /* Hardware Page Table Walker */
1891 #define read_c0_pwbase()        __read_ulong_c0_register($5, 5)
1892 #define write_c0_pwbase(val)    __write_ulong_c0_register($5, 5, val)
1893
1894 #define read_c0_pwfield()       __read_ulong_c0_register($5, 6)
1895 #define write_c0_pwfield(val)   __write_ulong_c0_register($5, 6, val)
1896
1897 #define read_c0_pwsize()        __read_ulong_c0_register($5, 7)
1898 #define write_c0_pwsize(val)    __write_ulong_c0_register($5, 7, val)
1899
1900 #define read_c0_pwctl()         __read_32bit_c0_register($6, 6)
1901 #define write_c0_pwctl(val)     __write_32bit_c0_register($6, 6, val)
1902
1903 #define read_c0_pgd()           __read_64bit_c0_register($9, 7)
1904 #define write_c0_pgd(val)       __write_64bit_c0_register($9, 7, val)
1905
1906 #define read_c0_kpgd()          __read_64bit_c0_register($31, 7)
1907 #define write_c0_kpgd(val)      __write_64bit_c0_register($31, 7, val)
1908
1909 /* Cavium OCTEON (cnMIPS) */
1910 #define read_c0_cvmcount()      __read_ulong_c0_register($9, 6)
1911 #define write_c0_cvmcount(val)  __write_ulong_c0_register($9, 6, val)
1912
1913 #define read_c0_cvmctl()        __read_64bit_c0_register($9, 7)
1914 #define write_c0_cvmctl(val)    __write_64bit_c0_register($9, 7, val)
1915
1916 #define read_c0_cvmmemctl()     __read_64bit_c0_register($11, 7)
1917 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1918
1919 #define read_c0_cvmmemctl2()    __read_64bit_c0_register($16, 6)
1920 #define write_c0_cvmmemctl2(val) __write_64bit_c0_register($16, 6, val)
1921
1922 #define read_c0_cvmvmconfig()   __read_64bit_c0_register($16, 7)
1923 #define write_c0_cvmvmconfig(val) __write_64bit_c0_register($16, 7, val)
1924
1925 /*
1926  * The cacheerr registers are not standardized.  On OCTEON, they are
1927  * 64 bits wide.
1928  */
1929 #define read_octeon_c0_icacheerr()      __read_64bit_c0_register($27, 0)
1930 #define write_octeon_c0_icacheerr(val)  __write_64bit_c0_register($27, 0, val)
1931
1932 #define read_octeon_c0_dcacheerr()      __read_64bit_c0_register($27, 1)
1933 #define write_octeon_c0_dcacheerr(val)  __write_64bit_c0_register($27, 1, val)
1934
1935 /* BMIPS3300 */
1936 #define read_c0_brcm_config_0()         __read_32bit_c0_register($22, 0)
1937 #define write_c0_brcm_config_0(val)     __write_32bit_c0_register($22, 0, val)
1938
1939 #define read_c0_brcm_bus_pll()          __read_32bit_c0_register($22, 4)
1940 #define write_c0_brcm_bus_pll(val)      __write_32bit_c0_register($22, 4, val)
1941
1942 #define read_c0_brcm_reset()            __read_32bit_c0_register($22, 5)
1943 #define write_c0_brcm_reset(val)        __write_32bit_c0_register($22, 5, val)
1944
1945 /* BMIPS43xx */
1946 #define read_c0_brcm_cmt_intr()         __read_32bit_c0_register($22, 1)
1947 #define write_c0_brcm_cmt_intr(val)     __write_32bit_c0_register($22, 1, val)
1948
1949 #define read_c0_brcm_cmt_ctrl()         __read_32bit_c0_register($22, 2)
1950 #define write_c0_brcm_cmt_ctrl(val)     __write_32bit_c0_register($22, 2, val)
1951
1952 #define read_c0_brcm_cmt_local()        __read_32bit_c0_register($22, 3)
1953 #define write_c0_brcm_cmt_local(val)    __write_32bit_c0_register($22, 3, val)
1954
1955 #define read_c0_brcm_config_1()         __read_32bit_c0_register($22, 5)
1956 #define write_c0_brcm_config_1(val)     __write_32bit_c0_register($22, 5, val)
1957
1958 #define read_c0_brcm_cbr()              __read_32bit_c0_register($22, 6)
1959 #define write_c0_brcm_cbr(val)          __write_32bit_c0_register($22, 6, val)
1960
1961 /* BMIPS5000 */
1962 #define read_c0_brcm_config()           __read_32bit_c0_register($22, 0)
1963 #define write_c0_brcm_config(val)       __write_32bit_c0_register($22, 0, val)
1964
1965 #define read_c0_brcm_mode()             __read_32bit_c0_register($22, 1)
1966 #define write_c0_brcm_mode(val)         __write_32bit_c0_register($22, 1, val)
1967
1968 #define read_c0_brcm_action()           __read_32bit_c0_register($22, 2)
1969 #define write_c0_brcm_action(val)       __write_32bit_c0_register($22, 2, val)
1970
1971 #define read_c0_brcm_edsp()             __read_32bit_c0_register($22, 3)
1972 #define write_c0_brcm_edsp(val)         __write_32bit_c0_register($22, 3, val)
1973
1974 #define read_c0_brcm_bootvec()          __read_32bit_c0_register($22, 4)
1975 #define write_c0_brcm_bootvec(val)      __write_32bit_c0_register($22, 4, val)
1976
1977 #define read_c0_brcm_sleepcount()       __read_32bit_c0_register($22, 7)
1978 #define write_c0_brcm_sleepcount(val)   __write_32bit_c0_register($22, 7, val)
1979
1980 /* Ingenic page ctrl register */
1981 #define write_c0_page_ctrl(val) __write_32bit_c0_register($5, 4, val)
1982
1983 /*
1984  * Macros to access the guest system control coprocessor
1985  */
1986
1987 #ifndef TOOLCHAIN_SUPPORTS_VIRT
1988 _ASM_MACRO_2R_1S(mfgc0, rt, rs, sel,
1989         _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel)
1990         _ASM_INSN32_IF_MM(0x000004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1991 _ASM_MACRO_2R_1S(dmfgc0, rt, rs, sel,
1992         _ASM_INSN_IF_MIPS(0x40600100 | __rt << 16 | __rs << 11 | \\sel)
1993         _ASM_INSN32_IF_MM(0x580004fc | __rt << 21 | __rs << 16 | \\sel << 11));
1994 _ASM_MACRO_2R_1S(mtgc0, rt, rd, sel,
1995         _ASM_INSN_IF_MIPS(0x40600200 | __rt << 16 | __rd << 11 | \\sel)
1996         _ASM_INSN32_IF_MM(0x000006fc | __rt << 21 | __rd << 16 | \\sel << 11));
1997 _ASM_MACRO_2R_1S(dmtgc0, rt, rd, sel,
1998         _ASM_INSN_IF_MIPS(0x40600300 | __rt << 16 | __rd << 11 | \\sel)
1999         _ASM_INSN32_IF_MM(0x580006fc | __rt << 21 | __rd << 16 | \\sel << 11));
2000 _ASM_MACRO_0(tlbgp,    _ASM_INSN_IF_MIPS(0x42000010)
2001                        _ASM_INSN32_IF_MM(0x0000017c));
2002 _ASM_MACRO_0(tlbgr,    _ASM_INSN_IF_MIPS(0x42000009)
2003                        _ASM_INSN32_IF_MM(0x0000117c));
2004 _ASM_MACRO_0(tlbgwi,   _ASM_INSN_IF_MIPS(0x4200000a)
2005                        _ASM_INSN32_IF_MM(0x0000217c));
2006 _ASM_MACRO_0(tlbgwr,   _ASM_INSN_IF_MIPS(0x4200000e)
2007                        _ASM_INSN32_IF_MM(0x0000317c));
2008 _ASM_MACRO_0(tlbginvf, _ASM_INSN_IF_MIPS(0x4200000c)
2009                        _ASM_INSN32_IF_MM(0x0000517c));
2010 #define _ASM_SET_VIRT ""
2011 #else   /* !TOOLCHAIN_SUPPORTS_VIRT */
2012 #define _ASM_SET_VIRT ".set\tvirt\n\t"
2013 #endif
2014
2015 #define __read_32bit_gc0_register(source, sel)                          \
2016 ({ int __res;                                                           \
2017         __asm__ __volatile__(                                           \
2018                 ".set\tpush\n\t"                                        \
2019                 ".set\tmips32r2\n\t"                                    \
2020                 _ASM_SET_VIRT                                           \
2021                 "mfgc0\t%0, " #source ", %1\n\t"                        \
2022                 ".set\tpop"                                             \
2023                 : "=r" (__res)                                          \
2024                 : "i" (sel));                                           \
2025         __res;                                                          \
2026 })
2027
2028 #define __read_64bit_gc0_register(source, sel)                          \
2029 ({ unsigned long long __res;                                            \
2030         __asm__ __volatile__(                                           \
2031                 ".set\tpush\n\t"                                        \
2032                 ".set\tmips64r2\n\t"                                    \
2033                 _ASM_SET_VIRT                                           \
2034                 "dmfgc0\t%0, " #source ", %1\n\t"                       \
2035                 ".set\tpop"                                             \
2036                 : "=r" (__res)                                          \
2037                 : "i" (sel));                                           \
2038         __res;                                                          \
2039 })
2040
2041 #define __write_32bit_gc0_register(register, sel, value)                \
2042 do {                                                                    \
2043         __asm__ __volatile__(                                           \
2044                 ".set\tpush\n\t"                                        \
2045                 ".set\tmips32r2\n\t"                                    \
2046                 _ASM_SET_VIRT                                           \
2047                 "mtgc0\t%z0, " #register ", %1\n\t"                     \
2048                 ".set\tpop"                                             \
2049                 : : "Jr" ((unsigned int)(value)),                       \
2050                     "i" (sel));                                         \
2051 } while (0)
2052
2053 #define __write_64bit_gc0_register(register, sel, value)                \
2054 do {                                                                    \
2055         __asm__ __volatile__(                                           \
2056                 ".set\tpush\n\t"                                        \
2057                 ".set\tmips64r2\n\t"                                    \
2058                 _ASM_SET_VIRT                                           \
2059                 "dmtgc0\t%z0, " #register ", %1\n\t"                    \
2060                 ".set\tpop"                                             \
2061                 : : "Jr" (value),                                       \
2062                     "i" (sel));                                         \
2063 } while (0)
2064
2065 #define __read_ulong_gc0_register(reg, sel)                             \
2066         ((sizeof(unsigned long) == 4) ?                                 \
2067         (unsigned long) __read_32bit_gc0_register(reg, sel) :           \
2068         (unsigned long) __read_64bit_gc0_register(reg, sel))
2069
2070 #define __write_ulong_gc0_register(reg, sel, val)                       \
2071 do {                                                                    \
2072         if (sizeof(unsigned long) == 4)                                 \
2073                 __write_32bit_gc0_register(reg, sel, val);              \
2074         else                                                            \
2075                 __write_64bit_gc0_register(reg, sel, val);              \
2076 } while (0)
2077
2078 #define read_gc0_index()                __read_32bit_gc0_register($0, 0)
2079 #define write_gc0_index(val)            __write_32bit_gc0_register($0, 0, val)
2080
2081 #define read_gc0_entrylo0()             __read_ulong_gc0_register($2, 0)
2082 #define write_gc0_entrylo0(val)         __write_ulong_gc0_register($2, 0, val)
2083
2084 #define read_gc0_entrylo1()             __read_ulong_gc0_register($3, 0)
2085 #define write_gc0_entrylo1(val)         __write_ulong_gc0_register($3, 0, val)
2086
2087 #define read_gc0_context()              __read_ulong_gc0_register($4, 0)
2088 #define write_gc0_context(val)          __write_ulong_gc0_register($4, 0, val)
2089
2090 #define read_gc0_contextconfig()        __read_32bit_gc0_register($4, 1)
2091 #define write_gc0_contextconfig(val)    __write_32bit_gc0_register($4, 1, val)
2092
2093 #define read_gc0_userlocal()            __read_ulong_gc0_register($4, 2)
2094 #define write_gc0_userlocal(val)        __write_ulong_gc0_register($4, 2, val)
2095
2096 #define read_gc0_xcontextconfig()       __read_ulong_gc0_register($4, 3)
2097 #define write_gc0_xcontextconfig(val)   __write_ulong_gc0_register($4, 3, val)
2098
2099 #define read_gc0_pagemask()             __read_32bit_gc0_register($5, 0)
2100 #define write_gc0_pagemask(val)         __write_32bit_gc0_register($5, 0, val)
2101
2102 #define read_gc0_pagegrain()            __read_32bit_gc0_register($5, 1)
2103 #define write_gc0_pagegrain(val)        __write_32bit_gc0_register($5, 1, val)
2104
2105 #define read_gc0_segctl0()              __read_ulong_gc0_register($5, 2)
2106 #define write_gc0_segctl0(val)          __write_ulong_gc0_register($5, 2, val)
2107
2108 #define read_gc0_segctl1()              __read_ulong_gc0_register($5, 3)
2109 #define write_gc0_segctl1(val)          __write_ulong_gc0_register($5, 3, val)
2110
2111 #define read_gc0_segctl2()              __read_ulong_gc0_register($5, 4)
2112 #define write_gc0_segctl2(val)          __write_ulong_gc0_register($5, 4, val)
2113
2114 #define read_gc0_pwbase()               __read_ulong_gc0_register($5, 5)
2115 #define write_gc0_pwbase(val)           __write_ulong_gc0_register($5, 5, val)
2116
2117 #define read_gc0_pwfield()              __read_ulong_gc0_register($5, 6)
2118 #define write_gc0_pwfield(val)          __write_ulong_gc0_register($5, 6, val)
2119
2120 #define read_gc0_pwsize()               __read_ulong_gc0_register($5, 7)
2121 #define write_gc0_pwsize(val)           __write_ulong_gc0_register($5, 7, val)
2122
2123 #define read_gc0_wired()                __read_32bit_gc0_register($6, 0)
2124 #define write_gc0_wired(val)            __write_32bit_gc0_register($6, 0, val)
2125
2126 #define read_gc0_pwctl()                __read_32bit_gc0_register($6, 6)
2127 #define write_gc0_pwctl(val)            __write_32bit_gc0_register($6, 6, val)
2128
2129 #define read_gc0_hwrena()               __read_32bit_gc0_register($7, 0)
2130 #define write_gc0_hwrena(val)           __write_32bit_gc0_register($7, 0, val)
2131
2132 #define read_gc0_badvaddr()             __read_ulong_gc0_register($8, 0)
2133 #define write_gc0_badvaddr(val)         __write_ulong_gc0_register($8, 0, val)
2134
2135 #define read_gc0_badinstr()             __read_32bit_gc0_register($8, 1)
2136 #define write_gc0_badinstr(val)         __write_32bit_gc0_register($8, 1, val)
2137
2138 #define read_gc0_badinstrp()            __read_32bit_gc0_register($8, 2)
2139 #define write_gc0_badinstrp(val)        __write_32bit_gc0_register($8, 2, val)
2140
2141 #define read_gc0_count()                __read_32bit_gc0_register($9, 0)
2142
2143 #define read_gc0_entryhi()              __read_ulong_gc0_register($10, 0)
2144 #define write_gc0_entryhi(val)          __write_ulong_gc0_register($10, 0, val)
2145
2146 #define read_gc0_compare()              __read_32bit_gc0_register($11, 0)
2147 #define write_gc0_compare(val)          __write_32bit_gc0_register($11, 0, val)
2148
2149 #define read_gc0_status()               __read_32bit_gc0_register($12, 0)
2150 #define write_gc0_status(val)           __write_32bit_gc0_register($12, 0, val)
2151
2152 #define read_gc0_intctl()               __read_32bit_gc0_register($12, 1)
2153 #define write_gc0_intctl(val)           __write_32bit_gc0_register($12, 1, val)
2154
2155 #define read_gc0_cause()                __read_32bit_gc0_register($13, 0)
2156 #define write_gc0_cause(val)            __write_32bit_gc0_register($13, 0, val)
2157
2158 #define read_gc0_epc()                  __read_ulong_gc0_register($14, 0)
2159 #define write_gc0_epc(val)              __write_ulong_gc0_register($14, 0, val)
2160
2161 #define read_gc0_prid()                 __read_32bit_gc0_register($15, 0)
2162
2163 #define read_gc0_ebase()                __read_32bit_gc0_register($15, 1)
2164 #define write_gc0_ebase(val)            __write_32bit_gc0_register($15, 1, val)
2165
2166 #define read_gc0_ebase_64()             __read_64bit_gc0_register($15, 1)
2167 #define write_gc0_ebase_64(val)         __write_64bit_gc0_register($15, 1, val)
2168
2169 #define read_gc0_config()               __read_32bit_gc0_register($16, 0)
2170 #define read_gc0_config1()              __read_32bit_gc0_register($16, 1)
2171 #define read_gc0_config2()              __read_32bit_gc0_register($16, 2)
2172 #define read_gc0_config3()              __read_32bit_gc0_register($16, 3)
2173 #define read_gc0_config4()              __read_32bit_gc0_register($16, 4)
2174 #define read_gc0_config5()              __read_32bit_gc0_register($16, 5)
2175 #define read_gc0_config6()              __read_32bit_gc0_register($16, 6)
2176 #define read_gc0_config7()              __read_32bit_gc0_register($16, 7)
2177 #define write_gc0_config(val)           __write_32bit_gc0_register($16, 0, val)
2178 #define write_gc0_config1(val)          __write_32bit_gc0_register($16, 1, val)
2179 #define write_gc0_config2(val)          __write_32bit_gc0_register($16, 2, val)
2180 #define write_gc0_config3(val)          __write_32bit_gc0_register($16, 3, val)
2181 #define write_gc0_config4(val)          __write_32bit_gc0_register($16, 4, val)
2182 #define write_gc0_config5(val)          __write_32bit_gc0_register($16, 5, val)
2183 #define write_gc0_config6(val)          __write_32bit_gc0_register($16, 6, val)
2184 #define write_gc0_config7(val)          __write_32bit_gc0_register($16, 7, val)
2185
2186 #define read_gc0_lladdr()               __read_ulong_gc0_register($17, 0)
2187 #define write_gc0_lladdr(val)           __write_ulong_gc0_register($17, 0, val)
2188
2189 #define read_gc0_watchlo0()             __read_ulong_gc0_register($18, 0)
2190 #define read_gc0_watchlo1()             __read_ulong_gc0_register($18, 1)
2191 #define read_gc0_watchlo2()             __read_ulong_gc0_register($18, 2)
2192 #define read_gc0_watchlo3()             __read_ulong_gc0_register($18, 3)
2193 #define read_gc0_watchlo4()             __read_ulong_gc0_register($18, 4)
2194 #define read_gc0_watchlo5()             __read_ulong_gc0_register($18, 5)
2195 #define read_gc0_watchlo6()             __read_ulong_gc0_register($18, 6)
2196 #define read_gc0_watchlo7()             __read_ulong_gc0_register($18, 7)
2197 #define write_gc0_watchlo0(val)         __write_ulong_gc0_register($18, 0, val)
2198 #define write_gc0_watchlo1(val)         __write_ulong_gc0_register($18, 1, val)
2199 #define write_gc0_watchlo2(val)         __write_ulong_gc0_register($18, 2, val)
2200 #define write_gc0_watchlo3(val)         __write_ulong_gc0_register($18, 3, val)
2201 #define write_gc0_watchlo4(val)         __write_ulong_gc0_register($18, 4, val)
2202 #define write_gc0_watchlo5(val)         __write_ulong_gc0_register($18, 5, val)
2203 #define write_gc0_watchlo6(val)         __write_ulong_gc0_register($18, 6, val)
2204 #define write_gc0_watchlo7(val)         __write_ulong_gc0_register($18, 7, val)
2205
2206 #define read_gc0_watchhi0()             __read_32bit_gc0_register($19, 0)
2207 #define read_gc0_watchhi1()             __read_32bit_gc0_register($19, 1)
2208 #define read_gc0_watchhi2()             __read_32bit_gc0_register($19, 2)
2209 #define read_gc0_watchhi3()             __read_32bit_gc0_register($19, 3)
2210 #define read_gc0_watchhi4()             __read_32bit_gc0_register($19, 4)
2211 #define read_gc0_watchhi5()             __read_32bit_gc0_register($19, 5)
2212 #define read_gc0_watchhi6()             __read_32bit_gc0_register($19, 6)
2213 #define read_gc0_watchhi7()             __read_32bit_gc0_register($19, 7)
2214 #define write_gc0_watchhi0(val)         __write_32bit_gc0_register($19, 0, val)
2215 #define write_gc0_watchhi1(val)         __write_32bit_gc0_register($19, 1, val)
2216 #define write_gc0_watchhi2(val)         __write_32bit_gc0_register($19, 2, val)
2217 #define write_gc0_watchhi3(val)         __write_32bit_gc0_register($19, 3, val)
2218 #define write_gc0_watchhi4(val)         __write_32bit_gc0_register($19, 4, val)
2219 #define write_gc0_watchhi5(val)         __write_32bit_gc0_register($19, 5, val)
2220 #define write_gc0_watchhi6(val)         __write_32bit_gc0_register($19, 6, val)
2221 #define write_gc0_watchhi7(val)         __write_32bit_gc0_register($19, 7, val)
2222
2223 #define read_gc0_xcontext()             __read_ulong_gc0_register($20, 0)
2224 #define write_gc0_xcontext(val)         __write_ulong_gc0_register($20, 0, val)
2225
2226 #define read_gc0_perfctrl0()            __read_32bit_gc0_register($25, 0)
2227 #define write_gc0_perfctrl0(val)        __write_32bit_gc0_register($25, 0, val)
2228 #define read_gc0_perfcntr0()            __read_32bit_gc0_register($25, 1)
2229 #define write_gc0_perfcntr0(val)        __write_32bit_gc0_register($25, 1, val)
2230 #define read_gc0_perfcntr0_64()         __read_64bit_gc0_register($25, 1)
2231 #define write_gc0_perfcntr0_64(val)     __write_64bit_gc0_register($25, 1, val)
2232 #define read_gc0_perfctrl1()            __read_32bit_gc0_register($25, 2)
2233 #define write_gc0_perfctrl1(val)        __write_32bit_gc0_register($25, 2, val)
2234 #define read_gc0_perfcntr1()            __read_32bit_gc0_register($25, 3)
2235 #define write_gc0_perfcntr1(val)        __write_32bit_gc0_register($25, 3, val)
2236 #define read_gc0_perfcntr1_64()         __read_64bit_gc0_register($25, 3)
2237 #define write_gc0_perfcntr1_64(val)     __write_64bit_gc0_register($25, 3, val)
2238 #define read_gc0_perfctrl2()            __read_32bit_gc0_register($25, 4)
2239 #define write_gc0_perfctrl2(val)        __write_32bit_gc0_register($25, 4, val)
2240 #define read_gc0_perfcntr2()            __read_32bit_gc0_register($25, 5)
2241 #define write_gc0_perfcntr2(val)        __write_32bit_gc0_register($25, 5, val)
2242 #define read_gc0_perfcntr2_64()         __read_64bit_gc0_register($25, 5)
2243 #define write_gc0_perfcntr2_64(val)     __write_64bit_gc0_register($25, 5, val)
2244 #define read_gc0_perfctrl3()            __read_32bit_gc0_register($25, 6)
2245 #define write_gc0_perfctrl3(val)        __write_32bit_gc0_register($25, 6, val)
2246 #define read_gc0_perfcntr3()            __read_32bit_gc0_register($25, 7)
2247 #define write_gc0_perfcntr3(val)        __write_32bit_gc0_register($25, 7, val)
2248 #define read_gc0_perfcntr3_64()         __read_64bit_gc0_register($25, 7)
2249 #define write_gc0_perfcntr3_64(val)     __write_64bit_gc0_register($25, 7, val)
2250
2251 #define read_gc0_errorepc()             __read_ulong_gc0_register($30, 0)
2252 #define write_gc0_errorepc(val)         __write_ulong_gc0_register($30, 0, val)
2253
2254 #define read_gc0_kscratch1()            __read_ulong_gc0_register($31, 2)
2255 #define read_gc0_kscratch2()            __read_ulong_gc0_register($31, 3)
2256 #define read_gc0_kscratch3()            __read_ulong_gc0_register($31, 4)
2257 #define read_gc0_kscratch4()            __read_ulong_gc0_register($31, 5)
2258 #define read_gc0_kscratch5()            __read_ulong_gc0_register($31, 6)
2259 #define read_gc0_kscratch6()            __read_ulong_gc0_register($31, 7)
2260 #define write_gc0_kscratch1(val)        __write_ulong_gc0_register($31, 2, val)
2261 #define write_gc0_kscratch2(val)        __write_ulong_gc0_register($31, 3, val)
2262 #define write_gc0_kscratch3(val)        __write_ulong_gc0_register($31, 4, val)
2263 #define write_gc0_kscratch4(val)        __write_ulong_gc0_register($31, 5, val)
2264 #define write_gc0_kscratch5(val)        __write_ulong_gc0_register($31, 6, val)
2265 #define write_gc0_kscratch6(val)        __write_ulong_gc0_register($31, 7, val)
2266
2267 /* Cavium OCTEON (cnMIPS) */
2268 #define read_gc0_cvmcount()             __read_ulong_gc0_register($9, 6)
2269 #define write_gc0_cvmcount(val)         __write_ulong_gc0_register($9, 6, val)
2270
2271 #define read_gc0_cvmctl()               __read_64bit_gc0_register($9, 7)
2272 #define write_gc0_cvmctl(val)           __write_64bit_gc0_register($9, 7, val)
2273
2274 #define read_gc0_cvmmemctl()            __read_64bit_gc0_register($11, 7)
2275 #define write_gc0_cvmmemctl(val)        __write_64bit_gc0_register($11, 7, val)
2276
2277 #define read_gc0_cvmmemctl2()           __read_64bit_gc0_register($16, 6)
2278 #define write_gc0_cvmmemctl2(val)       __write_64bit_gc0_register($16, 6, val)
2279
2280 /*
2281  * Macros to access the floating point coprocessor control registers
2282  */
2283 #define _read_32bit_cp1_register(source, gas_hardfloat)                 \
2284 ({                                                                      \
2285         unsigned int __res;                                             \
2286                                                                         \
2287         __asm__ __volatile__(                                           \
2288         "       .set    push                                    \n"     \
2289         "       .set    reorder                                 \n"     \
2290         "       # gas fails to assemble cfc1 for some archs,    \n"     \
2291         "       # like Octeon.                                  \n"     \
2292         "       .set    mips1                                   \n"     \
2293         "       "STR(gas_hardfloat)"                            \n"     \
2294         "       cfc1    %0,"STR(source)"                        \n"     \
2295         "       .set    pop                                     \n"     \
2296         : "=r" (__res));                                                \
2297         __res;                                                          \
2298 })
2299
2300 #define _write_32bit_cp1_register(dest, val, gas_hardfloat)             \
2301 do {                                                                    \
2302         __asm__ __volatile__(                                           \
2303         "       .set    push                                    \n"     \
2304         "       .set    reorder                                 \n"     \
2305         "       "STR(gas_hardfloat)"                            \n"     \
2306         "       ctc1    %0,"STR(dest)"                          \n"     \
2307         "       .set    pop                                     \n"     \
2308         : : "r" (val));                                                 \
2309 } while (0)
2310
2311 #ifdef GAS_HAS_SET_HARDFLOAT
2312 #define read_32bit_cp1_register(source)                                 \
2313         _read_32bit_cp1_register(source, .set hardfloat)
2314 #define write_32bit_cp1_register(dest, val)                             \
2315         _write_32bit_cp1_register(dest, val, .set hardfloat)
2316 #else
2317 #define read_32bit_cp1_register(source)                                 \
2318         _read_32bit_cp1_register(source, )
2319 #define write_32bit_cp1_register(dest, val)                             \
2320         _write_32bit_cp1_register(dest, val, )
2321 #endif
2322
2323 #ifdef TOOLCHAIN_SUPPORTS_DSP
2324 #define rddsp(mask)                                                     \
2325 ({                                                                      \
2326         unsigned int __dspctl;                                          \
2327                                                                         \
2328         __asm__ __volatile__(                                           \
2329         "       .set push                                       \n"     \
2330         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2331         "       .set dsp                                        \n"     \
2332         "       rddsp   %0, %x1                                 \n"     \
2333         "       .set pop                                        \n"     \
2334         : "=r" (__dspctl)                                               \
2335         : "i" (mask));                                                  \
2336         __dspctl;                                                       \
2337 })
2338
2339 #define wrdsp(val, mask)                                                \
2340 do {                                                                    \
2341         __asm__ __volatile__(                                           \
2342         "       .set push                                       \n"     \
2343         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2344         "       .set dsp                                        \n"     \
2345         "       wrdsp   %0, %x1                                 \n"     \
2346         "       .set pop                                        \n"     \
2347         :                                                               \
2348         : "r" (val), "i" (mask));                                       \
2349 } while (0)
2350
2351 #define mflo0()                                                         \
2352 ({                                                                      \
2353         long mflo0;                                                     \
2354         __asm__(                                                        \
2355         "       .set push                                       \n"     \
2356         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2357         "       .set dsp                                        \n"     \
2358         "       mflo %0, $ac0                                   \n"     \
2359         "       .set pop                                        \n"     \
2360         : "=r" (mflo0));                                                \
2361         mflo0;                                                          \
2362 })
2363
2364 #define mflo1()                                                         \
2365 ({                                                                      \
2366         long mflo1;                                                     \
2367         __asm__(                                                        \
2368         "       .set push                                       \n"     \
2369         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2370         "       .set dsp                                        \n"     \
2371         "       mflo %0, $ac1                                   \n"     \
2372         "       .set pop                                        \n"     \
2373         : "=r" (mflo1));                                                \
2374         mflo1;                                                          \
2375 })
2376
2377 #define mflo2()                                                         \
2378 ({                                                                      \
2379         long mflo2;                                                     \
2380         __asm__(                                                        \
2381         "       .set push                                       \n"     \
2382         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2383         "       .set dsp                                        \n"     \
2384         "       mflo %0, $ac2                                   \n"     \
2385         "       .set pop                                        \n"     \
2386         : "=r" (mflo2));                                                \
2387         mflo2;                                                          \
2388 })
2389
2390 #define mflo3()                                                         \
2391 ({                                                                      \
2392         long mflo3;                                                     \
2393         __asm__(                                                        \
2394         "       .set push                                       \n"     \
2395         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2396         "       .set dsp                                        \n"     \
2397         "       mflo %0, $ac3                                   \n"     \
2398         "       .set pop                                        \n"     \
2399         : "=r" (mflo3));                                                \
2400         mflo3;                                                          \
2401 })
2402
2403 #define mfhi0()                                                         \
2404 ({                                                                      \
2405         long mfhi0;                                                     \
2406         __asm__(                                                        \
2407         "       .set push                                       \n"     \
2408         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2409         "       .set dsp                                        \n"     \
2410         "       mfhi %0, $ac0                                   \n"     \
2411         "       .set pop                                        \n"     \
2412         : "=r" (mfhi0));                                                \
2413         mfhi0;                                                          \
2414 })
2415
2416 #define mfhi1()                                                         \
2417 ({                                                                      \
2418         long mfhi1;                                                     \
2419         __asm__(                                                        \
2420         "       .set push                                       \n"     \
2421         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2422         "       .set dsp                                        \n"     \
2423         "       mfhi %0, $ac1                                   \n"     \
2424         "       .set pop                                        \n"     \
2425         : "=r" (mfhi1));                                                \
2426         mfhi1;                                                          \
2427 })
2428
2429 #define mfhi2()                                                         \
2430 ({                                                                      \
2431         long mfhi2;                                                     \
2432         __asm__(                                                        \
2433         "       .set push                                       \n"     \
2434         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2435         "       .set dsp                                        \n"     \
2436         "       mfhi %0, $ac2                                   \n"     \
2437         "       .set pop                                        \n"     \
2438         : "=r" (mfhi2));                                                \
2439         mfhi2;                                                          \
2440 })
2441
2442 #define mfhi3()                                                         \
2443 ({                                                                      \
2444         long mfhi3;                                                     \
2445         __asm__(                                                        \
2446         "       .set push                                       \n"     \
2447         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2448         "       .set dsp                                        \n"     \
2449         "       mfhi %0, $ac3                                   \n"     \
2450         "       .set pop                                        \n"     \
2451         : "=r" (mfhi3));                                                \
2452         mfhi3;                                                          \
2453 })
2454
2455
2456 #define mtlo0(x)                                                        \
2457 ({                                                                      \
2458         __asm__(                                                        \
2459         "       .set push                                       \n"     \
2460         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2461         "       .set dsp                                        \n"     \
2462         "       mtlo %0, $ac0                                   \n"     \
2463         "       .set pop                                        \n"     \
2464         :                                                               \
2465         : "r" (x));                                                     \
2466 })
2467
2468 #define mtlo1(x)                                                        \
2469 ({                                                                      \
2470         __asm__(                                                        \
2471         "       .set push                                       \n"     \
2472         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2473         "       .set dsp                                        \n"     \
2474         "       mtlo %0, $ac1                                   \n"     \
2475         "       .set pop                                        \n"     \
2476         :                                                               \
2477         : "r" (x));                                                     \
2478 })
2479
2480 #define mtlo2(x)                                                        \
2481 ({                                                                      \
2482         __asm__(                                                        \
2483         "       .set push                                       \n"     \
2484         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2485         "       .set dsp                                        \n"     \
2486         "       mtlo %0, $ac2                                   \n"     \
2487         "       .set pop                                        \n"     \
2488         :                                                               \
2489         : "r" (x));                                                     \
2490 })
2491
2492 #define mtlo3(x)                                                        \
2493 ({                                                                      \
2494         __asm__(                                                        \
2495         "       .set push                                       \n"     \
2496         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2497         "       .set dsp                                        \n"     \
2498         "       mtlo %0, $ac3                                   \n"     \
2499         "       .set pop                                        \n"     \
2500         :                                                               \
2501         : "r" (x));                                                     \
2502 })
2503
2504 #define mthi0(x)                                                        \
2505 ({                                                                      \
2506         __asm__(                                                        \
2507         "       .set push                                       \n"     \
2508         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2509         "       .set dsp                                        \n"     \
2510         "       mthi %0, $ac0                                   \n"     \
2511         "       .set pop                                        \n"     \
2512         :                                                               \
2513         : "r" (x));                                                     \
2514 })
2515
2516 #define mthi1(x)                                                        \
2517 ({                                                                      \
2518         __asm__(                                                        \
2519         "       .set push                                       \n"     \
2520         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2521         "       .set dsp                                        \n"     \
2522         "       mthi %0, $ac1                                   \n"     \
2523         "       .set pop                                        \n"     \
2524         :                                                               \
2525         : "r" (x));                                                     \
2526 })
2527
2528 #define mthi2(x)                                                        \
2529 ({                                                                      \
2530         __asm__(                                                        \
2531         "       .set push                                       \n"     \
2532         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2533         "       .set dsp                                        \n"     \
2534         "       mthi %0, $ac2                                   \n"     \
2535         "       .set pop                                        \n"     \
2536         :                                                               \
2537         : "r" (x));                                                     \
2538 })
2539
2540 #define mthi3(x)                                                        \
2541 ({                                                                      \
2542         __asm__(                                                        \
2543         "       .set push                                       \n"     \
2544         "       .set " MIPS_ISA_LEVEL "                         \n"     \
2545         "       .set dsp                                        \n"     \
2546         "       mthi %0, $ac3                                   \n"     \
2547         "       .set pop                                        \n"     \
2548         :                                                               \
2549         : "r" (x));                                                     \
2550 })
2551
2552 #else
2553
2554 #define rddsp(mask)                                                     \
2555 ({                                                                      \
2556         unsigned int __res;                                             \
2557                                                                         \
2558         __asm__ __volatile__(                                           \
2559         "       .set    push                                    \n"     \
2560         "       .set    noat                                    \n"     \
2561         "       # rddsp $1, %x1                                 \n"     \
2562         _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16))                     \
2563         _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14))                     \
2564         "       move    %0, $1                                  \n"     \
2565         "       .set    pop                                     \n"     \
2566         : "=r" (__res)                                                  \
2567         : "i" (mask));                                                  \
2568         __res;                                                          \
2569 })
2570
2571 #define wrdsp(val, mask)                                                \
2572 do {                                                                    \
2573         __asm__ __volatile__(                                           \
2574         "       .set    push                                    \n"     \
2575         "       .set    noat                                    \n"     \
2576         "       move    $1, %0                                  \n"     \
2577         "       # wrdsp $1, %x1                                 \n"     \
2578         _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11))                     \
2579         _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14))                     \
2580         "       .set    pop                                     \n"     \
2581         :                                                               \
2582         : "r" (val), "i" (mask));                                       \
2583 } while (0)
2584
2585 #define _dsp_mfxxx(ins)                                                 \
2586 ({                                                                      \
2587         unsigned long __treg;                                           \
2588                                                                         \
2589         __asm__ __volatile__(                                           \
2590         "       .set    push                                    \n"     \
2591         "       .set    noat                                    \n"     \
2592         _ASM_INSN_IF_MIPS(0x00000810 | %X1)                             \
2593         _ASM_INSN32_IF_MM(0x0001007c | %x1)                             \
2594         "       move    %0, $1                                  \n"     \
2595         "       .set    pop                                     \n"     \
2596         : "=r" (__treg)                                                 \
2597         : "i" (ins));                                                   \
2598         __treg;                                                         \
2599 })
2600
2601 #define _dsp_mtxxx(val, ins)                                            \
2602 do {                                                                    \
2603         __asm__ __volatile__(                                           \
2604         "       .set    push                                    \n"     \
2605         "       .set    noat                                    \n"     \
2606         "       move    $1, %0                                  \n"     \
2607         _ASM_INSN_IF_MIPS(0x00200011 | %X1)                             \
2608         _ASM_INSN32_IF_MM(0x0001207c | %x1)                             \
2609         "       .set    pop                                     \n"     \
2610         :                                                               \
2611         : "r" (val), "i" (ins));                                        \
2612 } while (0)
2613
2614 #ifdef CONFIG_CPU_MICROMIPS
2615
2616 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2617 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2618
2619 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2620 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2621
2622 #else  /* !CONFIG_CPU_MICROMIPS */
2623
2624 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2625 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2626
2627 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2628 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2629
2630 #endif /* CONFIG_CPU_MICROMIPS */
2631
2632 #define mflo0() _dsp_mflo(0)
2633 #define mflo1() _dsp_mflo(1)
2634 #define mflo2() _dsp_mflo(2)
2635 #define mflo3() _dsp_mflo(3)
2636
2637 #define mfhi0() _dsp_mfhi(0)
2638 #define mfhi1() _dsp_mfhi(1)
2639 #define mfhi2() _dsp_mfhi(2)
2640 #define mfhi3() _dsp_mfhi(3)
2641
2642 #define mtlo0(x) _dsp_mtlo(x, 0)
2643 #define mtlo1(x) _dsp_mtlo(x, 1)
2644 #define mtlo2(x) _dsp_mtlo(x, 2)
2645 #define mtlo3(x) _dsp_mtlo(x, 3)
2646
2647 #define mthi0(x) _dsp_mthi(x, 0)
2648 #define mthi1(x) _dsp_mthi(x, 1)
2649 #define mthi2(x) _dsp_mthi(x, 2)
2650 #define mthi3(x) _dsp_mthi(x, 3)
2651
2652 #endif
2653
2654 /*
2655  * TLB operations.
2656  *
2657  * It is responsibility of the caller to take care of any TLB hazards.
2658  */
2659 static inline void tlb_probe(void)
2660 {
2661         __asm__ __volatile__(
2662                 ".set noreorder\n\t"
2663                 "tlbp\n\t"
2664                 ".set reorder");
2665 }
2666
2667 static inline void tlb_read(void)
2668 {
2669 #if MIPS34K_MISSED_ITLB_WAR
2670         int res = 0;
2671
2672         __asm__ __volatile__(
2673         "       .set    push                                    \n"
2674         "       .set    noreorder                               \n"
2675         "       .set    noat                                    \n"
2676         "       .set    mips32r2                                \n"
2677         "       .word   0x41610001              # dvpe $1       \n"
2678         "       move    %0, $1                                  \n"
2679         "       ehb                                             \n"
2680         "       .set    pop                                     \n"
2681         : "=r" (res));
2682
2683         instruction_hazard();
2684 #endif
2685
2686         __asm__ __volatile__(
2687                 ".set noreorder\n\t"
2688                 "tlbr\n\t"
2689                 ".set reorder");
2690
2691 #if MIPS34K_MISSED_ITLB_WAR
2692         if ((res & _ULCAST_(1)))
2693                 __asm__ __volatile__(
2694                 "       .set    push                            \n"
2695                 "       .set    noreorder                       \n"
2696                 "       .set    noat                            \n"
2697                 "       .set    mips32r2                        \n"
2698                 "       .word   0x41600021      # evpe          \n"
2699                 "       ehb                                     \n"
2700                 "       .set    pop                             \n");
2701 #endif
2702 }
2703
2704 static inline void tlb_write_indexed(void)
2705 {
2706         __asm__ __volatile__(
2707                 ".set noreorder\n\t"
2708                 "tlbwi\n\t"
2709                 ".set reorder");
2710 }
2711
2712 static inline void tlb_write_random(void)
2713 {
2714         __asm__ __volatile__(
2715                 ".set noreorder\n\t"
2716                 "tlbwr\n\t"
2717                 ".set reorder");
2718 }
2719
2720 /*
2721  * Guest TLB operations.
2722  *
2723  * It is responsibility of the caller to take care of any TLB hazards.
2724  */
2725 static inline void guest_tlb_probe(void)
2726 {
2727         __asm__ __volatile__(
2728                 ".set push\n\t"
2729                 ".set noreorder\n\t"
2730                 _ASM_SET_VIRT
2731                 "tlbgp\n\t"
2732                 ".set pop");
2733 }
2734
2735 static inline void guest_tlb_read(void)
2736 {
2737         __asm__ __volatile__(
2738                 ".set push\n\t"
2739                 ".set noreorder\n\t"
2740                 _ASM_SET_VIRT
2741                 "tlbgr\n\t"
2742                 ".set pop");
2743 }
2744
2745 static inline void guest_tlb_write_indexed(void)
2746 {
2747         __asm__ __volatile__(
2748                 ".set push\n\t"
2749                 ".set noreorder\n\t"
2750                 _ASM_SET_VIRT
2751                 "tlbgwi\n\t"
2752                 ".set pop");
2753 }
2754
2755 static inline void guest_tlb_write_random(void)
2756 {
2757         __asm__ __volatile__(
2758                 ".set push\n\t"
2759                 ".set noreorder\n\t"
2760                 _ASM_SET_VIRT
2761                 "tlbgwr\n\t"
2762                 ".set pop");
2763 }
2764
2765 /*
2766  * Guest TLB Invalidate Flush
2767  */
2768 static inline void guest_tlbinvf(void)
2769 {
2770         __asm__ __volatile__(
2771                 ".set push\n\t"
2772                 ".set noreorder\n\t"
2773                 _ASM_SET_VIRT
2774                 "tlbginvf\n\t"
2775                 ".set pop");
2776 }
2777
2778 /*
2779  * Manipulate bits in a register.
2780  */
2781 #define __BUILD_SET_COMMON(name)                                \
2782 static inline unsigned int                                      \
2783 set_##name(unsigned int set)                                    \
2784 {                                                               \
2785         unsigned int res, new;                                  \
2786                                                                 \
2787         res = read_##name();                                    \
2788         new = res | set;                                        \
2789         write_##name(new);                                      \
2790                                                                 \
2791         return res;                                             \
2792 }                                                               \
2793                                                                 \
2794 static inline unsigned int                                      \
2795 clear_##name(unsigned int clear)                                \
2796 {                                                               \
2797         unsigned int res, new;                                  \
2798                                                                 \
2799         res = read_##name();                                    \
2800         new = res & ~clear;                                     \
2801         write_##name(new);                                      \
2802                                                                 \
2803         return res;                                             \
2804 }                                                               \
2805                                                                 \
2806 static inline unsigned int                                      \
2807 change_##name(unsigned int change, unsigned int val)            \
2808 {                                                               \
2809         unsigned int res, new;                                  \
2810                                                                 \
2811         res = read_##name();                                    \
2812         new = res & ~change;                                    \
2813         new |= (val & change);                                  \
2814         write_##name(new);                                      \
2815                                                                 \
2816         return res;                                             \
2817 }
2818
2819 /*
2820  * Manipulate bits in a c0 register.
2821  */
2822 #define __BUILD_SET_C0(name)    __BUILD_SET_COMMON(c0_##name)
2823
2824 __BUILD_SET_C0(status)
2825 __BUILD_SET_C0(cause)
2826 __BUILD_SET_C0(config)
2827 __BUILD_SET_C0(config5)
2828 __BUILD_SET_C0(config7)
2829 __BUILD_SET_C0(intcontrol)
2830 __BUILD_SET_C0(intctl)
2831 __BUILD_SET_C0(srsmap)
2832 __BUILD_SET_C0(pagegrain)
2833 __BUILD_SET_C0(guestctl0)
2834 __BUILD_SET_C0(guestctl0ext)
2835 __BUILD_SET_C0(guestctl1)
2836 __BUILD_SET_C0(guestctl2)
2837 __BUILD_SET_C0(guestctl3)
2838 __BUILD_SET_C0(brcm_config_0)
2839 __BUILD_SET_C0(brcm_bus_pll)
2840 __BUILD_SET_C0(brcm_reset)
2841 __BUILD_SET_C0(brcm_cmt_intr)
2842 __BUILD_SET_C0(brcm_cmt_ctrl)
2843 __BUILD_SET_C0(brcm_config)
2844 __BUILD_SET_C0(brcm_mode)
2845
2846 /*
2847  * Manipulate bits in a guest c0 register.
2848  */
2849 #define __BUILD_SET_GC0(name)   __BUILD_SET_COMMON(gc0_##name)
2850
2851 __BUILD_SET_GC0(wired)
2852 __BUILD_SET_GC0(status)
2853 __BUILD_SET_GC0(cause)
2854 __BUILD_SET_GC0(ebase)
2855 __BUILD_SET_GC0(config1)
2856
2857 /*
2858  * Return low 10 bits of ebase.
2859  * Note that under KVM (MIPSVZ) this returns vcpu id.
2860  */
2861 static inline unsigned int get_ebase_cpunum(void)
2862 {
2863         return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2864 }
2865
2866 #endif /* !__ASSEMBLY__ */
2867
2868 #endif /* _ASM_MIPSREGS_H */