arch/mips/include/asm/mach-ralink/mt7620/cpu-feature-overrides.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Ralink MT7620 specific CPU feature overrides
   4  *
   5  * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   6  * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  * This file was derived from: include/asm-mips/cpu-features.h
   9  *      Copyright (C) 2003, 2004 Ralf Baechle
  10  *      Copyright (C) 2004 Maciej W. Rozycki
  11  */
  12 #ifndef _MT7620_CPU_FEATURE_OVERRIDES_H
  13 #define _MT7620_CPU_FEATURE_OVERRIDES_H
  14
  15 #define cpu_has_tlb             1
  16 #define cpu_has_4kex            1
  17 #define cpu_has_3k_cache        0
  18 #define cpu_has_4k_cache        1
  19 #define cpu_has_tx39_cache      0
  20 #define cpu_has_sb1_cache       0
  21 #define cpu_has_fpu             0
  22 #define cpu_has_32fpr           0
  23 #define cpu_has_counter         1
  24 #define cpu_has_watch           1
  25 #define cpu_has_divec           1
  26
  27 #define cpu_has_prefetch        1
  28 #define cpu_has_ejtag           1
  29 #define cpu_has_llsc            1
  30
  31 #define cpu_has_mips16          1
  32 #define cpu_has_mdmx            0
  33 #define cpu_has_mips3d          0
  34 #define cpu_has_smartmips       0
  35
  36 #define cpu_has_mips32r1        1
  37 #define cpu_has_mips32r2        1
  38 #define cpu_has_mips64r1        0
  39 #define cpu_has_mips64r2        0
  40
  41 #define cpu_has_dsp             1
  42 #define cpu_has_dsp2            0
  43 #define cpu_has_mipsmt          0
  44
  45 #define cpu_has_64bits          0
  46 #define cpu_has_64bit_zero_reg  0
  47 #define cpu_has_64bit_gp_regs   0
  48 #define cpu_has_64bit_addresses 0
  49
  50 #define cpu_dcache_line_size()  32
  51 #define cpu_icache_line_size()  32
  52
  53 #endif /* _MT7620_CPU_FEATURE_OVERRIDES_H */