2 * m54xxsim.h -- ColdFire 547x/548x System Integration Unit support.
8 #define CPU_NAME "COLDFIRE(m54xx)"
9 #define CPU_INSTR_PER_JIFFY 2
10 #define MCF_BUSCLK (MCF_CLK / 2)
11 #define MACHINE MACH_M54XX
12 #define FPUTYPE FPU_COLDFIRE
13 #define IOMEMBASE MCF_MBAR
14 #define IOMEMSIZE 0x01000000
16 #include <asm/m54xxacr.h>
18 #define MCFINT_VECBASE 64
21 * Interrupt Controller Registers
23 #define MCFICM_INTC0 (MCF_MBAR + 0x700) /* Base for Interrupt Ctrl 0 */
25 #define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
26 #define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
27 #define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
28 #define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
29 #define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
30 #define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
31 #define MCFINTC_IRLR 0x18 /* */
32 #define MCFINTC_IACKL 0x19 /* */
33 #define MCFINTC_ICR0 0x40 /* Base ICR register */
38 #define MCFUART_BASE0 (MCF_MBAR + 0x8600) /* Base address UART0 */
39 #define MCFUART_BASE1 (MCF_MBAR + 0x8700) /* Base address UART1 */
40 #define MCFUART_BASE2 (MCF_MBAR + 0x8800) /* Base address UART2 */
41 #define MCFUART_BASE3 (MCF_MBAR + 0x8900) /* Base address UART3 */
44 * Define system peripheral IRQ usage.
46 #define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */
47 #define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */
48 #define MCF_IRQ_I2C0 (MCFINT_VECBASE + 40)
49 #define MCF_IRQ_UART0 (MCFINT_VECBASE + 35)
50 #define MCF_IRQ_UART1 (MCFINT_VECBASE + 34)
51 #define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
52 #define MCF_IRQ_UART3 (MCFINT_VECBASE + 32)
55 * Slice Timer support.
57 #define MCFSLT_TIMER0 (MCF_MBAR + 0x900) /* Base addr TIMER0 */
58 #define MCFSLT_TIMER1 (MCF_MBAR + 0x910) /* Base addr TIMER1 */
61 * Generic GPIO support
63 #define MCFGPIO_PODR (MCF_MBAR + 0xA00)
64 #define MCFGPIO_PDDR (MCF_MBAR + 0xA10)
65 #define MCFGPIO_PPDR (MCF_MBAR + 0xA20)
66 #define MCFGPIO_SETR (MCF_MBAR + 0xA20)
67 #define MCFGPIO_CLRR (MCF_MBAR + 0xA30)
69 #define MCFGPIO_PIN_MAX 136 /* 128 gpio + 8 eport */
70 #define MCFGPIO_IRQ_MAX 8
71 #define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
76 #define MCFEPORT_EPPAR (MCF_MBAR + 0xf00) /* Pin assignment */
77 #define MCFEPORT_EPDDR (MCF_MBAR + 0xf04) /* Data direction */
78 #define MCFEPORT_EPIER (MCF_MBAR + 0xf05) /* Interrupt enable */
79 #define MCFEPORT_EPDR (MCF_MBAR + 0xf08) /* Port data (w) */
80 #define MCFEPORT_EPPDR (MCF_MBAR + 0xf09) /* Port data (r) */
81 #define MCFEPORT_EPFR (MCF_MBAR + 0xf0c) /* Flags */
84 * Pin Assignment register definitions
86 #define MCFGPIO_PAR_FBCTL (MCF_MBAR + 0xA40)
87 #define MCFGPIO_PAR_FBCS (MCF_MBAR + 0xA42)
88 #define MCFGPIO_PAR_DMA (MCF_MBAR + 0xA43)
89 #define MCFGPIO_PAR_FECI2CIRQ (MCF_MBAR + 0xA44)
90 #define MCFGPIO_PAR_PCIBG (MCF_MBAR + 0xA48) /* PCI bus grant */
91 #define MCFGPIO_PAR_PCIBR (MCF_MBAR + 0xA4A) /* PCI */
92 #define MCFGPIO_PAR_PSC0 (MCF_MBAR + 0xA4F)
93 #define MCFGPIO_PAR_PSC1 (MCF_MBAR + 0xA4E)
94 #define MCFGPIO_PAR_PSC2 (MCF_MBAR + 0xA4D)
95 #define MCFGPIO_PAR_PSC3 (MCF_MBAR + 0xA4C)
96 #define MCFGPIO_PAR_DSPI (MCF_MBAR + 0xA50)
97 #define MCFGPIO_PAR_TIMER (MCF_MBAR + 0xA52)
99 #define MCF_PAR_SDA (0x0008)
100 #define MCF_PAR_SCL (0x0004)
101 #define MCF_PAR_PSC_TXD (0x04)
102 #define MCF_PAR_PSC_RXD (0x08)
103 #define MCF_PAR_PSC_CTS_GPIO (0x00)
104 #define MCF_PAR_PSC_CTS_BCLK (0x80)
105 #define MCF_PAR_PSC_CTS_CTS (0xC0)
106 #define MCF_PAR_PSC_RTS_GPIO (0x00)
107 #define MCF_PAR_PSC_RTS_FSYNC (0x20)
108 #define MCF_PAR_PSC_RTS_RTS (0x30)
109 #define MCF_PAR_PSC_CANRX (0x40)
111 #define MCF_PAR_FECI2CIRQ (MCF_MBAR + 0x00000a44) /* FEC/I2C/IRQ */
112 #define MCF_PAR_FECI2CIRQ_SDA (1 << 3)
113 #define MCF_PAR_FECI2CIRQ_SCL (1 << 2)
118 #define MCFI2C_BASE0 (MCF_MBAR + 0x8f00)
119 #define MCFI2C_SIZE0 0x40
121 #endif /* m54xxsim_h */