arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier PXs3 SoC
   4 //
   5 // Copyright (C) 2017 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/gpio/uniphier-gpio.h>
  10
  11 / {
  12         compatible = "socionext,uniphier-pxs3";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15         interrupt-parent = <&gic>;
  16
  17         cpus {
  18                 #address-cells = <2>;
  19                 #size-cells = <0>;
  20
  21                 cpu-map {
  22                         cluster0 {
  23                                 core0 {
  24                                         cpu = <&cpu0>;
  25                                 };
  26                                 core1 {
  27                                         cpu = <&cpu1>;
  28                                 };
  29                                 core2 {
  30                                         cpu = <&cpu2>;
  31                                 };
  32                                 core3 {
  33                                         cpu = <&cpu3>;
  34                                 };
  35                         };
  36                 };
  37
  38                 cpu0: cpu@0 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a53";
  41                         reg = <0 0x000>;
  42                         clocks = <&sys_clk 33>;
  43                         enable-method = "psci";
  44                         operating-points-v2 = <&cluster0_opp>;
  45                 };
  46
  47                 cpu1: cpu@1 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a53";
  50                         reg = <0 0x001>;
  51                         clocks = <&sys_clk 33>;
  52                         enable-method = "psci";
  53                         operating-points-v2 = <&cluster0_opp>;
  54                 };
  55
  56                 cpu2: cpu@2 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a53";
  59                         reg = <0 0x002>;
  60                         clocks = <&sys_clk 33>;
  61                         enable-method = "psci";
  62                         operating-points-v2 = <&cluster0_opp>;
  63                 };
  64
  65                 cpu3: cpu@3 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a53";
  68                         reg = <0 0x003>;
  69                         clocks = <&sys_clk 33>;
  70                         enable-method = "psci";
  71                         operating-points-v2 = <&cluster0_opp>;
  72                 };
  73         };
  74
  75         cluster0_opp: opp-table {
  76                 compatible = "operating-points-v2";
  77                 opp-shared;
  78
  79                 opp-250000000 {
  80                         opp-hz = /bits/ 64 <250000000>;
  81                         clock-latency-ns = <300>;
  82                 };
  83                 opp-325000000 {
  84                         opp-hz = /bits/ 64 <325000000>;
  85                         clock-latency-ns = <300>;
  86                 };
  87                 opp-500000000 {
  88                         opp-hz = /bits/ 64 <500000000>;
  89                         clock-latency-ns = <300>;
  90                 };
  91                 opp-650000000 {
  92                         opp-hz = /bits/ 64 <650000000>;
  93                         clock-latency-ns = <300>;
  94                 };
  95                 opp-666667000 {
  96                         opp-hz = /bits/ 64 <666667000>;
  97                         clock-latency-ns = <300>;
  98                 };
  99                 opp-866667000 {
 100                         opp-hz = /bits/ 64 <866667000>;
 101                         clock-latency-ns = <300>;
 102                 };
 103                 opp-1000000000 {
 104                         opp-hz = /bits/ 64 <1000000000>;
 105                         clock-latency-ns = <300>;
 106                 };
 107                 opp-1300000000 {
 108                         opp-hz = /bits/ 64 <1300000000>;
 109                         clock-latency-ns = <300>;
 110                 };
 111         };
 112
 113         psci {
 114                 compatible = "arm,psci-1.0";
 115                 method = "smc";
 116         };
 117
 118         clocks {
 119                 refclk: ref {
 120                         compatible = "fixed-clock";
 121                         #clock-cells = <0>;
 122                         clock-frequency = <25000000>;
 123                 };
 124         };
 125
 126         emmc_pwrseq: emmc-pwrseq {
 127                 compatible = "mmc-pwrseq-emmc";
 128                 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>;
 129         };
 130
 131         timer {
 132                 compatible = "arm,armv8-timer";
 133                 interrupts = <1 13 4>,
 134                              <1 14 4>,
 135                              <1 11 4>,
 136                              <1 10 4>;
 137         };
 138
 139         reserved-memory {
 140                 #address-cells = <2>;
 141                 #size-cells = <2>;
 142                 ranges;
 143
 144                 secure-memory@81000000 {
 145                         reg = <0x0 0x81000000 0x0 0x01000000>;
 146                         no-map;
 147                 };
 148         };
 149
 150         soc@0 {
 151                 compatible = "simple-bus";
 152                 #address-cells = <1>;
 153                 #size-cells = <1>;
 154                 ranges = <0 0 0 0xffffffff>;
 155
 156                 spi0: spi@54006000 {
 157                         compatible = "socionext,uniphier-scssi";
 158                         status = "disabled";
 159                         reg = <0x54006000 0x100>;
 160                         interrupts = <0 39 4>;
 161                         pinctrl-names = "default";
 162                         pinctrl-0 = <&pinctrl_spi0>;
 163                         clocks = <&peri_clk 11>;
 164                         resets = <&peri_rst 11>;
 165                 };
 166
 167                 spi1: spi@54006100 {
 168                         compatible = "socionext,uniphier-scssi";
 169                         status = "disabled";
 170                         reg = <0x54006100 0x100>;
 171                         interrupts = <0 216 4>;
 172                         pinctrl-names = "default";
 173                         pinctrl-0 = <&pinctrl_spi1>;
 174                         clocks = <&peri_clk 11>;
 175                         resets = <&peri_rst 11>;
 176                 };
 177
 178                 serial0: serial@54006800 {
 179                         compatible = "socionext,uniphier-uart";
 180                         status = "disabled";
 181                         reg = <0x54006800 0x40>;
 182                         interrupts = <0 33 4>;
 183                         pinctrl-names = "default";
 184                         pinctrl-0 = <&pinctrl_uart0>;
 185                         clocks = <&peri_clk 0>;
 186                         resets = <&peri_rst 0>;
 187                 };
 188
 189                 serial1: serial@54006900 {
 190                         compatible = "socionext,uniphier-uart";
 191                         status = "disabled";
 192                         reg = <0x54006900 0x40>;
 193                         interrupts = <0 35 4>;
 194                         pinctrl-names = "default";
 195                         pinctrl-0 = <&pinctrl_uart1>;
 196                         clocks = <&peri_clk 1>;
 197                         resets = <&peri_rst 1>;
 198                 };
 199
 200                 serial2: serial@54006a00 {
 201                         compatible = "socionext,uniphier-uart";
 202                         status = "disabled";
 203                         reg = <0x54006a00 0x40>;
 204                         interrupts = <0 37 4>;
 205                         pinctrl-names = "default";
 206                         pinctrl-0 = <&pinctrl_uart2>;
 207                         clocks = <&peri_clk 2>;
 208                         resets = <&peri_rst 2>;
 209                 };
 210
 211                 serial3: serial@54006b00 {
 212                         compatible = "socionext,uniphier-uart";
 213                         status = "disabled";
 214                         reg = <0x54006b00 0x40>;
 215                         interrupts = <0 177 4>;
 216                         pinctrl-names = "default";
 217                         pinctrl-0 = <&pinctrl_uart3>;
 218                         clocks = <&peri_clk 3>;
 219                         resets = <&peri_rst 3>;
 220                 };
 221
 222                 gpio: gpio@55000000 {
 223                         compatible = "socionext,uniphier-gpio";
 224                         reg = <0x55000000 0x200>;
 225                         interrupt-parent = <&aidet>;
 226                         interrupt-controller;
 227                         #interrupt-cells = <2>;
 228                         gpio-controller;
 229                         #gpio-cells = <2>;
 230                         gpio-ranges = <&pinctrl 0 0 0>,
 231                                       <&pinctrl 104 0 0>,
 232                                       <&pinctrl 168 0 0>;
 233                         gpio-ranges-group-names = "gpio_range0",
 234                                                   "gpio_range1",
 235                                                   "gpio_range2";
 236                         ngpios = <286>;
 237                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 238                                                      <21 217 3>;
 239                 };
 240
 241                 i2c0: i2c@58780000 {
 242                         compatible = "socionext,uniphier-fi2c";
 243                         status = "disabled";
 244                         reg = <0x58780000 0x80>;
 245                         #address-cells = <1>;
 246                         #size-cells = <0>;
 247                         interrupts = <0 41 4>;
 248                         pinctrl-names = "default";
 249                         pinctrl-0 = <&pinctrl_i2c0>;
 250                         clocks = <&peri_clk 4>;
 251                         resets = <&peri_rst 4>;
 252                         clock-frequency = <100000>;
 253                 };
 254
 255                 i2c1: i2c@58781000 {
 256                         compatible = "socionext,uniphier-fi2c";
 257                         status = "disabled";
 258                         reg = <0x58781000 0x80>;
 259                         #address-cells = <1>;
 260                         #size-cells = <0>;
 261                         interrupts = <0 42 4>;
 262                         pinctrl-names = "default";
 263                         pinctrl-0 = <&pinctrl_i2c1>;
 264                         clocks = <&peri_clk 5>;
 265                         resets = <&peri_rst 5>;
 266                         clock-frequency = <100000>;
 267                 };
 268
 269                 i2c2: i2c@58782000 {
 270                         compatible = "socionext,uniphier-fi2c";
 271                         status = "disabled";
 272                         reg = <0x58782000 0x80>;
 273                         #address-cells = <1>;
 274                         #size-cells = <0>;
 275                         interrupts = <0 43 4>;
 276                         pinctrl-names = "default";
 277                         pinctrl-0 = <&pinctrl_i2c2>;
 278                         clocks = <&peri_clk 6>;
 279                         resets = <&peri_rst 6>;
 280                         clock-frequency = <100000>;
 281                 };
 282
 283                 i2c3: i2c@58783000 {
 284                         compatible = "socionext,uniphier-fi2c";
 285                         status = "disabled";
 286                         reg = <0x58783000 0x80>;
 287                         #address-cells = <1>;
 288                         #size-cells = <0>;
 289                         interrupts = <0 44 4>;
 290                         pinctrl-names = "default";
 291                         pinctrl-0 = <&pinctrl_i2c3>;
 292                         clocks = <&peri_clk 7>;
 293                         resets = <&peri_rst 7>;
 294                         clock-frequency = <100000>;
 295                 };
 296
 297                 /* chip-internal connection for HDMI */
 298                 i2c6: i2c@58786000 {
 299                         compatible = "socionext,uniphier-fi2c";
 300                         reg = <0x58786000 0x80>;
 301                         #address-cells = <1>;
 302                         #size-cells = <0>;
 303                         interrupts = <0 26 4>;
 304                         clocks = <&peri_clk 10>;
 305                         resets = <&peri_rst 10>;
 306                         clock-frequency = <400000>;
 307                 };
 308
 309                 system_bus: system-bus@58c00000 {
 310                         compatible = "socionext,uniphier-system-bus";
 311                         status = "disabled";
 312                         reg = <0x58c00000 0x400>;
 313                         #address-cells = <2>;
 314                         #size-cells = <1>;
 315                         pinctrl-names = "default";
 316                         pinctrl-0 = <&pinctrl_system_bus>;
 317                 };
 318
 319                 smpctrl@59801000 {
 320                         compatible = "socionext,uniphier-smpctrl";
 321                         reg = <0x59801000 0x400>;
 322                 };
 323
 324                 sdctrl@59810000 {
 325                         compatible = "socionext,uniphier-pxs3-sdctrl",
 326                                      "simple-mfd", "syscon";
 327                         reg = <0x59810000 0x400>;
 328
 329                         sd_clk: clock {
 330                                 compatible = "socionext,uniphier-pxs3-sd-clock";
 331                                 #clock-cells = <1>;
 332                         };
 333
 334                         sd_rst: reset {
 335                                 compatible = "socionext,uniphier-pxs3-sd-reset";
 336                                 #reset-cells = <1>;
 337                         };
 338                 };
 339
 340                 perictrl@59820000 {
 341                         compatible = "socionext,uniphier-pxs3-perictrl",
 342                                      "simple-mfd", "syscon";
 343                         reg = <0x59820000 0x200>;
 344
 345                         peri_clk: clock {
 346                                 compatible = "socionext,uniphier-pxs3-peri-clock";
 347                                 #clock-cells = <1>;
 348                         };
 349
 350                         peri_rst: reset {
 351                                 compatible = "socionext,uniphier-pxs3-peri-reset";
 352                                 #reset-cells = <1>;
 353                         };
 354                 };
 355
 356                 emmc: sdhc@5a000000 {
 357                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 358                         reg = <0x5a000000 0x400>;
 359                         interrupts = <0 78 4>;
 360                         pinctrl-names = "default";
 361                         pinctrl-0 = <&pinctrl_emmc>;
 362                         clocks = <&sys_clk 4>;
 363                         resets = <&sys_rst 4>;
 364                         bus-width = <8>;
 365                         mmc-ddr-1_8v;
 366                         mmc-hs200-1_8v;
 367                         mmc-pwrseq = <&emmc_pwrseq>;
 368                         cdns,phy-input-delay-legacy = <9>;
 369                         cdns,phy-input-delay-mmc-highspeed = <2>;
 370                         cdns,phy-input-delay-mmc-ddr = <3>;
 371                         cdns,phy-dll-delay-sdclk = <21>;
 372                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 373                 };
 374
 375                 sd: sdhc@5a400000 {
 376                         compatible = "socionext,uniphier-sd-v3.1.1";
 377                         status = "disabled";
 378                         reg = <0x5a400000 0x800>;
 379                         interrupts = <0 76 4>;
 380                         pinctrl-names = "default", "uhs";
 381                         pinctrl-0 = <&pinctrl_sd>;
 382                         pinctrl-1 = <&pinctrl_sd_uhs>;
 383                         clocks = <&sd_clk 0>;
 384                         reset-names = "host";
 385                         resets = <&sd_rst 0>;
 386                         bus-width = <4>;
 387                         cap-sd-highspeed;
 388                         sd-uhs-sdr12;
 389                         sd-uhs-sdr25;
 390                         sd-uhs-sdr50;
 391                 };
 392
 393                 soc_glue: soc-glue@5f800000 {
 394                         compatible = "socionext,uniphier-pxs3-soc-glue",
 395                                      "simple-mfd", "syscon";
 396                         reg = <0x5f800000 0x2000>;
 397
 398                         pinctrl: pinctrl {
 399                                 compatible = "socionext,uniphier-pxs3-pinctrl";
 400                         };
 401                 };
 402
 403                 soc-glue@5f900000 {
 404                         compatible = "socionext,uniphier-pxs3-soc-glue-debug",
 405                                      "simple-mfd";
 406                         #address-cells = <1>;
 407                         #size-cells = <1>;
 408                         ranges = <0 0x5f900000 0x2000>;
 409
 410                         efuse@100 {
 411                                 compatible = "socionext,uniphier-efuse";
 412                                 reg = <0x100 0x28>;
 413                         };
 414
 415                         efuse@200 {
 416                                 compatible = "socionext,uniphier-efuse";
 417                                 reg = <0x200 0x68>;
 418                                 #address-cells = <1>;
 419                                 #size-cells = <1>;
 420
 421                                 /* USB cells */
 422                                 usb_rterm0: trim@54,4 {
 423                                         reg = <0x54 1>;
 424                                         bits = <4 2>;
 425                                 };
 426                                 usb_rterm1: trim@55,4 {
 427                                         reg = <0x55 1>;
 428                                         bits = <4 2>;
 429                                 };
 430                                 usb_rterm2: trim@58,4 {
 431                                         reg = <0x58 1>;
 432                                         bits = <4 2>;
 433                                 };
 434                                 usb_rterm3: trim@59,4 {
 435                                         reg = <0x59 1>;
 436                                         bits = <4 2>;
 437                                 };
 438                                 usb_sel_t0: trim@54,0 {
 439                                         reg = <0x54 1>;
 440                                         bits = <0 4>;
 441                                 };
 442                                 usb_sel_t1: trim@55,0 {
 443                                         reg = <0x55 1>;
 444                                         bits = <0 4>;
 445                                 };
 446                                 usb_sel_t2: trim@58,0 {
 447                                         reg = <0x58 1>;
 448                                         bits = <0 4>;
 449                                 };
 450                                 usb_sel_t3: trim@59,0 {
 451                                         reg = <0x59 1>;
 452                                         bits = <0 4>;
 453                                 };
 454                                 usb_hs_i0: trim@56,0 {
 455                                         reg = <0x56 1>;
 456                                         bits = <0 4>;
 457                                 };
 458                                 usb_hs_i2: trim@5a,0 {
 459                                         reg = <0x5a 1>;
 460                                         bits = <0 4>;
 461                                 };
 462                         };
 463                 };
 464
 465                 aidet: aidet@5fc20000 {
 466                         compatible = "socionext,uniphier-pxs3-aidet";
 467                         reg = <0x5fc20000 0x200>;
 468                         interrupt-controller;
 469                         #interrupt-cells = <2>;
 470                 };
 471
 472                 gic: interrupt-controller@5fe00000 {
 473                         compatible = "arm,gic-v3";
 474                         reg = <0x5fe00000 0x10000>,     /* GICD */
 475                               <0x5fe80000 0x80000>;     /* GICR */
 476                         interrupt-controller;
 477                         #interrupt-cells = <3>;
 478                         interrupts = <1 9 4>;
 479                 };
 480
 481                 sysctrl@61840000 {
 482                         compatible = "socionext,uniphier-pxs3-sysctrl",
 483                                      "simple-mfd", "syscon";
 484                         reg = <0x61840000 0x10000>;
 485
 486                         sys_clk: clock {
 487                                 compatible = "socionext,uniphier-pxs3-clock";
 488                                 #clock-cells = <1>;
 489                         };
 490
 491                         sys_rst: reset {
 492                                 compatible = "socionext,uniphier-pxs3-reset";
 493                                 #reset-cells = <1>;
 494                         };
 495
 496                         watchdog {
 497                                 compatible = "socionext,uniphier-wdt";
 498                         };
 499                 };
 500
 501                 eth0: ethernet@65000000 {
 502                         compatible = "socionext,uniphier-pxs3-ave4";
 503                         status = "disabled";
 504                         reg = <0x65000000 0x8500>;
 505                         interrupts = <0 66 4>;
 506                         pinctrl-names = "default";
 507                         pinctrl-0 = <&pinctrl_ether_rgmii>;
 508                         clock-names = "ether";
 509                         clocks = <&sys_clk 6>;
 510                         reset-names = "ether";
 511                         resets = <&sys_rst 6>;
 512                         phy-mode = "rgmii";
 513                         local-mac-address = [00 00 00 00 00 00];
 514                         socionext,syscon-phy-mode = <&soc_glue 0>;
 515
 516                         mdio0: mdio {
 517                                 #address-cells = <1>;
 518                                 #size-cells = <0>;
 519                         };
 520                 };
 521
 522                 eth1: ethernet@65200000 {
 523                         compatible = "socionext,uniphier-pxs3-ave4";
 524                         status = "disabled";
 525                         reg = <0x65200000 0x8500>;
 526                         interrupts = <0 67 4>;
 527                         pinctrl-names = "default";
 528                         pinctrl-0 = <&pinctrl_ether1_rgmii>;
 529                         clock-names = "ether";
 530                         clocks = <&sys_clk 7>;
 531                         reset-names = "ether";
 532                         resets = <&sys_rst 7>;
 533                         phy-mode = "rgmii";
 534                         local-mac-address = [00 00 00 00 00 00];
 535                         socionext,syscon-phy-mode = <&soc_glue 1>;
 536
 537                         mdio1: mdio {
 538                                 #address-cells = <1>;
 539                                 #size-cells = <0>;
 540                         };
 541                 };
 542
 543                 usb0: usb@65a00000 {
 544                         compatible = "socionext,uniphier-dwc3", "snps,dwc3";
 545                         status = "disabled";
 546                         reg = <0x65a00000 0xcd00>;
 547                         interrupt-names = "host", "peripheral";
 548                         interrupts = <0 134 4>, <0 135 4>;
 549                         pinctrl-names = "default";
 550                         pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
 551                         clock-names = "ref", "bus_early", "suspend";
 552                         clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
 553                         resets = <&usb0_rst 15>;
 554                         phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
 555                                <&usb0_ssphy0>, <&usb0_ssphy1>;
 556                         dr_mode = "host";
 557                 };
 558
 559                 usb-glue@65b00000 {
 560                         compatible = "socionext,uniphier-pxs3-dwc3-glue",
 561                                      "simple-mfd";
 562                         #address-cells = <1>;
 563                         #size-cells = <1>;
 564                         ranges = <0 0x65b00000 0x400>;
 565
 566                         usb0_rst: reset@0 {
 567                                 compatible = "socionext,uniphier-pxs3-usb3-reset";
 568                                 reg = <0x0 0x4>;
 569                                 #reset-cells = <1>;
 570                                 clock-names = "link";
 571                                 clocks = <&sys_clk 12>;
 572                                 reset-names = "link";
 573                                 resets = <&sys_rst 12>;
 574                         };
 575
 576                         usb0_vbus0: regulator@100 {
 577                                 compatible = "socionext,uniphier-pxs3-usb3-regulator";
 578                                 reg = <0x100 0x10>;
 579                                 clock-names = "link";
 580                                 clocks = <&sys_clk 12>;
 581                                 reset-names = "link";
 582                                 resets = <&sys_rst 12>;
 583                         };
 584
 585                         usb0_vbus1: regulator@110 {
 586                                 compatible = "socionext,uniphier-pxs3-usb3-regulator";
 587                                 reg = <0x110 0x10>;
 588                                 clock-names = "link";
 589                                 clocks = <&sys_clk 12>;
 590                                 reset-names = "link";
 591                                 resets = <&sys_rst 12>;
 592                         };
 593
 594                         usb0_hsphy0: hs-phy@200 {
 595                                 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
 596                                 reg = <0x200 0x10>;
 597                                 #phy-cells = <0>;
 598                                 clock-names = "link", "phy";
 599                                 clocks = <&sys_clk 12>, <&sys_clk 16>;
 600                                 reset-names = "link", "phy";
 601                                 resets = <&sys_rst 12>, <&sys_rst 16>;
 602                                 vbus-supply = <&usb0_vbus0>;
 603                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 604                                 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
 605                                               <&usb_hs_i0>;
 606                         };
 607
 608                         usb0_hsphy1: hs-phy@210 {
 609                                 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
 610                                 reg = <0x210 0x10>;
 611                                 #phy-cells = <0>;
 612                                 clock-names = "link", "phy";
 613                                 clocks = <&sys_clk 12>, <&sys_clk 16>;
 614                                 reset-names = "link", "phy";
 615                                 resets = <&sys_rst 12>, <&sys_rst 16>;
 616                                 vbus-supply = <&usb0_vbus1>;
 617                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 618                                 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
 619                                               <&usb_hs_i0>;
 620                         };
 621
 622                         usb0_ssphy0: ss-phy@300 {
 623                                 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
 624                                 reg = <0x300 0x10>;
 625                                 #phy-cells = <0>;
 626                                 clock-names = "link", "phy";
 627                                 clocks = <&sys_clk 12>, <&sys_clk 17>;
 628                                 reset-names = "link", "phy";
 629                                 resets = <&sys_rst 12>, <&sys_rst 17>;
 630                                 vbus-supply = <&usb0_vbus0>;
 631                         };
 632
 633                         usb0_ssphy1: ss-phy@310 {
 634                                 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
 635                                 reg = <0x310 0x10>;
 636                                 #phy-cells = <0>;
 637                                 clock-names = "link", "phy";
 638                                 clocks = <&sys_clk 12>, <&sys_clk 18>;
 639                                 reset-names = "link", "phy";
 640                                 resets = <&sys_rst 12>, <&sys_rst 18>;
 641                                 vbus-supply = <&usb0_vbus1>;
 642                         };
 643                 };
 644
 645                 usb1: usb@65c00000 {
 646                         compatible = "socionext,uniphier-dwc3", "snps,dwc3";
 647                         status = "disabled";
 648                         reg = <0x65c00000 0xcd00>;
 649                         interrupt-names = "host", "peripheral";
 650                         interrupts = <0 137 4>, <0 138 4>;
 651                         pinctrl-names = "default";
 652                         pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
 653                         clock-names = "ref", "bus_early", "suspend";
 654                         clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
 655                         resets = <&usb1_rst 15>;
 656                         phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
 657                                <&usb1_ssphy0>;
 658                         dr_mode = "host";
 659                 };
 660
 661                 usb-glue@65d00000 {
 662                         compatible = "socionext,uniphier-pxs3-dwc3-glue",
 663                                      "simple-mfd";
 664                         #address-cells = <1>;
 665                         #size-cells = <1>;
 666                         ranges = <0 0x65d00000 0x400>;
 667
 668                         usb1_rst: reset@0 {
 669                                 compatible = "socionext,uniphier-pxs3-usb3-reset";
 670                                 reg = <0x0 0x4>;
 671                                 #reset-cells = <1>;
 672                                 clock-names = "link";
 673                                 clocks = <&sys_clk 13>;
 674                                 reset-names = "link";
 675                                 resets = <&sys_rst 13>;
 676                         };
 677
 678                         usb1_vbus0: regulator@100 {
 679                                 compatible = "socionext,uniphier-pxs3-usb3-regulator";
 680                                 reg = <0x100 0x10>;
 681                                 clock-names = "link";
 682                                 clocks = <&sys_clk 13>;
 683                                 reset-names = "link";
 684                                 resets = <&sys_rst 13>;
 685                         };
 686
 687                         usb1_vbus1: regulator@110 {
 688                                 compatible = "socionext,uniphier-pxs3-usb3-regulator";
 689                                 reg = <0x110 0x10>;
 690                                 clock-names = "link";
 691                                 clocks = <&sys_clk 13>;
 692                                 reset-names = "link";
 693                                 resets = <&sys_rst 13>;
 694                         };
 695
 696                         usb1_hsphy0: hs-phy@200 {
 697                                 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
 698                                 reg = <0x200 0x10>;
 699                                 #phy-cells = <0>;
 700                                 clock-names = "link", "phy", "phy-ext";
 701                                 clocks = <&sys_clk 13>, <&sys_clk 20>,
 702                                          <&sys_clk 14>;
 703                                 reset-names = "link", "phy";
 704                                 resets = <&sys_rst 13>, <&sys_rst 20>;
 705                                 vbus-supply = <&usb1_vbus0>;
 706                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 707                                 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
 708                                               <&usb_hs_i2>;
 709                         };
 710
 711                         usb1_hsphy1: hs-phy@210 {
 712                                 compatible = "socionext,uniphier-pxs3-usb3-hsphy";
 713                                 reg = <0x210 0x10>;
 714                                 #phy-cells = <0>;
 715                                 clock-names = "link", "phy", "phy-ext";
 716                                 clocks = <&sys_clk 13>, <&sys_clk 20>,
 717                                          <&sys_clk 14>;
 718                                 reset-names = "link", "phy";
 719                                 resets = <&sys_rst 13>, <&sys_rst 20>;
 720                                 vbus-supply = <&usb1_vbus1>;
 721                                 nvmem-cell-names = "rterm", "sel_t", "hs_i";
 722                                 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
 723                                               <&usb_hs_i2>;
 724                         };
 725
 726                         usb1_ssphy0: ss-phy@300 {
 727                                 compatible = "socionext,uniphier-pxs3-usb3-ssphy";
 728                                 reg = <0x300 0x10>;
 729                                 #phy-cells = <0>;
 730                                 clock-names = "link", "phy", "phy-ext";
 731                                 clocks = <&sys_clk 13>, <&sys_clk 21>,
 732                                          <&sys_clk 14>;
 733                                 reset-names = "link", "phy";
 734                                 resets = <&sys_rst 13>, <&sys_rst 21>;
 735                                 vbus-supply = <&usb1_vbus0>;
 736                         };
 737                 };
 738
 739                 pcie: pcie@66000000 {
 740                         compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
 741                         status = "disabled";
 742                         reg-names = "dbi", "link", "config";
 743                         reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
 744                               <0x2fff0000 0x10000>;
 745                         #address-cells = <3>;
 746                         #size-cells = <2>;
 747                         clocks = <&sys_clk 24>;
 748                         resets = <&sys_rst 24>;
 749                         num-lanes = <1>;
 750                         num-viewport = <1>;
 751                         bus-range = <0x0 0xff>;
 752                         device_type = "pci";
 753                         ranges =
 754                         /* downstream I/O */
 755                                 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
 756                         /* non-prefetchable memory */
 757                                 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
 758                         #interrupt-cells = <1>;
 759                         interrupt-names = "dma", "msi";
 760                         interrupts = <0 224 4>, <0 225 4>;
 761                         interrupt-map-mask = <0 0 0 7>;
 762                         interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
 763                                         <0 0 0 2 &pcie_intc 1>, /* INTB */
 764                                         <0 0 0 3 &pcie_intc 2>, /* INTC */
 765                                         <0 0 0 4 &pcie_intc 3>; /* INTD */
 766                         phy-names = "pcie-phy";
 767                         phys = <&pcie_phy>;
 768
 769                         pcie_intc: legacy-interrupt-controller {
 770                                 interrupt-controller;
 771                                 #interrupt-cells = <1>;
 772                                 interrupt-parent = <&gic>;
 773                                 interrupts = <0 226 4>;
 774                         };
 775                 };
 776
 777                 pcie_phy: phy@66038000 {
 778                         compatible = "socionext,uniphier-pxs3-pcie-phy";
 779                         reg = <0x66038000 0x4000>;
 780                         #phy-cells = <0>;
 781                         clocks = <&sys_clk 24>;
 782                         resets = <&sys_rst 24>;
 783                         socionext,syscon = <&soc_glue>;
 784                 };
 785
 786                 nand: nand@68000000 {
 787                         compatible = "socionext,uniphier-denali-nand-v5b";
 788                         status = "disabled";
 789                         reg-names = "nand_data", "denali_reg";
 790                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 791                         #address-cells = <1>;
 792                         #size-cells = <0>;
 793                         interrupts = <0 65 4>;
 794                         pinctrl-names = "default";
 795                         pinctrl-0 = <&pinctrl_nand>;
 796                         clock-names = "nand", "nand_x", "ecc";
 797                         clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 798                         resets = <&sys_rst 2>;
 799                 };
 800         };
 801 };
 802
 803 #include "uniphier-pinctrl.dtsi"