arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3399";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 i2c6 = &i2c6;
  66                 i2c7 = &i2c7;
  67                 i2c8 = &i2c8;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73         };
  74
  75         cpus {
  76                 #address-cells = <2>;
  77                 #size-cells = <0>;
  78
  79                 cpu-map {
  80                         cluster0 {
  81                                 core0 {
  82                                         cpu = <&cpu_l0>;
  83                                 };
  84                                 core1 {
  85                                         cpu = <&cpu_l1>;
  86                                 };
  87                                 core2 {
  88                                         cpu = <&cpu_l2>;
  89                                 };
  90                                 core3 {
  91                                         cpu = <&cpu_l3>;
  92                                 };
  93                         };
  94
  95                         cluster1 {
  96                                 core0 {
  97                                         cpu = <&cpu_b0>;
  98                                 };
  99                                 core1 {
 100                                         cpu = <&cpu_b1>;
 101                                 };
 102                         };
 103                 };
 104
 105                 cpu_l0: cpu@0 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a53", "arm,armv8";
 108                         reg = <0x0 0x0>;
 109                         enable-method = "psci";
 110                         #cooling-cells = <2>; /* min followed by max */
 111                         clocks = <&cru ARMCLKL>;
 112                 };
 113
 114                 cpu_l1: cpu@1 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a53", "arm,armv8";
 117                         reg = <0x0 0x1>;
 118                         enable-method = "psci";
 119                         clocks = <&cru ARMCLKL>;
 120                 };
 121
 122                 cpu_l2: cpu@2 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53", "arm,armv8";
 125                         reg = <0x0 0x2>;
 126                         enable-method = "psci";
 127                         clocks = <&cru ARMCLKL>;
 128                 };
 129
 130                 cpu_l3: cpu@3 {
 131                         device_type = "cpu";
 132                         compatible = "arm,cortex-a53", "arm,armv8";
 133                         reg = <0x0 0x3>;
 134                         enable-method = "psci";
 135                         clocks = <&cru ARMCLKL>;
 136                 };
 137
 138                 cpu_b0: cpu@100 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a72", "arm,armv8";
 141                         reg = <0x0 0x100>;
 142                         enable-method = "psci";
 143                         #cooling-cells = <2>; /* min followed by max */
 144                         clocks = <&cru ARMCLKB>;
 145                 };
 146
 147                 cpu_b1: cpu@101 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a72", "arm,armv8";
 150                         reg = <0x0 0x101>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKB>;
 153                 };
 154         };
 155
 156         pmu_a53 {
 157                 compatible = "arm,cortex-a53-pmu";
 158                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 159         };
 160
 161         pmu_a72 {
 162                 compatible = "arm,cortex-a72-pmu";
 163                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 164         };
 165
 166         psci {
 167                 compatible = "arm,psci-1.0";
 168                 method = "smc";
 169         };
 170
 171         timer {
 172                 compatible = "arm,armv8-timer";
 173                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 174                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 175                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 176                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 177                 arm,no-tick-in-suspend;
 178         };
 179
 180         xin24m: xin24m {
 181                 compatible = "fixed-clock";
 182                 clock-frequency = <24000000>;
 183                 clock-output-names = "xin24m";
 184                 #clock-cells = <0>;
 185         };
 186
 187         amba {
 188                 compatible = "simple-bus";
 189                 #address-cells = <2>;
 190                 #size-cells = <2>;
 191                 ranges;
 192
 193                 dmac_bus: dma-controller@ff6d0000 {
 194                         compatible = "arm,pl330", "arm,primecell";
 195                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 196                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 197                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 198                         #dma-cells = <1>;
 199                         clocks = <&cru ACLK_DMAC0_PERILP>;
 200                         clock-names = "apb_pclk";
 201                 };
 202
 203                 dmac_peri: dma-controller@ff6e0000 {
 204                         compatible = "arm,pl330", "arm,primecell";
 205                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 206                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 207                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 208                         #dma-cells = <1>;
 209                         clocks = <&cru ACLK_DMAC1_PERILP>;
 210                         clock-names = "apb_pclk";
 211                 };
 212         };
 213
 214         gmac: ethernet@fe300000 {
 215                 compatible = "rockchip,rk3399-gmac";
 216                 reg = <0x0 0xfe300000 0x0 0x10000>;
 217                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 218                 interrupt-names = "macirq";
 219                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 220                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 221                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 222                          <&cru PCLK_GMAC>;
 223                 clock-names = "stmmaceth", "mac_clk_rx",
 224                               "mac_clk_tx", "clk_mac_ref",
 225                               "clk_mac_refout", "aclk_mac",
 226                               "pclk_mac";
 227                 power-domains = <&power RK3399_PD_GMAC>;
 228                 resets = <&cru SRST_A_GMAC>;
 229                 reset-names = "stmmaceth";
 230                 rockchip,grf = <&grf>;
 231                 status = "disabled";
 232         };
 233
 234         sdio0: dwmmc@fe310000 {
 235                 compatible = "rockchip,rk3399-dw-mshc",
 236                              "rockchip,rk3288-dw-mshc";
 237                 reg = <0x0 0xfe310000 0x0 0x4000>;
 238                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 239                 max-frequency = <150000000>;
 240                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 241                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 242                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 243                 fifo-depth = <0x100>;
 244                 status = "disabled";
 245         };
 246
 247         sdmmc: dwmmc@fe320000 {
 248                 compatible = "rockchip,rk3399-dw-mshc",
 249                              "rockchip,rk3288-dw-mshc";
 250                 reg = <0x0 0xfe320000 0x0 0x4000>;
 251                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 252                 max-frequency = <150000000>;
 253                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 254                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 255                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 256                 fifo-depth = <0x100>;
 257                 power-domains = <&power RK3399_PD_SD>;
 258                 status = "disabled";
 259         };
 260
 261         sdhci: sdhci@fe330000 {
 262                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 263                 reg = <0x0 0xfe330000 0x0 0x10000>;
 264                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 265                 arasan,soc-ctl-syscon = <&grf>;
 266                 assigned-clocks = <&cru SCLK_EMMC>;
 267                 assigned-clock-rates = <200000000>;
 268                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 269                 clock-names = "clk_xin", "clk_ahb";
 270                 clock-output-names = "emmc_cardclock";
 271                 #clock-cells = <0>;
 272                 phys = <&emmc_phy>;
 273                 phy-names = "phy_arasan";
 274                 power-domains = <&power RK3399_PD_EMMC>;
 275                 status = "disabled";
 276         };
 277
 278         pcie0: pcie@f8000000 {
 279                 compatible = "rockchip,rk3399-pcie";
 280                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 281                       <0x0 0xfd000000 0x0 0x1000000>;
 282                 reg-names = "axi-base", "apb-base";
 283                 #address-cells = <3>;
 284                 #size-cells = <2>;
 285                 #interrupt-cells = <1>;
 286                 bus-range = <0x0 0x1>;
 287                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 288                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 289                 clock-names = "aclk", "aclk-perf",
 290                               "hclk", "pm";
 291                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 292                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 293                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 294                 interrupt-names = "sys", "legacy", "client";
 295                 interrupt-map-mask = <0 0 0 7>;
 296                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 297                                 <0 0 0 2 &pcie0_intc 1>,
 298                                 <0 0 0 3 &pcie0_intc 2>,
 299                                 <0 0 0 4 &pcie0_intc 3>;
 300                 msi-map = <0x0 &its 0x0 0x1000>;
 301                 phys = <&pcie_phy>;
 302                 phy-names = "pcie-phy";
 303                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
 304                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
 305                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 306                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 307                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
 308                          <&cru SRST_A_PCIE>;
 309                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 310                               "pm", "pclk", "aclk";
 311                 status = "disabled";
 312
 313                 pcie0_intc: interrupt-controller {
 314                         interrupt-controller;
 315                         #address-cells = <0>;
 316                         #interrupt-cells = <1>;
 317                 };
 318         };
 319
 320         usb_host0_ehci: usb@fe380000 {
 321                 compatible = "generic-ehci";
 322                 reg = <0x0 0xfe380000 0x0 0x20000>;
 323                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 324                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 325                 clock-names = "hclk_host0", "hclk_host0_arb";
 326                 phys = <&u2phy0_host>;
 327                 phy-names = "usb";
 328                 status = "disabled";
 329         };
 330
 331         usb_host0_ohci: usb@fe3a0000 {
 332                 compatible = "generic-ohci";
 333                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 334                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 335                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 336                 clock-names = "hclk_host0", "hclk_host0_arb";
 337                 status = "disabled";
 338         };
 339
 340         usb_host1_ehci: usb@fe3c0000 {
 341                 compatible = "generic-ehci";
 342                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 343                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 344                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 345                 clock-names = "hclk_host1", "hclk_host1_arb";
 346                 phys = <&u2phy1_host>;
 347                 phy-names = "usb";
 348                 status = "disabled";
 349         };
 350
 351         usb_host1_ohci: usb@fe3e0000 {
 352                 compatible = "generic-ohci";
 353                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 354                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 355                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 356                 clock-names = "hclk_host1", "hclk_host1_arb";
 357                 status = "disabled";
 358         };
 359
 360         gic: interrupt-controller@fee00000 {
 361                 compatible = "arm,gic-v3";
 362                 #interrupt-cells = <4>;
 363                 #address-cells = <2>;
 364                 #size-cells = <2>;
 365                 ranges;
 366                 interrupt-controller;
 367
 368                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 369                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 370                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 371                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 372                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 373                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 374                 its: interrupt-controller@fee20000 {
 375                         compatible = "arm,gic-v3-its";
 376                         msi-controller;
 377                         reg = <0x0 0xfee20000 0x0 0x20000>;
 378                 };
 379
 380                 ppi-partitions {
 381                         ppi_cluster0: interrupt-partition-0 {
 382                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 383                         };
 384
 385                         ppi_cluster1: interrupt-partition-1 {
 386                                 affinity = <&cpu_b0 &cpu_b1>;
 387                         };
 388                 };
 389         };
 390
 391         saradc: saradc@ff100000 {
 392                 compatible = "rockchip,rk3399-saradc";
 393                 reg = <0x0 0xff100000 0x0 0x100>;
 394                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 395                 #io-channel-cells = <1>;
 396                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 397                 clock-names = "saradc", "apb_pclk";
 398                 resets = <&cru SRST_P_SARADC>;
 399                 reset-names = "saradc-apb";
 400                 status = "disabled";
 401         };
 402
 403         i2c1: i2c@ff110000 {
 404                 compatible = "rockchip,rk3399-i2c";
 405                 reg = <0x0 0xff110000 0x0 0x1000>;
 406                 assigned-clocks = <&cru SCLK_I2C1>;
 407                 assigned-clock-rates = <200000000>;
 408                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 409                 clock-names = "i2c", "pclk";
 410                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 411                 pinctrl-names = "default";
 412                 pinctrl-0 = <&i2c1_xfer>;
 413                 #address-cells = <1>;
 414                 #size-cells = <0>;
 415                 status = "disabled";
 416         };
 417
 418         i2c2: i2c@ff120000 {
 419                 compatible = "rockchip,rk3399-i2c";
 420                 reg = <0x0 0xff120000 0x0 0x1000>;
 421                 assigned-clocks = <&cru SCLK_I2C2>;
 422                 assigned-clock-rates = <200000000>;
 423                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 424                 clock-names = "i2c", "pclk";
 425                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 426                 pinctrl-names = "default";
 427                 pinctrl-0 = <&i2c2_xfer>;
 428                 #address-cells = <1>;
 429                 #size-cells = <0>;
 430                 status = "disabled";
 431         };
 432
 433         i2c3: i2c@ff130000 {
 434                 compatible = "rockchip,rk3399-i2c";
 435                 reg = <0x0 0xff130000 0x0 0x1000>;
 436                 assigned-clocks = <&cru SCLK_I2C3>;
 437                 assigned-clock-rates = <200000000>;
 438                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 439                 clock-names = "i2c", "pclk";
 440                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&i2c3_xfer>;
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445                 status = "disabled";
 446         };
 447
 448         i2c5: i2c@ff140000 {
 449                 compatible = "rockchip,rk3399-i2c";
 450                 reg = <0x0 0xff140000 0x0 0x1000>;
 451                 assigned-clocks = <&cru SCLK_I2C5>;
 452                 assigned-clock-rates = <200000000>;
 453                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 454                 clock-names = "i2c", "pclk";
 455                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 456                 pinctrl-names = "default";
 457                 pinctrl-0 = <&i2c5_xfer>;
 458                 #address-cells = <1>;
 459                 #size-cells = <0>;
 460                 status = "disabled";
 461         };
 462
 463         i2c6: i2c@ff150000 {
 464                 compatible = "rockchip,rk3399-i2c";
 465                 reg = <0x0 0xff150000 0x0 0x1000>;
 466                 assigned-clocks = <&cru SCLK_I2C6>;
 467                 assigned-clock-rates = <200000000>;
 468                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 469                 clock-names = "i2c", "pclk";
 470                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 471                 pinctrl-names = "default";
 472                 pinctrl-0 = <&i2c6_xfer>;
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 status = "disabled";
 476         };
 477
 478         i2c7: i2c@ff160000 {
 479                 compatible = "rockchip,rk3399-i2c";
 480                 reg = <0x0 0xff160000 0x0 0x1000>;
 481                 assigned-clocks = <&cru SCLK_I2C7>;
 482                 assigned-clock-rates = <200000000>;
 483                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 484                 clock-names = "i2c", "pclk";
 485                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&i2c7_xfer>;
 488                 #address-cells = <1>;
 489                 #size-cells = <0>;
 490                 status = "disabled";
 491         };
 492
 493         uart0: serial@ff180000 {
 494                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 495                 reg = <0x0 0xff180000 0x0 0x100>;
 496                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 497                 clock-names = "baudclk", "apb_pclk";
 498                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 499                 reg-shift = <2>;
 500                 reg-io-width = <4>;
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&uart0_xfer>;
 503                 status = "disabled";
 504         };
 505
 506         uart1: serial@ff190000 {
 507                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 508                 reg = <0x0 0xff190000 0x0 0x100>;
 509                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 510                 clock-names = "baudclk", "apb_pclk";
 511                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 512                 reg-shift = <2>;
 513                 reg-io-width = <4>;
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&uart1_xfer>;
 516                 status = "disabled";
 517         };
 518
 519         uart2: serial@ff1a0000 {
 520                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 521                 reg = <0x0 0xff1a0000 0x0 0x100>;
 522                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 523                 clock-names = "baudclk", "apb_pclk";
 524                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 525                 reg-shift = <2>;
 526                 reg-io-width = <4>;
 527                 pinctrl-names = "default";
 528                 pinctrl-0 = <&uart2c_xfer>;
 529                 status = "disabled";
 530         };
 531
 532         uart3: serial@ff1b0000 {
 533                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 534                 reg = <0x0 0xff1b0000 0x0 0x100>;
 535                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 536                 clock-names = "baudclk", "apb_pclk";
 537                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 538                 reg-shift = <2>;
 539                 reg-io-width = <4>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&uart3_xfer>;
 542                 status = "disabled";
 543         };
 544
 545         spi0: spi@ff1c0000 {
 546                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 547                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 548                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 549                 clock-names = "spiclk", "apb_pclk";
 550                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 status = "disabled";
 556         };
 557
 558         spi1: spi@ff1d0000 {
 559                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 560                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 561                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 562                 clock-names = "spiclk", "apb_pclk";
 563                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 566                 #address-cells = <1>;
 567                 #size-cells = <0>;
 568                 status = "disabled";
 569         };
 570
 571         spi2: spi@ff1e0000 {
 572                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 573                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 574                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 575                 clock-names = "spiclk", "apb_pclk";
 576                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 577                 pinctrl-names = "default";
 578                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 579                 #address-cells = <1>;
 580                 #size-cells = <0>;
 581                 status = "disabled";
 582         };
 583
 584         spi4: spi@ff1f0000 {
 585                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 586                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 587                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 588                 clock-names = "spiclk", "apb_pclk";
 589                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 590                 pinctrl-names = "default";
 591                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 592                 #address-cells = <1>;
 593                 #size-cells = <0>;
 594                 status = "disabled";
 595         };
 596
 597         spi5: spi@ff200000 {
 598                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 599                 reg = <0x0 0xff200000 0x0 0x1000>;
 600                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 601                 clock-names = "spiclk", "apb_pclk";
 602                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 603                 pinctrl-names = "default";
 604                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 605                 #address-cells = <1>;
 606                 #size-cells = <0>;
 607                 status = "disabled";
 608         };
 609
 610         thermal-zones {
 611                 cpu_thermal: cpu {
 612                         polling-delay-passive = <100>;
 613                         polling-delay = <1000>;
 614
 615                         thermal-sensors = <&tsadc 0>;
 616
 617                         trips {
 618                                 cpu_alert0: cpu_alert0 {
 619                                         temperature = <70000>;
 620                                         hysteresis = <2000>;
 621                                         type = "passive";
 622                                 };
 623                                 cpu_alert1: cpu_alert1 {
 624                                         temperature = <75000>;
 625                                         hysteresis = <2000>;
 626                                         type = "passive";
 627                                 };
 628                                 cpu_crit: cpu_crit {
 629                                         temperature = <95000>;
 630                                         hysteresis = <2000>;
 631                                         type = "critical";
 632                                 };
 633                         };
 634
 635                         cooling-maps {
 636                                 map0 {
 637                                         trip = <&cpu_alert0>;
 638                                         cooling-device =
 639                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 640                                 };
 641                                 map1 {
 642                                         trip = <&cpu_alert1>;
 643                                         cooling-device =
 644                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 645                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 646                                 };
 647                         };
 648                 };
 649
 650                 gpu_thermal: gpu {
 651                         polling-delay-passive = <100>;
 652                         polling-delay = <1000>;
 653
 654                         thermal-sensors = <&tsadc 1>;
 655
 656                         trips {
 657                                 gpu_alert0: gpu_alert0 {
 658                                         temperature = <75000>;
 659                                         hysteresis = <2000>;
 660                                         type = "passive";
 661                                 };
 662                                 gpu_crit: gpu_crit {
 663                                         temperature = <95000>;
 664                                         hysteresis = <2000>;
 665                                         type = "critical";
 666                                 };
 667                         };
 668
 669                         cooling-maps {
 670                                 map0 {
 671                                         trip = <&gpu_alert0>;
 672                                         cooling-device =
 673                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 674                                 };
 675                         };
 676                 };
 677         };
 678
 679         tsadc: tsadc@ff260000 {
 680                 compatible = "rockchip,rk3399-tsadc";
 681                 reg = <0x0 0xff260000 0x0 0x100>;
 682                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 683                 assigned-clocks = <&cru SCLK_TSADC>;
 684                 assigned-clock-rates = <750000>;
 685                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 686                 clock-names = "tsadc", "apb_pclk";
 687                 resets = <&cru SRST_TSADC>;
 688                 reset-names = "tsadc-apb";
 689                 rockchip,grf = <&grf>;
 690                 rockchip,hw-tshut-temp = <95000>;
 691                 pinctrl-names = "init", "default", "sleep";
 692                 pinctrl-0 = <&otp_gpio>;
 693                 pinctrl-1 = <&otp_out>;
 694                 pinctrl-2 = <&otp_gpio>;
 695                 #thermal-sensor-cells = <1>;
 696                 status = "disabled";
 697         };
 698
 699         qos_sd: qos@ffa74000 {
 700                 compatible = "syscon";
 701                 reg = <0x0 0xffa74000 0x0 0x20>;
 702         };
 703
 704         qos_emmc: qos@ffa58000 {
 705                 compatible = "syscon";
 706                 reg = <0x0 0xffa58000 0x0 0x20>;
 707         };
 708
 709         qos_gmac: qos@ffa5c000 {
 710                 compatible = "syscon";
 711                 reg = <0x0 0xffa5c000 0x0 0x20>;
 712         };
 713
 714         qos_hdcp: qos@ffa90000 {
 715                 compatible = "syscon";
 716                 reg = <0x0 0xffa90000 0x0 0x20>;
 717         };
 718
 719         qos_iep: qos@ffa98000 {
 720                 compatible = "syscon";
 721                 reg = <0x0 0xffa98000 0x0 0x20>;
 722         };
 723
 724         qos_isp0_m0: qos@ffaa0000 {
 725                 compatible = "syscon";
 726                 reg = <0x0 0xffaa0000 0x0 0x20>;
 727         };
 728
 729         qos_isp0_m1: qos@ffaa0080 {
 730                 compatible = "syscon";
 731                 reg = <0x0 0xffaa0080 0x0 0x20>;
 732         };
 733
 734         qos_isp1_m0: qos@ffaa8000 {
 735                 compatible = "syscon";
 736                 reg = <0x0 0xffaa8000 0x0 0x20>;
 737         };
 738
 739         qos_isp1_m1: qos@ffaa8080 {
 740                 compatible = "syscon";
 741                 reg = <0x0 0xffaa8080 0x0 0x20>;
 742         };
 743
 744         qos_rga_r: qos@ffab0000 {
 745                 compatible = "syscon";
 746                 reg = <0x0 0xffab0000 0x0 0x20>;
 747         };
 748
 749         qos_rga_w: qos@ffab0080 {
 750                 compatible = "syscon";
 751                 reg = <0x0 0xffab0080 0x0 0x20>;
 752         };
 753
 754         qos_video_m0: qos@ffab8000 {
 755                 compatible = "syscon";
 756                 reg = <0x0 0xffab8000 0x0 0x20>;
 757         };
 758
 759         qos_video_m1_r: qos@ffac0000 {
 760                 compatible = "syscon";
 761                 reg = <0x0 0xffac0000 0x0 0x20>;
 762         };
 763
 764         qos_video_m1_w: qos@ffac0080 {
 765                 compatible = "syscon";
 766                 reg = <0x0 0xffac0080 0x0 0x20>;
 767         };
 768
 769         qos_vop_big_r: qos@ffac8000 {
 770                 compatible = "syscon";
 771                 reg = <0x0 0xffac8000 0x0 0x20>;
 772         };
 773
 774         qos_vop_big_w: qos@ffac8080 {
 775                 compatible = "syscon";
 776                 reg = <0x0 0xffac8080 0x0 0x20>;
 777         };
 778
 779         qos_vop_little: qos@ffad0000 {
 780                 compatible = "syscon";
 781                 reg = <0x0 0xffad0000 0x0 0x20>;
 782         };
 783
 784         qos_gpu: qos@ffae0000 {
 785                 compatible = "syscon";
 786                 reg = <0x0 0xffae0000 0x0 0x20>;
 787         };
 788
 789         pmu: power-management@ff310000 {
 790                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 791                 reg = <0x0 0xff310000 0x0 0x1000>;
 792
 793                 /*
 794                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 795                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 796                  * Some of the power domains are grouped together for every
 797                  * voltage domain.
 798                  * The detail contents as below.
 799                  */
 800                 power: power-controller {
 801                         compatible = "rockchip,rk3399-power-controller";
 802                         #power-domain-cells = <1>;
 803                         #address-cells = <1>;
 804                         #size-cells = <0>;
 805
 806                         /* These power domains are grouped by VD_CENTER */
 807                         pd_iep@RK3399_PD_IEP {
 808                                 reg = <RK3399_PD_IEP>;
 809                                 clocks = <&cru ACLK_IEP>,
 810                                          <&cru HCLK_IEP>;
 811                                 pm_qos = <&qos_iep>;
 812                         };
 813                         pd_rga@RK3399_PD_RGA {
 814                                 reg = <RK3399_PD_RGA>;
 815                                 clocks = <&cru ACLK_RGA>,
 816                                          <&cru HCLK_RGA>;
 817                                 pm_qos = <&qos_rga_r>,
 818                                          <&qos_rga_w>;
 819                         };
 820                         pd_vcodec@RK3399_PD_VCODEC {
 821                                 reg = <RK3399_PD_VCODEC>;
 822                                 clocks = <&cru ACLK_VCODEC>,
 823                                          <&cru HCLK_VCODEC>;
 824                                 pm_qos = <&qos_video_m0>;
 825                         };
 826                         pd_vdu@RK3399_PD_VDU {
 827                                 reg = <RK3399_PD_VDU>;
 828                                 clocks = <&cru ACLK_VDU>,
 829                                          <&cru HCLK_VDU>;
 830                                 pm_qos = <&qos_video_m1_r>,
 831                                          <&qos_video_m1_w>;
 832                         };
 833
 834                         /* These power domains are grouped by VD_GPU */
 835                         pd_gpu@RK3399_PD_GPU {
 836                                 reg = <RK3399_PD_GPU>;
 837                                 clocks = <&cru ACLK_GPU>;
 838                                 pm_qos = <&qos_gpu>;
 839                         };
 840
 841                         /* These power domains are grouped by VD_LOGIC */
 842                         pd_emmc@RK3399_PD_EMMC {
 843                                 reg = <RK3399_PD_EMMC>;
 844                                 clocks = <&cru ACLK_EMMC>;
 845                                 pm_qos = <&qos_emmc>;
 846                         };
 847                         pd_gmac@RK3399_PD_GMAC {
 848                                 reg = <RK3399_PD_GMAC>;
 849                                 clocks = <&cru ACLK_GMAC>,
 850                                          <&cru PCLK_GMAC>;
 851                                 pm_qos = <&qos_gmac>;
 852                         };
 853                         pd_sd@RK3399_PD_SD {
 854                                 reg = <RK3399_PD_SD>;
 855                                 clocks = <&cru HCLK_SDMMC>,
 856                                          <&cru SCLK_SDMMC>;
 857                                 pm_qos = <&qos_sd>;
 858                         };
 859                         pd_vio@RK3399_PD_VIO {
 860                                 reg = <RK3399_PD_VIO>;
 861                                 #address-cells = <1>;
 862                                 #size-cells = <0>;
 863
 864                                 pd_hdcp@RK3399_PD_HDCP {
 865                                         reg = <RK3399_PD_HDCP>;
 866                                         clocks = <&cru ACLK_HDCP>,
 867                                                  <&cru HCLK_HDCP>,
 868                                                  <&cru PCLK_HDCP>;
 869                                         pm_qos = <&qos_hdcp>;
 870                                 };
 871                                 pd_isp0@RK3399_PD_ISP0 {
 872                                         reg = <RK3399_PD_ISP0>;
 873                                         clocks = <&cru ACLK_ISP0>,
 874                                                  <&cru HCLK_ISP0>;
 875                                         pm_qos = <&qos_isp0_m0>,
 876                                                  <&qos_isp0_m1>;
 877                                 };
 878                                 pd_isp1@RK3399_PD_ISP1 {
 879                                         reg = <RK3399_PD_ISP1>;
 880                                         clocks = <&cru ACLK_ISP1>,
 881                                                  <&cru HCLK_ISP1>;
 882                                         pm_qos = <&qos_isp1_m0>,
 883                                                  <&qos_isp1_m1>;
 884                                 };
 885                                 pd_tcpc0@RK3399_PD_TCPC0 {
 886                                         reg = <RK3399_PD_TCPD0>;
 887                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
 888                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
 889                                 };
 890                                 pd_tcpc1@RK3399_PD_TCPC1 {
 891                                         reg = <RK3399_PD_TCPD1>;
 892                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
 893                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
 894                                 };
 895                                 pd_vo@RK3399_PD_VO {
 896                                         reg = <RK3399_PD_VO>;
 897                                         #address-cells = <1>;
 898                                         #size-cells = <0>;
 899
 900                                         pd_vopb@RK3399_PD_VOPB {
 901                                                 reg = <RK3399_PD_VOPB>;
 902                                                 clocks = <&cru ACLK_VOP0>,
 903                                                          <&cru HCLK_VOP0>;
 904                                                 pm_qos = <&qos_vop_big_r>,
 905                                                          <&qos_vop_big_w>;
 906                                         };
 907                                         pd_vopl@RK3399_PD_VOPL {
 908                                                 reg = <RK3399_PD_VOPL>;
 909                                                 clocks = <&cru ACLK_VOP1>,
 910                                                          <&cru HCLK_VOP1>;
 911                                                 pm_qos = <&qos_vop_little>;
 912                                         };
 913                                 };
 914                         };
 915                 };
 916         };
 917
 918         pmugrf: syscon@ff320000 {
 919                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 920                 reg = <0x0 0xff320000 0x0 0x1000>;
 921                 #address-cells = <1>;
 922                 #size-cells = <1>;
 923
 924                 pmu_io_domains: io-domains {
 925                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 926                         status = "disabled";
 927                 };
 928         };
 929
 930         spi3: spi@ff350000 {
 931                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 932                 reg = <0x0 0xff350000 0x0 0x1000>;
 933                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 934                 clock-names = "spiclk", "apb_pclk";
 935                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
 936                 pinctrl-names = "default";
 937                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 938                 #address-cells = <1>;
 939                 #size-cells = <0>;
 940                 status = "disabled";
 941         };
 942
 943         uart4: serial@ff370000 {
 944                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 945                 reg = <0x0 0xff370000 0x0 0x100>;
 946                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 947                 clock-names = "baudclk", "apb_pclk";
 948                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
 949                 reg-shift = <2>;
 950                 reg-io-width = <4>;
 951                 pinctrl-names = "default";
 952                 pinctrl-0 = <&uart4_xfer>;
 953                 status = "disabled";
 954         };
 955
 956         i2c0: i2c@ff3c0000 {
 957                 compatible = "rockchip,rk3399-i2c";
 958                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 959                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
 960                 assigned-clock-rates = <200000000>;
 961                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 962                 clock-names = "i2c", "pclk";
 963                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 964                 pinctrl-names = "default";
 965                 pinctrl-0 = <&i2c0_xfer>;
 966                 #address-cells = <1>;
 967                 #size-cells = <0>;
 968                 status = "disabled";
 969         };
 970
 971         i2c4: i2c@ff3d0000 {
 972                 compatible = "rockchip,rk3399-i2c";
 973                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 974                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
 975                 assigned-clock-rates = <200000000>;
 976                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 977                 clock-names = "i2c", "pclk";
 978                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
 979                 pinctrl-names = "default";
 980                 pinctrl-0 = <&i2c4_xfer>;
 981                 #address-cells = <1>;
 982                 #size-cells = <0>;
 983                 status = "disabled";
 984         };
 985
 986         i2c8: i2c@ff3e0000 {
 987                 compatible = "rockchip,rk3399-i2c";
 988                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 989                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
 990                 assigned-clock-rates = <200000000>;
 991                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 992                 clock-names = "i2c", "pclk";
 993                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
 994                 pinctrl-names = "default";
 995                 pinctrl-0 = <&i2c8_xfer>;
 996                 #address-cells = <1>;
 997                 #size-cells = <0>;
 998                 status = "disabled";
 999         };
1000
1001         pwm0: pwm@ff420000 {
1002                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1003                 reg = <0x0 0xff420000 0x0 0x10>;
1004                 #pwm-cells = <3>;
1005                 pinctrl-names = "default";
1006                 pinctrl-0 = <&pwm0_pin>;
1007                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1008                 clock-names = "pwm";
1009                 status = "disabled";
1010         };
1011
1012         pwm1: pwm@ff420010 {
1013                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1014                 reg = <0x0 0xff420010 0x0 0x10>;
1015                 #pwm-cells = <3>;
1016                 pinctrl-names = "default";
1017                 pinctrl-0 = <&pwm1_pin>;
1018                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1019                 clock-names = "pwm";
1020                 status = "disabled";
1021         };
1022
1023         pwm2: pwm@ff420020 {
1024                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1025                 reg = <0x0 0xff420020 0x0 0x10>;
1026                 #pwm-cells = <3>;
1027                 pinctrl-names = "default";
1028                 pinctrl-0 = <&pwm2_pin>;
1029                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1030                 clock-names = "pwm";
1031                 status = "disabled";
1032         };
1033
1034         pwm3: pwm@ff420030 {
1035                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1036                 reg = <0x0 0xff420030 0x0 0x10>;
1037                 #pwm-cells = <3>;
1038                 pinctrl-names = "default";
1039                 pinctrl-0 = <&pwm3a_pin>;
1040                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1041                 clock-names = "pwm";
1042                 status = "disabled";
1043         };
1044
1045         efuse0: efuse@ff690000 {
1046                 compatible = "rockchip,rk3399-efuse";
1047                 reg = <0x0 0xff690000 0x0 0x80>;
1048                 #address-cells = <1>;
1049                 #size-cells = <1>;
1050                 clocks = <&cru PCLK_EFUSE1024NS>;
1051                 clock-names = "pclk_efuse";
1052
1053                 /* Data cells */
1054                 cpu_id: cpu-id@7 {
1055                         reg = <0x07 0x10>;
1056                 };
1057                 cpub_leakage: cpu-leakage@17 {
1058                         reg = <0x17 0x1>;
1059                 };
1060                 gpu_leakage: gpu-leakage@18 {
1061                         reg = <0x18 0x1>;
1062                 };
1063                 center_leakage: center-leakage@19 {
1064                         reg = <0x19 0x1>;
1065                 };
1066                 cpul_leakage: cpu-leakage@1a {
1067                         reg = <0x1a 0x1>;
1068                 };
1069                 logic_leakage: logic-leakage@1b {
1070                         reg = <0x1b 0x1>;
1071                 };
1072                 wafer_info: wafer-info@1c {
1073                         reg = <0x1c 0x1>;
1074                 };
1075         };
1076
1077         pmucru: pmu-clock-controller@ff750000 {
1078                 compatible = "rockchip,rk3399-pmucru";
1079                 reg = <0x0 0xff750000 0x0 0x1000>;
1080                 #clock-cells = <1>;
1081                 #reset-cells = <1>;
1082                 assigned-clocks = <&pmucru PLL_PPLL>;
1083                 assigned-clock-rates = <676000000>;
1084         };
1085
1086         cru: clock-controller@ff760000 {
1087                 compatible = "rockchip,rk3399-cru";
1088                 reg = <0x0 0xff760000 0x0 0x1000>;
1089                 #clock-cells = <1>;
1090                 #reset-cells = <1>;
1091                 assigned-clocks =
1092                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1093                         <&cru PLL_NPLL>,
1094                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1095                         <&cru PCLK_PERIHP>,
1096                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1097                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1098                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1099                 assigned-clock-rates =
1100                          <594000000>,  <800000000>,
1101                         <1000000000>,
1102                          <150000000>,   <75000000>,
1103                           <37500000>,
1104                          <100000000>,  <100000000>,
1105                           <50000000>, <600000000>,
1106                          <100000000>,   <50000000>;
1107         };
1108
1109         grf: syscon@ff770000 {
1110                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1111                 reg = <0x0 0xff770000 0x0 0x10000>;
1112                 #address-cells = <1>;
1113                 #size-cells = <1>;
1114
1115                 io_domains: io-domains {
1116                         compatible = "rockchip,rk3399-io-voltage-domain";
1117                         status = "disabled";
1118                 };
1119
1120                 u2phy0: usb2-phy@e450 {
1121                         compatible = "rockchip,rk3399-usb2phy";
1122                         reg = <0xe450 0x10>;
1123                         clocks = <&cru SCLK_USB2PHY0_REF>;
1124                         clock-names = "phyclk";
1125                         #clock-cells = <0>;
1126                         clock-output-names = "clk_usbphy0_480m";
1127                         status = "disabled";
1128
1129                         u2phy0_host: host-port {
1130                                 #phy-cells = <0>;
1131                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1132                                 interrupt-names = "linestate";
1133                                 status = "disabled";
1134                         };
1135
1136                         u2phy0_otg: otg-port {
1137                                 #phy-cells = <0>;
1138                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1139                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1140                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1141                                 interrupt-names = "otg-bvalid", "otg-id",
1142                                                   "linestate";
1143                                 status = "disabled";
1144                         };
1145                 };
1146
1147                 u2phy1: usb2-phy@e460 {
1148                         compatible = "rockchip,rk3399-usb2phy";
1149                         reg = <0xe460 0x10>;
1150                         clocks = <&cru SCLK_USB2PHY1_REF>;
1151                         clock-names = "phyclk";
1152                         #clock-cells = <0>;
1153                         clock-output-names = "clk_usbphy1_480m";
1154                         status = "disabled";
1155
1156                         u2phy1_host: host-port {
1157                                 #phy-cells = <0>;
1158                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1159                                 interrupt-names = "linestate";
1160                                 status = "disabled";
1161                         };
1162
1163                         u2phy1_otg: otg-port {
1164                                 #phy-cells = <0>;
1165                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1166                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1167                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1168                                 interrupt-names = "otg-bvalid", "otg-id",
1169                                                   "linestate";
1170                                 status = "disabled";
1171                         };
1172                 };
1173
1174                 emmc_phy: phy@f780 {
1175                         compatible = "rockchip,rk3399-emmc-phy";
1176                         reg = <0xf780 0x24>;
1177                         clocks = <&sdhci>;
1178                         clock-names = "emmcclk";
1179                         #phy-cells = <0>;
1180                         status = "disabled";
1181                 };
1182
1183                 pcie_phy: pcie-phy {
1184                         compatible = "rockchip,rk3399-pcie-phy";
1185                         clocks = <&cru SCLK_PCIEPHY_REF>;
1186                         clock-names = "refclk";
1187                         #phy-cells = <0>;
1188                         resets = <&cru SRST_PCIEPHY>;
1189                         reset-names = "phy";
1190                         status = "disabled";
1191                 };
1192         };
1193
1194         tcphy0: phy@ff7c0000 {
1195                 compatible = "rockchip,rk3399-typec-phy";
1196                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1197                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1198                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1199                 clock-names = "tcpdcore", "tcpdphy-ref";
1200                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1201                 assigned-clock-rates = <50000000>;
1202                 power-domains = <&power RK3399_PD_TCPD0>;
1203                 resets = <&cru SRST_UPHY0>,
1204                          <&cru SRST_UPHY0_PIPE_L00>,
1205                          <&cru SRST_P_UPHY0_TCPHY>;
1206                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1207                 rockchip,grf = <&grf>;
1208                 rockchip,typec-conn-dir = <0xe580 0 16>;
1209                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1210                 rockchip,external-psm = <0xe588 14 30>;
1211                 rockchip,pipe-status = <0xe5c0 0 0>;
1212                 status = "disabled";
1213
1214                 tcphy0_dp: dp-port {
1215                         #phy-cells = <0>;
1216                 };
1217
1218                 tcphy0_usb3: usb3-port {
1219                         #phy-cells = <0>;
1220                 };
1221         };
1222
1223         tcphy1: phy@ff800000 {
1224                 compatible = "rockchip,rk3399-typec-phy";
1225                 reg = <0x0 0xff800000 0x0 0x40000>;
1226                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1227                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1228                 clock-names = "tcpdcore", "tcpdphy-ref";
1229                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1230                 assigned-clock-rates = <50000000>;
1231                 power-domains = <&power RK3399_PD_TCPD1>;
1232                 resets = <&cru SRST_UPHY1>,
1233                          <&cru SRST_UPHY1_PIPE_L00>,
1234                          <&cru SRST_P_UPHY1_TCPHY>;
1235                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1236                 rockchip,grf = <&grf>;
1237                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1238                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1239                 rockchip,external-psm = <0xe594 14 30>;
1240                 rockchip,pipe-status = <0xe5c0 16 16>;
1241                 status = "disabled";
1242
1243                 tcphy1_dp: dp-port {
1244                         #phy-cells = <0>;
1245                 };
1246
1247                 tcphy1_usb3: usb3-port {
1248                         #phy-cells = <0>;
1249                 };
1250         };
1251
1252         watchdog@ff848000 {
1253                 compatible = "snps,dw-wdt";
1254                 reg = <0x0 0xff848000 0x0 0x100>;
1255                 clocks = <&cru PCLK_WDT>;
1256                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1257         };
1258
1259         rktimer: rktimer@ff850000 {
1260                 compatible = "rockchip,rk3399-timer";
1261                 reg = <0x0 0xff850000 0x0 0x1000>;
1262                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1263                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1264                 clock-names = "pclk", "timer";
1265         };
1266
1267         spdif: spdif@ff870000 {
1268                 compatible = "rockchip,rk3399-spdif";
1269                 reg = <0x0 0xff870000 0x0 0x1000>;
1270                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1271                 dmas = <&dmac_bus 7>;
1272                 dma-names = "tx";
1273                 clock-names = "mclk", "hclk";
1274                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1275                 pinctrl-names = "default";
1276                 pinctrl-0 = <&spdif_bus>;
1277                 status = "disabled";
1278         };
1279
1280         i2s0: i2s@ff880000 {
1281                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1282                 reg = <0x0 0xff880000 0x0 0x1000>;
1283                 rockchip,grf = <&grf>;
1284                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1285                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1286                 dma-names = "tx", "rx";
1287                 clock-names = "i2s_clk", "i2s_hclk";
1288                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1289                 pinctrl-names = "default";
1290                 pinctrl-0 = <&i2s0_8ch_bus>;
1291                 status = "disabled";
1292         };
1293
1294         i2s1: i2s@ff890000 {
1295                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1296                 reg = <0x0 0xff890000 0x0 0x1000>;
1297                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1298                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1299                 dma-names = "tx", "rx";
1300                 clock-names = "i2s_clk", "i2s_hclk";
1301                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1302                 pinctrl-names = "default";
1303                 pinctrl-0 = <&i2s1_2ch_bus>;
1304                 status = "disabled";
1305         };
1306
1307         i2s2: i2s@ff8a0000 {
1308                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1309                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1310                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1311                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1312                 dma-names = "tx", "rx";
1313                 clock-names = "i2s_clk", "i2s_hclk";
1314                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1315                 status = "disabled";
1316         };
1317
1318         pinctrl: pinctrl {
1319                 compatible = "rockchip,rk3399-pinctrl";
1320                 rockchip,grf = <&grf>;
1321                 rockchip,pmu = <&pmugrf>;
1322                 #address-cells = <2>;
1323                 #size-cells = <2>;
1324                 ranges;
1325
1326                 gpio0: gpio0@ff720000 {
1327                         compatible = "rockchip,gpio-bank";
1328                         reg = <0x0 0xff720000 0x0 0x100>;
1329                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1330                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1331
1332                         gpio-controller;
1333                         #gpio-cells = <0x2>;
1334
1335                         interrupt-controller;
1336                         #interrupt-cells = <0x2>;
1337                 };
1338
1339                 gpio1: gpio1@ff730000 {
1340                         compatible = "rockchip,gpio-bank";
1341                         reg = <0x0 0xff730000 0x0 0x100>;
1342                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1343                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1344
1345                         gpio-controller;
1346                         #gpio-cells = <0x2>;
1347
1348                         interrupt-controller;
1349                         #interrupt-cells = <0x2>;
1350                 };
1351
1352                 gpio2: gpio2@ff780000 {
1353                         compatible = "rockchip,gpio-bank";
1354                         reg = <0x0 0xff780000 0x0 0x100>;
1355                         clocks = <&cru PCLK_GPIO2>;
1356                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1357
1358                         gpio-controller;
1359                         #gpio-cells = <0x2>;
1360
1361                         interrupt-controller;
1362                         #interrupt-cells = <0x2>;
1363                 };
1364
1365                 gpio3: gpio3@ff788000 {
1366                         compatible = "rockchip,gpio-bank";
1367                         reg = <0x0 0xff788000 0x0 0x100>;
1368                         clocks = <&cru PCLK_GPIO3>;
1369                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1370
1371                         gpio-controller;
1372                         #gpio-cells = <0x2>;
1373
1374                         interrupt-controller;
1375                         #interrupt-cells = <0x2>;
1376                 };
1377
1378                 gpio4: gpio4@ff790000 {
1379                         compatible = "rockchip,gpio-bank";
1380                         reg = <0x0 0xff790000 0x0 0x100>;
1381                         clocks = <&cru PCLK_GPIO4>;
1382                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1383
1384                         gpio-controller;
1385                         #gpio-cells = <0x2>;
1386
1387                         interrupt-controller;
1388                         #interrupt-cells = <0x2>;
1389                 };
1390
1391                 pcfg_pull_up: pcfg-pull-up {
1392                         bias-pull-up;
1393                 };
1394
1395                 pcfg_pull_down: pcfg-pull-down {
1396                         bias-pull-down;
1397                 };
1398
1399                 pcfg_pull_none: pcfg-pull-none {
1400                         bias-disable;
1401                 };
1402
1403                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1404                         bias-disable;
1405                         drive-strength = <12>;
1406                 };
1407
1408                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1409                         bias-pull-up;
1410                         drive-strength = <8>;
1411                 };
1412
1413                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1414                         bias-pull-down;
1415                         drive-strength = <4>;
1416                 };
1417
1418                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1419                         bias-pull-up;
1420                         drive-strength = <2>;
1421                 };
1422
1423                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1424                         bias-pull-down;
1425                         drive-strength = <12>;
1426                 };
1427
1428                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1429                         bias-disable;
1430                         drive-strength = <13>;
1431                 };
1432
1433                 clock {
1434                         clk_32k: clk-32k {
1435                                 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
1436                         };
1437                 };
1438
1439                 gmac {
1440                         rgmii_pins: rgmii-pins {
1441                                 rockchip,pins =
1442                                         /* mac_txclk */
1443                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1444                                         /* mac_rxclk */
1445                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1446                                         /* mac_mdio */
1447                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1448                                         /* mac_txen */
1449                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1450                                         /* mac_clk */
1451                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1452                                         /* mac_rxdv */
1453                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1454                                         /* mac_mdc */
1455                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1456                                         /* mac_rxd1 */
1457                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1458                                         /* mac_rxd0 */
1459                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1460                                         /* mac_txd1 */
1461                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1462                                         /* mac_txd0 */
1463                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1464                                         /* mac_rxd3 */
1465                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1466                                         /* mac_rxd2 */
1467                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1468                                         /* mac_txd3 */
1469                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1470                                         /* mac_txd2 */
1471                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1472                         };
1473
1474                         rmii_pins: rmii-pins {
1475                                 rockchip,pins =
1476                                         /* mac_mdio */
1477                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1478                                         /* mac_txen */
1479                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1480                                         /* mac_clk */
1481                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1482                                         /* mac_rxer */
1483                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1484                                         /* mac_rxdv */
1485                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1486                                         /* mac_mdc */
1487                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1488                                         /* mac_rxd1 */
1489                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1490                                         /* mac_rxd0 */
1491                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1492                                         /* mac_txd1 */
1493                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1494                                         /* mac_txd0 */
1495                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1496                         };
1497                 };
1498
1499                 i2c0 {
1500                         i2c0_xfer: i2c0-xfer {
1501                                 rockchip,pins =
1502                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1503                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1504                         };
1505                 };
1506
1507                 i2c1 {
1508                         i2c1_xfer: i2c1-xfer {
1509                                 rockchip,pins =
1510                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1511                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1512                         };
1513                 };
1514
1515                 i2c2 {
1516                         i2c2_xfer: i2c2-xfer {
1517                                 rockchip,pins =
1518                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1519                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1520                         };
1521                 };
1522
1523                 i2c3 {
1524                         i2c3_xfer: i2c3-xfer {
1525                                 rockchip,pins =
1526                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1527                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1528                         };
1529                 };
1530
1531                 i2c4 {
1532                         i2c4_xfer: i2c4-xfer {
1533                                 rockchip,pins =
1534                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1535                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1536                         };
1537                 };
1538
1539                 i2c5 {
1540                         i2c5_xfer: i2c5-xfer {
1541                                 rockchip,pins =
1542                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1543                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1544                         };
1545                 };
1546
1547                 i2c6 {
1548                         i2c6_xfer: i2c6-xfer {
1549                                 rockchip,pins =
1550                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1551                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1552                         };
1553                 };
1554
1555                 i2c7 {
1556                         i2c7_xfer: i2c7-xfer {
1557                                 rockchip,pins =
1558                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1559                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1560                         };
1561                 };
1562
1563                 i2c8 {
1564                         i2c8_xfer: i2c8-xfer {
1565                                 rockchip,pins =
1566                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1567                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1568                         };
1569                 };
1570
1571                 i2s0 {
1572                         i2s0_8ch_bus: i2s0-8ch-bus {
1573                                 rockchip,pins =
1574                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1575                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1576                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1577                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1578                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1579                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1580                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1581                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1582                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1583                         };
1584                 };
1585
1586                 i2s1 {
1587                         i2s1_2ch_bus: i2s1-2ch-bus {
1588                                 rockchip,pins =
1589                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1590                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1591                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1592                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1593                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1594                         };
1595                 };
1596
1597                 sleep {
1598                         ap_pwroff: ap-pwroff {
1599                                 rockchip,pins = <1 5 RK_FUNC_1 &pcfg_pull_none>;
1600                         };
1601
1602                         ddrio_pwroff: ddrio-pwroff {
1603                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1604                         };
1605                 };
1606
1607                 spdif {
1608                         spdif_bus: spdif-bus {
1609                                 rockchip,pins =
1610                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1611                         };
1612                 };
1613
1614                 spi0 {
1615                         spi0_clk: spi0-clk {
1616                                 rockchip,pins =
1617                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1618                         };
1619                         spi0_cs0: spi0-cs0 {
1620                                 rockchip,pins =
1621                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1622                         };
1623                         spi0_cs1: spi0-cs1 {
1624                                 rockchip,pins =
1625                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1626                         };
1627                         spi0_tx: spi0-tx {
1628                                 rockchip,pins =
1629                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1630                         };
1631                         spi0_rx: spi0-rx {
1632                                 rockchip,pins =
1633                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1634                         };
1635                 };
1636
1637                 spi1 {
1638                         spi1_clk: spi1-clk {
1639                                 rockchip,pins =
1640                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1641                         };
1642                         spi1_cs0: spi1-cs0 {
1643                                 rockchip,pins =
1644                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1645                         };
1646                         spi1_rx: spi1-rx {
1647                                 rockchip,pins =
1648                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1649                         };
1650                         spi1_tx: spi1-tx {
1651                                 rockchip,pins =
1652                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1653                         };
1654                 };
1655
1656                 spi2 {
1657                         spi2_clk: spi2-clk {
1658                                 rockchip,pins =
1659                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1660                         };
1661                         spi2_cs0: spi2-cs0 {
1662                                 rockchip,pins =
1663                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1664                         };
1665                         spi2_rx: spi2-rx {
1666                                 rockchip,pins =
1667                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1668                         };
1669                         spi2_tx: spi2-tx {
1670                                 rockchip,pins =
1671                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1672                         };
1673                 };
1674
1675                 spi3 {
1676                         spi3_clk: spi3-clk {
1677                                 rockchip,pins =
1678                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1679                         };
1680                         spi3_cs0: spi3-cs0 {
1681                                 rockchip,pins =
1682                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1683                         };
1684                         spi3_rx: spi3-rx {
1685                                 rockchip,pins =
1686                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1687                         };
1688                         spi3_tx: spi3-tx {
1689                                 rockchip,pins =
1690                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1691                         };
1692                 };
1693
1694                 spi4 {
1695                         spi4_clk: spi4-clk {
1696                                 rockchip,pins =
1697                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1698                         };
1699                         spi4_cs0: spi4-cs0 {
1700                                 rockchip,pins =
1701                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1702                         };
1703                         spi4_rx: spi4-rx {
1704                                 rockchip,pins =
1705                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1706                         };
1707                         spi4_tx: spi4-tx {
1708                                 rockchip,pins =
1709                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1710                         };
1711                 };
1712
1713                 spi5 {
1714                         spi5_clk: spi5-clk {
1715                                 rockchip,pins =
1716                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1717                         };
1718                         spi5_cs0: spi5-cs0 {
1719                                 rockchip,pins =
1720                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1721                         };
1722                         spi5_rx: spi5-rx {
1723                                 rockchip,pins =
1724                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1725                         };
1726                         spi5_tx: spi5-tx {
1727                                 rockchip,pins =
1728                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1729                         };
1730                 };
1731
1732                 tsadc {
1733                         otp_gpio: otp-gpio {
1734                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1735                         };
1736
1737                         otp_out: otp-out {
1738                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1739                         };
1740                 };
1741
1742                 uart0 {
1743                         uart0_xfer: uart0-xfer {
1744                                 rockchip,pins =
1745                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1746                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1747                         };
1748
1749                         uart0_cts: uart0-cts {
1750                                 rockchip,pins =
1751                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1752                         };
1753
1754                         uart0_rts: uart0-rts {
1755                                 rockchip,pins =
1756                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1757                         };
1758                 };
1759
1760                 uart1 {
1761                         uart1_xfer: uart1-xfer {
1762                                 rockchip,pins =
1763                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1764                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1765                         };
1766                 };
1767
1768                 uart2a {
1769                         uart2a_xfer: uart2a-xfer {
1770                                 rockchip,pins =
1771                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1772                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1773                         };
1774                 };
1775
1776                 uart2b {
1777                         uart2b_xfer: uart2b-xfer {
1778                                 rockchip,pins =
1779                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1780                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1781                         };
1782                 };
1783
1784                 uart2c {
1785                         uart2c_xfer: uart2c-xfer {
1786                                 rockchip,pins =
1787                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1788                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1789                         };
1790                 };
1791
1792                 uart3 {
1793                         uart3_xfer: uart3-xfer {
1794                                 rockchip,pins =
1795                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1796                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1797                         };
1798
1799                         uart3_cts: uart3-cts {
1800                                 rockchip,pins =
1801                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1802                         };
1803
1804                         uart3_rts: uart3-rts {
1805                                 rockchip,pins =
1806                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1807                         };
1808                 };
1809
1810                 uart4 {
1811                         uart4_xfer: uart4-xfer {
1812                                 rockchip,pins =
1813                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1814                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1815                         };
1816                 };
1817
1818                 uarthdcp {
1819                         uarthdcp_xfer: uarthdcp-xfer {
1820                                 rockchip,pins =
1821                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1822                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1823                         };
1824                 };
1825
1826                 pwm0 {
1827                         pwm0_pin: pwm0-pin {
1828                                 rockchip,pins =
1829                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1830                         };
1831
1832                         vop0_pwm_pin: vop0-pwm-pin {
1833                                 rockchip,pins =
1834                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1835                         };
1836                 };
1837
1838                 pwm1 {
1839                         pwm1_pin: pwm1-pin {
1840                                 rockchip,pins =
1841                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1842                         };
1843
1844                         vop1_pwm_pin: vop1-pwm-pin {
1845                                 rockchip,pins =
1846                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1847                         };
1848                 };
1849
1850                 pwm2 {
1851                         pwm2_pin: pwm2-pin {
1852                                 rockchip,pins =
1853                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1854                         };
1855                 };
1856
1857                 pwm3a {
1858                         pwm3a_pin: pwm3a-pin {
1859                                 rockchip,pins =
1860                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1861                         };
1862                 };
1863
1864                 pwm3b {
1865                         pwm3b_pin: pwm3b-pin {
1866                                 rockchip,pins =
1867                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1868                         };
1869                 };
1870
1871                 pcie {
1872                         pcie_clkreqn: pci-clkreqn {
1873                                 rockchip,pins =
1874                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
1875                         };
1876
1877                         pcie_clkreqnb: pci-clkreqnb {
1878                                 rockchip,pins =
1879                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1880                         };
1881                 };
1882
1883         };
1884 };