arch/arm64/boot/dts/mediatek/mt8173.dtsi

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: Eddie Huang <eddie.huang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/clock/mt8173-clk.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/power/mt8173-power.h>
  18 #include <dt-bindings/reset-controller/mt8173-resets.h>
  19 #include "mt8173-pinfunc.h"
  20
  21 / {
  22         compatible = "mediatek,mt8173";
  23         interrupt-parent = <&sysirq>;
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu-map {
  32                         cluster0 {
  33                                 core0 {
  34                                         cpu = <&cpu0>;
  35                                 };
  36                                 core1 {
  37                                         cpu = <&cpu1>;
  38                                 };
  39                         };
  40
  41                         cluster1 {
  42                                 core0 {
  43                                         cpu = <&cpu2>;
  44                                 };
  45                                 core1 {
  46                                         cpu = <&cpu3>;
  47                                 };
  48                         };
  49                 };
  50
  51                 cpu0: cpu@0 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a53";
  54                         reg = <0x000>;
  55                         enable-method = "psci";
  56                         cpu-idle-states = <&CPU_SLEEP_0>;
  57                         #cooling-cells = <2>;
  58                 };
  59
  60                 cpu1: cpu@1 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53";
  63                         reg = <0x001>;
  64                         enable-method = "psci";
  65                         cpu-idle-states = <&CPU_SLEEP_0>;
  66                 };
  67
  68                 cpu2: cpu@100 {
  69                         device_type = "cpu";
  70                         compatible = "arm,cortex-a57";
  71                         reg = <0x100>;
  72                         enable-method = "psci";
  73                         cpu-idle-states = <&CPU_SLEEP_0>;
  74                         #cooling-cells = <2>;
  75                 };
  76
  77                 cpu3: cpu@101 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a57";
  80                         reg = <0x101>;
  81                         enable-method = "psci";
  82                         cpu-idle-states = <&CPU_SLEEP_0>;
  83                 };
  84
  85                 idle-states {
  86                         entry-method = "psci";
  87
  88                         CPU_SLEEP_0: cpu-sleep-0 {
  89                                 compatible = "arm,idle-state";
  90                                 local-timer-stop;
  91                                 entry-latency-us = <639>;
  92                                 exit-latency-us = <680>;
  93                                 min-residency-us = <1088>;
  94                                 arm,psci-suspend-param = <0x0010000>;
  95                         };
  96                 };
  97         };
  98
  99         psci {
 100                 compatible = "arm,psci";
 101                 method = "smc";
 102                 cpu_suspend   = <0x84000001>;
 103                 cpu_off       = <0x84000002>;
 104                 cpu_on        = <0x84000003>;
 105         };
 106
 107         clk26m: oscillator@0 {
 108                 compatible = "fixed-clock";
 109                 #clock-cells = <0>;
 110                 clock-frequency = <26000000>;
 111                 clock-output-names = "clk26m";
 112         };
 113
 114         clk32k: oscillator@1 {
 115                 compatible = "fixed-clock";
 116                 #clock-cells = <0>;
 117                 clock-frequency = <32000>;
 118                 clock-output-names = "clk32k";
 119         };
 120
 121         cpum_ck: oscillator@2 {
 122                 compatible = "fixed-clock";
 123                 #clock-cells = <0>;
 124                 clock-frequency = <0>;
 125                 clock-output-names = "cpum_ck";
 126         };
 127
 128         timer {
 129                 compatible = "arm,armv8-timer";
 130                 interrupt-parent = <&gic>;
 131                 interrupts = <GIC_PPI 13
 132                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 133                              <GIC_PPI 14
 134                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 135                              <GIC_PPI 11
 136                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 137                              <GIC_PPI 10
 138                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 139         };
 140
 141         soc {
 142                 #address-cells = <2>;
 143                 #size-cells = <2>;
 144                 compatible = "simple-bus";
 145                 ranges;
 146
 147                 topckgen: clock-controller@10000000 {
 148                         compatible = "mediatek,mt8173-topckgen";
 149                         reg = <0 0x10000000 0 0x1000>;
 150                         #clock-cells = <1>;
 151                 };
 152
 153                 infracfg: power-controller@10001000 {
 154                         compatible = "mediatek,mt8173-infracfg", "syscon";
 155                         reg = <0 0x10001000 0 0x1000>;
 156                         #clock-cells = <1>;
 157                         #reset-cells = <1>;
 158                 };
 159
 160                 pericfg: power-controller@10003000 {
 161                         compatible = "mediatek,mt8173-pericfg", "syscon";
 162                         reg = <0 0x10003000 0 0x1000>;
 163                         #clock-cells = <1>;
 164                         #reset-cells = <1>;
 165                 };
 166
 167                 syscfg_pctl_a: syscfg_pctl_a@10005000 {
 168                         compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
 169                         reg = <0 0x10005000 0 0x1000>;
 170                 };
 171
 172                 pio: pinctrl@0x10005000 {
 173                         compatible = "mediatek,mt8173-pinctrl";
 174                         reg = <0 0x1000b000 0 0x1000>;
 175                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
 176                         pins-are-numbered;
 177                         gpio-controller;
 178                         #gpio-cells = <2>;
 179                         interrupt-controller;
 180                         #interrupt-cells = <2>;
 181                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
 182                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 183                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 184
 185                         i2c0_pins_a: i2c0 {
 186                                 pins1 {
 187                                         pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
 188                                                  <MT8173_PIN_46_SCL0__FUNC_SCL0>;
 189                                         bias-disable;
 190                                 };
 191                         };
 192
 193                         i2c1_pins_a: i2c1 {
 194                                 pins1 {
 195                                         pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>,
 196                                                  <MT8173_PIN_126_SCL1__FUNC_SCL1>;
 197                                         bias-disable;
 198                                 };
 199                         };
 200
 201                         i2c2_pins_a: i2c2 {
 202                                 pins1 {
 203                                         pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>,
 204                                                  <MT8173_PIN_44_SCL2__FUNC_SCL2>;
 205                                         bias-disable;
 206                                 };
 207                         };
 208
 209                         i2c3_pins_a: i2c3 {
 210                                 pins1 {
 211                                         pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>,
 212                                                  <MT8173_PIN_107_SCL3__FUNC_SCL3>;
 213                                         bias-disable;
 214                                 };
 215                         };
 216
 217                         i2c4_pins_a: i2c4 {
 218                                 pins1 {
 219                                         pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>,
 220                                                  <MT8173_PIN_134_SCL4__FUNC_SCL4>;
 221                                         bias-disable;
 222                                 };
 223                         };
 224
 225                         i2c6_pins_a: i2c6 {
 226                                 pins1 {
 227                                         pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>,
 228                                                  <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>;
 229                                         bias-disable;
 230                                 };
 231                         };
 232                 };
 233
 234                 scpsys: scpsys@10006000 {
 235                         compatible = "mediatek,mt8173-scpsys";
 236                         #power-domain-cells = <1>;
 237                         reg = <0 0x10006000 0 0x1000>;
 238                         clocks = <&clk26m>,
 239                                  <&topckgen CLK_TOP_MM_SEL>,
 240                                  <&topckgen CLK_TOP_VENC_SEL>,
 241                                  <&topckgen CLK_TOP_VENC_LT_SEL>;
 242                         clock-names = "mfg", "mm", "venc", "venc_lt";
 243                         infracfg = <&infracfg>;
 244                 };
 245
 246                 watchdog: watchdog@10007000 {
 247                         compatible = "mediatek,mt8173-wdt",
 248                                      "mediatek,mt6589-wdt";
 249                         reg = <0 0x10007000 0 0x100>;
 250                 };
 251
 252                 pwrap: pwrap@1000d000 {
 253                         compatible = "mediatek,mt8173-pwrap";
 254                         reg = <0 0x1000d000 0 0x1000>;
 255                         reg-names = "pwrap";
 256                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 257                         resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
 258                         reset-names = "pwrap";
 259                         clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
 260                         clock-names = "spi", "wrap";
 261                 };
 262
 263                 sysirq: intpol-controller@10200620 {
 264                         compatible = "mediatek,mt8173-sysirq",
 265                                      "mediatek,mt6577-sysirq";
 266                         interrupt-controller;
 267                         #interrupt-cells = <3>;
 268                         interrupt-parent = <&gic>;
 269                         reg = <0 0x10200620 0 0x20>;
 270                 };
 271
 272                 apmixedsys: clock-controller@10209000 {
 273                         compatible = "mediatek,mt8173-apmixedsys";
 274                         reg = <0 0x10209000 0 0x1000>;
 275                         #clock-cells = <1>;
 276                 };
 277
 278                 gic: interrupt-controller@10220000 {
 279                         compatible = "arm,gic-400";
 280                         #interrupt-cells = <3>;
 281                         interrupt-parent = <&gic>;
 282                         interrupt-controller;
 283                         reg = <0 0x10221000 0 0x1000>,
 284                               <0 0x10222000 0 0x2000>,
 285                               <0 0x10224000 0 0x2000>,
 286                               <0 0x10226000 0 0x2000>;
 287                         interrupts = <GIC_PPI 9
 288                                 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 289                 };
 290
 291                 uart0: serial@11002000 {
 292                         compatible = "mediatek,mt8173-uart",
 293                                      "mediatek,mt6577-uart";
 294                         reg = <0 0x11002000 0 0x400>;
 295                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
 296                         clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
 297                         clock-names = "baud", "bus";
 298                         status = "disabled";
 299                 };
 300
 301                 uart1: serial@11003000 {
 302                         compatible = "mediatek,mt8173-uart",
 303                                      "mediatek,mt6577-uart";
 304                         reg = <0 0x11003000 0 0x400>;
 305                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
 306                         clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
 307                         clock-names = "baud", "bus";
 308                         status = "disabled";
 309                 };
 310
 311                 uart2: serial@11004000 {
 312                         compatible = "mediatek,mt8173-uart",
 313                                      "mediatek,mt6577-uart";
 314                         reg = <0 0x11004000 0 0x400>;
 315                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
 316                         clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
 317                         clock-names = "baud", "bus";
 318                         status = "disabled";
 319                 };
 320
 321                 uart3: serial@11005000 {
 322                         compatible = "mediatek,mt8173-uart",
 323                                      "mediatek,mt6577-uart";
 324                         reg = <0 0x11005000 0 0x400>;
 325                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
 326                         clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
 327                         clock-names = "baud", "bus";
 328                         status = "disabled";
 329                 };
 330
 331                 i2c0: i2c@11007000 {
 332                         compatible = "mediatek,mt8173-i2c";
 333                         reg = <0 0x11007000 0 0x70>,
 334                               <0 0x11000100 0 0x80>;
 335                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
 336                         clock-div = <16>;
 337                         clocks = <&pericfg CLK_PERI_I2C0>,
 338                                  <&pericfg CLK_PERI_AP_DMA>;
 339                         clock-names = "main", "dma";
 340                         pinctrl-names = "default";
 341                         pinctrl-0 = <&i2c0_pins_a>;
 342                         #address-cells = <1>;
 343                         #size-cells = <0>;
 344                         status = "disabled";
 345                 };
 346
 347                 i2c1: i2c@11008000 {
 348                         compatible = "mediatek,mt8173-i2c";
 349                         reg = <0 0x11008000 0 0x70>,
 350                               <0 0x11000180 0 0x80>;
 351                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 352                         clock-div = <16>;
 353                         clocks = <&pericfg CLK_PERI_I2C1>,
 354                                  <&pericfg CLK_PERI_AP_DMA>;
 355                         clock-names = "main", "dma";
 356                         pinctrl-names = "default";
 357                         pinctrl-0 = <&i2c1_pins_a>;
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         status = "disabled";
 361                 };
 362
 363                 i2c2: i2c@11009000 {
 364                         compatible = "mediatek,mt8173-i2c";
 365                         reg = <0 0x11009000 0 0x70>,
 366                               <0 0x11000200 0 0x80>;
 367                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
 368                         clock-div = <16>;
 369                         clocks = <&pericfg CLK_PERI_I2C2>,
 370                                  <&pericfg CLK_PERI_AP_DMA>;
 371                         clock-names = "main", "dma";
 372                         pinctrl-names = "default";
 373                         pinctrl-0 = <&i2c2_pins_a>;
 374                         #address-cells = <1>;
 375                         #size-cells = <0>;
 376                         status = "disabled";
 377                 };
 378
 379                 spi: spi@1100a000 {
 380                         compatible = "mediatek,mt8173-spi";
 381                         #address-cells = <1>;
 382                         #size-cells = <0>;
 383                         reg = <0 0x1100a000 0 0x1000>;
 384                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
 385                         clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
 386                                  <&topckgen CLK_TOP_SPI_SEL>,
 387                                  <&pericfg CLK_PERI_SPI0>;
 388                         clock-names = "parent-clk", "sel-clk", "spi-clk";
 389                         status = "disabled";
 390                 };
 391
 392                 i2c3: i2c@11010000 {
 393                         compatible = "mediatek,mt8173-i2c";
 394                         reg = <0 0x11010000 0 0x70>,
 395                               <0 0x11000280 0 0x80>;
 396                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 397                         clock-div = <16>;
 398                         clocks = <&pericfg CLK_PERI_I2C3>,
 399                                  <&pericfg CLK_PERI_AP_DMA>;
 400                         clock-names = "main", "dma";
 401                         pinctrl-names = "default";
 402                         pinctrl-0 = <&i2c3_pins_a>;
 403                         #address-cells = <1>;
 404                         #size-cells = <0>;
 405                         status = "disabled";
 406                 };
 407
 408                 i2c4: i2c@11011000 {
 409                         compatible = "mediatek,mt8173-i2c";
 410                         reg = <0 0x11011000 0 0x70>,
 411                               <0 0x11000300 0 0x80>;
 412                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 413                         clock-div = <16>;
 414                         clocks = <&pericfg CLK_PERI_I2C4>,
 415                                  <&pericfg CLK_PERI_AP_DMA>;
 416                         clock-names = "main", "dma";
 417                         pinctrl-names = "default";
 418                         pinctrl-0 = <&i2c4_pins_a>;
 419                         #address-cells = <1>;
 420                         #size-cells = <0>;
 421                         status = "disabled";
 422                 };
 423
 424                 i2c6: i2c@11013000 {
 425                         compatible = "mediatek,mt8173-i2c";
 426                         reg = <0 0x11013000 0 0x70>,
 427                               <0 0x11000080 0 0x80>;
 428                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
 429                         clock-div = <16>;
 430                         clocks = <&pericfg CLK_PERI_I2C6>,
 431                                  <&pericfg CLK_PERI_AP_DMA>;
 432                         clock-names = "main", "dma";
 433                         pinctrl-names = "default";
 434                         pinctrl-0 = <&i2c6_pins_a>;
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         status = "disabled";
 438                 };
 439
 440                 afe: audio-controller@11220000  {
 441                         compatible = "mediatek,mt8173-afe-pcm";
 442                         reg = <0 0x11220000 0 0x1000>;
 443                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>;
 444                         power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
 445                         clocks = <&infracfg CLK_INFRA_AUDIO>,
 446                                  <&topckgen CLK_TOP_AUDIO_SEL>,
 447                                  <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
 448                                  <&topckgen CLK_TOP_APLL1_DIV0>,
 449                                  <&topckgen CLK_TOP_APLL2_DIV0>,
 450                                  <&topckgen CLK_TOP_I2S0_M_SEL>,
 451                                  <&topckgen CLK_TOP_I2S1_M_SEL>,
 452                                  <&topckgen CLK_TOP_I2S2_M_SEL>,
 453                                  <&topckgen CLK_TOP_I2S3_M_SEL>,
 454                                  <&topckgen CLK_TOP_I2S3_B_SEL>;
 455                         clock-names = "infra_sys_audio_clk",
 456                                       "top_pdn_audio",
 457                                       "top_pdn_aud_intbus",
 458                                       "bck0",
 459                                       "bck1",
 460                                       "i2s0_m",
 461                                       "i2s1_m",
 462                                       "i2s2_m",
 463                                       "i2s3_m",
 464                                       "i2s3_b";
 465                         assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>,
 466                                           <&topckgen CLK_TOP_AUD_2_SEL>;
 467                         assigned-clock-parents = <&topckgen CLK_TOP_APLL1>,
 468                                                  <&topckgen CLK_TOP_APLL2>;
 469                 };
 470
 471                 mmc0: mmc@11230000 {
 472                         compatible = "mediatek,mt8173-mmc",
 473                                      "mediatek,mt8135-mmc";
 474                         reg = <0 0x11230000 0 0x1000>;
 475                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>;
 476                         clocks = <&pericfg CLK_PERI_MSDC30_0>,
 477                                  <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
 478                         clock-names = "source", "hclk";
 479                         status = "disabled";
 480                 };
 481
 482                 mmc1: mmc@11240000 {
 483                         compatible = "mediatek,mt8173-mmc",
 484                                      "mediatek,mt8135-mmc";
 485                         reg = <0 0x11240000 0 0x1000>;
 486                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
 487                         clocks = <&pericfg CLK_PERI_MSDC30_1>,
 488                                  <&topckgen CLK_TOP_AXI_SEL>;
 489                         clock-names = "source", "hclk";
 490                         status = "disabled";
 491                 };
 492
 493                 mmc2: mmc@11250000 {
 494                         compatible = "mediatek,mt8173-mmc",
 495                                      "mediatek,mt8135-mmc";
 496                         reg = <0 0x11250000 0 0x1000>;
 497                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
 498                         clocks = <&pericfg CLK_PERI_MSDC30_2>,
 499                                  <&topckgen CLK_TOP_AXI_SEL>;
 500                         clock-names = "source", "hclk";
 501                         status = "disabled";
 502                 };
 503
 504                 mmc3: mmc@11260000 {
 505                         compatible = "mediatek,mt8173-mmc",
 506                                      "mediatek,mt8135-mmc";
 507                         reg = <0 0x11260000 0 0x1000>;
 508                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
 509                         clocks = <&pericfg CLK_PERI_MSDC30_3>,
 510                                  <&topckgen CLK_TOP_MSDC50_2_H_SEL>;
 511                         clock-names = "source", "hclk";
 512                         status = "disabled";
 513                 };
 514
 515                 mmsys: clock-controller@14000000 {
 516                         compatible = "mediatek,mt8173-mmsys", "syscon";
 517                         reg = <0 0x14000000 0 0x1000>;
 518                         #clock-cells = <1>;
 519                 };
 520
 521                 imgsys: clock-controller@15000000 {
 522                         compatible = "mediatek,mt8173-imgsys", "syscon";
 523                         reg = <0 0x15000000 0 0x1000>;
 524                         #clock-cells = <1>;
 525                 };
 526
 527                 vdecsys: clock-controller@16000000 {
 528                         compatible = "mediatek,mt8173-vdecsys", "syscon";
 529                         reg = <0 0x16000000 0 0x1000>;
 530                         #clock-cells = <1>;
 531                 };
 532
 533                 vencsys: clock-controller@18000000 {
 534                         compatible = "mediatek,mt8173-vencsys", "syscon";
 535                         reg = <0 0x18000000 0 0x1000>;
 536                         #clock-cells = <1>;
 537                 };
 538
 539                 vencltsys: clock-controller@19000000 {
 540                         compatible = "mediatek,mt8173-vencltsys", "syscon";
 541                         reg = <0 0x19000000 0 0x1000>;
 542                         #clock-cells = <1>;
 543                 };
 544         };
 545 };
 546