2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 * Sean Wang <sean.wang@mediatek.com>
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/clock/mt7622-clk.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt7622-power.h>
14 #include <dt-bindings/reset/mt7622-reset.h>
15 #include <dt-bindings/thermal/thermal.h>
18 compatible = "mediatek,mt7622";
19 interrupt-parent = <&sysirq>;
23 cpu_opp_table: opp-table {
24 compatible = "operating-points-v2";
27 opp-hz = /bits/ 64 <30000000>;
28 opp-microvolt = <950000>;
32 opp-hz = /bits/ 64 <437500000>;
33 opp-microvolt = <1000000>;
37 opp-hz = /bits/ 64 <600000000>;
38 opp-microvolt = <1050000>;
42 opp-hz = /bits/ 64 <812500000>;
43 opp-microvolt = <1100000>;
47 opp-hz = /bits/ 64 <1025000000>;
48 opp-microvolt = <1150000>;
52 opp-hz = /bits/ 64 <1137500000>;
53 opp-microvolt = <1200000>;
57 opp-hz = /bits/ 64 <1262500000>;
58 opp-microvolt = <1250000>;
62 opp-hz = /bits/ 64 <1350000000>;
63 opp-microvolt = <1310000>;
73 compatible = "arm,cortex-a53", "arm,armv8";
75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
76 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = <&cpu_opp_table>;
80 enable-method = "psci";
81 clock-frequency = <1300000000>;
86 compatible = "arm,cortex-a53", "arm,armv8";
88 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
89 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
90 clock-names = "cpu", "intermediate";
91 operating-points-v2 = <&cpu_opp_table>;
93 enable-method = "psci";
94 clock-frequency = <1300000000>;
99 compatible = "fixed-clock";
100 clock-frequency = <40000000>;
105 compatible = "fixed-clock";
107 clock-frequency = <25000000>;
108 clock-output-names = "clkxtal";
112 compatible = "arm,psci-0.2";
117 #address-cells = <2>;
121 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
122 secmon_reserved: secmon@43000000 {
123 reg = <0 0x43000000 0 0x30000>;
129 cpu_thermal: cpu-thermal {
130 polling-delay-passive = <1000>;
131 polling-delay = <1000>;
133 thermal-sensors = <&thermal 0>;
136 cpu_passive: cpu-passive {
137 temperature = <47000>;
142 cpu_active: cpu-active {
143 temperature = <67000>;
149 temperature = <87000>;
155 temperature = <107000>;
163 trip = <&cpu_passive>;
164 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
168 trip = <&cpu_active>;
169 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
174 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
181 compatible = "arm,armv8-timer";
182 interrupt-parent = <&gic>;
183 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
184 IRQ_TYPE_LEVEL_HIGH)>,
185 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
186 IRQ_TYPE_LEVEL_HIGH)>,
187 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
188 IRQ_TYPE_LEVEL_HIGH)>,
189 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
190 IRQ_TYPE_LEVEL_HIGH)>;
193 infracfg: infracfg@10000000 {
194 compatible = "mediatek,mt7622-infracfg",
196 reg = <0 0x10000000 0 0x1000>;
201 pwrap: pwrap@10001000 {
202 compatible = "mediatek,mt7622-pwrap";
203 reg = <0 0x10001000 0 0x250>;
205 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
206 clock-names = "spi", "wrap";
207 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
208 reset-names = "pwrap";
209 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
213 pericfg: pericfg@10002000 {
214 compatible = "mediatek,mt7622-pericfg",
216 reg = <0 0x10002000 0 0x1000>;
221 scpsys: scpsys@10006000 {
222 compatible = "mediatek,mt7622-scpsys",
224 #power-domain-cells = <1>;
225 reg = <0 0x10006000 0 0x1000>;
226 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
227 <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
228 <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
229 <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
230 infracfg = <&infracfg>;
231 clocks = <&topckgen CLK_TOP_HIF_SEL>;
232 clock-names = "hif_sel";
236 compatible = "mediatek,mt7622-cir";
237 reg = <0 0x10009000 0 0x1000>;
238 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
239 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
240 <&topckgen CLK_TOP_AXI_SEL>;
241 clock-names = "clk", "bus";
245 sysirq: interrupt-controller@10200620 {
246 compatible = "mediatek,mt7622-sysirq",
247 "mediatek,mt6577-sysirq";
248 interrupt-controller;
249 #interrupt-cells = <3>;
250 interrupt-parent = <&gic>;
251 reg = <0 0x10200620 0 0x20>;
254 efuse: efuse@10206000 {
255 compatible = "mediatek,mt7622-efuse",
257 reg = <0 0x10206000 0 0x1000>;
258 #address-cells = <1>;
261 thermal_calibration: calib@198 {
266 apmixedsys: apmixedsys@10209000 {
267 compatible = "mediatek,mt7622-apmixedsys",
269 reg = <0 0x10209000 0 0x1000>;
273 topckgen: topckgen@10210000 {
274 compatible = "mediatek,mt7622-topckgen",
276 reg = <0 0x10210000 0 0x1000>;
281 compatible = "mediatek,mt7622-rng",
282 "mediatek,mt7623-rng";
283 reg = <0 0x1020f000 0 0x1000>;
284 clocks = <&infracfg CLK_INFRA_TRNG>;
288 pio: pinctrl@10211000 {
289 compatible = "mediatek,mt7622-pinctrl";
290 reg = <0 0x10211000 0 0x1000>,
291 <0 0x10005000 0 0x1000>;
292 reg-names = "base", "eint";
295 gpio-ranges = <&pio 0 0 103>;
296 interrupt-controller;
297 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
298 interrupt-parent = <&gic>;
299 #interrupt-cells = <2>;
302 watchdog: watchdog@10212000 {
303 compatible = "mediatek,mt7622-wdt",
304 "mediatek,mt6589-wdt";
305 reg = <0 0x10212000 0 0x800>;
309 compatible = "mediatek,mt7622-rtc",
311 reg = <0 0x10212800 0 0x200>;
312 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
313 clocks = <&topckgen CLK_TOP_RTC>;
317 gic: interrupt-controller@10300000 {
318 compatible = "arm,gic-400";
319 interrupt-controller;
320 #interrupt-cells = <3>;
321 interrupt-parent = <&gic>;
322 reg = <0 0x10310000 0 0x1000>,
323 <0 0x10320000 0 0x1000>,
324 <0 0x10340000 0 0x2000>,
325 <0 0x10360000 0 0x2000>;
328 auxadc: adc@11001000 {
329 compatible = "mediatek,mt7622-auxadc";
330 reg = <0 0x11001000 0 0x1000>;
331 clocks = <&pericfg CLK_PERI_AUXADC_PD>;
332 clock-names = "main";
333 #io-channel-cells = <1>;
336 uart0: serial@11002000 {
337 compatible = "mediatek,mt7622-uart",
338 "mediatek,mt6577-uart";
339 reg = <0 0x11002000 0 0x400>;
340 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
341 clocks = <&topckgen CLK_TOP_UART_SEL>,
342 <&pericfg CLK_PERI_UART0_PD>;
343 clock-names = "baud", "bus";
347 uart1: serial@11003000 {
348 compatible = "mediatek,mt7622-uart",
349 "mediatek,mt6577-uart";
350 reg = <0 0x11003000 0 0x400>;
351 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
352 clocks = <&topckgen CLK_TOP_UART_SEL>,
353 <&pericfg CLK_PERI_UART1_PD>;
354 clock-names = "baud", "bus";
358 uart2: serial@11004000 {
359 compatible = "mediatek,mt7622-uart",
360 "mediatek,mt6577-uart";
361 reg = <0 0x11004000 0 0x400>;
362 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
363 clocks = <&topckgen CLK_TOP_UART_SEL>,
364 <&pericfg CLK_PERI_UART2_PD>;
365 clock-names = "baud", "bus";
369 uart3: serial@11005000 {
370 compatible = "mediatek,mt7622-uart",
371 "mediatek,mt6577-uart";
372 reg = <0 0x11005000 0 0x400>;
373 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
374 clocks = <&topckgen CLK_TOP_UART_SEL>,
375 <&pericfg CLK_PERI_UART3_PD>;
376 clock-names = "baud", "bus";
381 compatible = "mediatek,mt7622-pwm";
382 reg = <0 0x11006000 0 0x1000>;
383 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
384 clocks = <&topckgen CLK_TOP_PWM_SEL>,
385 <&pericfg CLK_PERI_PWM_PD>,
386 <&pericfg CLK_PERI_PWM1_PD>,
387 <&pericfg CLK_PERI_PWM2_PD>,
388 <&pericfg CLK_PERI_PWM3_PD>,
389 <&pericfg CLK_PERI_PWM4_PD>,
390 <&pericfg CLK_PERI_PWM5_PD>,
391 <&pericfg CLK_PERI_PWM6_PD>;
392 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
398 compatible = "mediatek,mt7622-i2c";
399 reg = <0 0x11007000 0 0x90>,
400 <0 0x11000100 0 0x80>;
401 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
403 clocks = <&pericfg CLK_PERI_I2C0_PD>,
404 <&pericfg CLK_PERI_AP_DMA_PD>;
405 clock-names = "main", "dma";
406 #address-cells = <1>;
412 compatible = "mediatek,mt7622-i2c";
413 reg = <0 0x11008000 0 0x90>,
414 <0 0x11000180 0 0x80>;
415 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
417 clocks = <&pericfg CLK_PERI_I2C1_PD>,
418 <&pericfg CLK_PERI_AP_DMA_PD>;
419 clock-names = "main", "dma";
420 #address-cells = <1>;
426 compatible = "mediatek,mt7622-i2c";
427 reg = <0 0x11009000 0 0x90>,
428 <0 0x11000200 0 0x80>;
429 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
431 clocks = <&pericfg CLK_PERI_I2C2_PD>,
432 <&pericfg CLK_PERI_AP_DMA_PD>;
433 clock-names = "main", "dma";
434 #address-cells = <1>;
440 compatible = "mediatek,mt7622-spi";
441 reg = <0 0x1100a000 0 0x100>;
442 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
443 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
444 <&topckgen CLK_TOP_SPI0_SEL>,
445 <&pericfg CLK_PERI_SPI0_PD>;
446 clock-names = "parent-clk", "sel-clk", "spi-clk";
447 #address-cells = <1>;
452 thermal: thermal@1100b000 {
453 #thermal-sensor-cells = <1>;
454 compatible = "mediatek,mt7622-thermal";
455 reg = <0 0x1100b000 0 0x1000>;
456 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
457 clocks = <&pericfg CLK_PERI_THERM_PD>,
458 <&pericfg CLK_PERI_AUXADC_PD>;
459 clock-names = "therm", "auxadc";
460 resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
461 reset-names = "therm";
462 mediatek,auxadc = <&auxadc>;
463 mediatek,apmixedsys = <&apmixedsys>;
464 nvmem-cells = <&thermal_calibration>;
465 nvmem-cell-names = "calibration-data";
468 btif: serial@1100c000 {
469 compatible = "mediatek,mt7622-btif",
471 reg = <0 0x1100c000 0 0x1000>;
472 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
473 clocks = <&pericfg CLK_PERI_BTIF_PD>;
474 clock-names = "main";
480 nandc: nfi@1100d000 {
481 compatible = "mediatek,mt7622-nfc";
482 reg = <0 0x1100D000 0 0x1000>;
483 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
484 clocks = <&pericfg CLK_PERI_NFI_PD>,
485 <&pericfg CLK_PERI_SNFI_PD>;
486 clock-names = "nfi_clk", "pad_clk";
488 #address-cells = <1>;
494 compatible = "mediatek,mt7622-ecc";
495 reg = <0 0x1100e000 0 0x1000>;
496 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
497 clocks = <&pericfg CLK_PERI_NFIECC_PD>;
498 clock-names = "nfiecc_clk";
502 nor_flash: spi@11014000 {
503 compatible = "mediatek,mt7622-nor",
504 "mediatek,mt8173-nor";
505 reg = <0 0x11014000 0 0xe0>;
506 clocks = <&pericfg CLK_PERI_FLASH_PD>,
507 <&topckgen CLK_TOP_FLASH_SEL>;
508 clock-names = "spi", "sf";
509 #address-cells = <1>;
515 compatible = "mediatek,mt7622-spi";
516 reg = <0 0x11016000 0 0x100>;
517 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
518 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
519 <&topckgen CLK_TOP_SPI1_SEL>,
520 <&pericfg CLK_PERI_SPI1_PD>;
521 clock-names = "parent-clk", "sel-clk", "spi-clk";
522 #address-cells = <1>;
527 uart4: serial@11019000 {
528 compatible = "mediatek,mt7622-uart",
529 "mediatek,mt6577-uart";
530 reg = <0 0x11019000 0 0x400>;
531 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
532 clocks = <&topckgen CLK_TOP_UART_SEL>,
533 <&pericfg CLK_PERI_UART4_PD>;
534 clock-names = "baud", "bus";
538 audsys: clock-controller@11220000 {
539 compatible = "mediatek,mt7622-audsys", "syscon";
540 reg = <0 0x11220000 0 0x2000>;
543 afe: audio-controller {
544 compatible = "mediatek,mt7622-audio";
545 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
546 <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
547 interrupt-names = "afe", "asys";
549 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
550 <&topckgen CLK_TOP_AUD1_SEL>,
551 <&topckgen CLK_TOP_AUD2_SEL>,
552 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
553 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
554 <&topckgen CLK_TOP_I2S0_MCK_SEL>,
555 <&topckgen CLK_TOP_I2S1_MCK_SEL>,
556 <&topckgen CLK_TOP_I2S2_MCK_SEL>,
557 <&topckgen CLK_TOP_I2S3_MCK_SEL>,
558 <&topckgen CLK_TOP_I2S0_MCK_DIV>,
559 <&topckgen CLK_TOP_I2S1_MCK_DIV>,
560 <&topckgen CLK_TOP_I2S2_MCK_DIV>,
561 <&topckgen CLK_TOP_I2S3_MCK_DIV>,
562 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
563 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
564 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
565 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
566 <&audsys CLK_AUDIO_I2SO1>,
567 <&audsys CLK_AUDIO_I2SO2>,
568 <&audsys CLK_AUDIO_I2SO3>,
569 <&audsys CLK_AUDIO_I2SO4>,
570 <&audsys CLK_AUDIO_I2SIN1>,
571 <&audsys CLK_AUDIO_I2SIN2>,
572 <&audsys CLK_AUDIO_I2SIN3>,
573 <&audsys CLK_AUDIO_I2SIN4>,
574 <&audsys CLK_AUDIO_ASRCO1>,
575 <&audsys CLK_AUDIO_ASRCO2>,
576 <&audsys CLK_AUDIO_ASRCO3>,
577 <&audsys CLK_AUDIO_ASRCO4>,
578 <&audsys CLK_AUDIO_AFE>,
579 <&audsys CLK_AUDIO_AFE_CONN>,
580 <&audsys CLK_AUDIO_A1SYS>,
581 <&audsys CLK_AUDIO_A2SYS>;
583 clock-names = "infra_sys_audio_clk",
584 "top_audio_mux1_sel",
585 "top_audio_mux2_sel",
586 "top_audio_a1sys_hp",
587 "top_audio_a2sys_hp",
617 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
618 <&topckgen CLK_TOP_A2SYS_HP_SEL>,
619 <&topckgen CLK_TOP_A1SYS_HP_DIV>,
620 <&topckgen CLK_TOP_A2SYS_HP_DIV>;
621 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
622 <&topckgen CLK_TOP_AUD2PLL>;
623 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
628 compatible = "mediatek,mt7622-mmc";
629 reg = <0 0x11230000 0 0x1000>;
630 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
631 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
632 <&topckgen CLK_TOP_MSDC50_0_SEL>;
633 clock-names = "source", "hclk";
638 compatible = "mediatek,mt7622-mmc";
639 reg = <0 0x11240000 0 0x1000>;
640 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
641 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
642 <&topckgen CLK_TOP_AXI_SEL>;
643 clock-names = "source", "hclk";
647 ssusbsys: ssusbsys@1a000000 {
648 compatible = "mediatek,mt7622-ssusbsys",
650 reg = <0 0x1a000000 0 0x1000>;
655 ssusb: usb@1a0c0000 {
656 compatible = "mediatek,mt7622-xhci",
658 reg = <0 0x1a0c0000 0 0x01000>,
659 <0 0x1a0c4700 0 0x0100>;
660 reg-names = "mac", "ippc";
661 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
662 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
663 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
664 <&ssusbsys CLK_SSUSB_REF_EN>,
665 <&ssusbsys CLK_SSUSB_MCU_EN>,
666 <&ssusbsys CLK_SSUSB_DMA_EN>;
667 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
668 phys = <&u2port0 PHY_TYPE_USB2>,
669 <&u3port0 PHY_TYPE_USB3>,
670 <&u2port1 PHY_TYPE_USB2>;
675 u3phy: usb-phy@1a0c4000 {
676 compatible = "mediatek,mt7622-u3phy",
677 "mediatek,generic-tphy-v1";
678 reg = <0 0x1a0c4000 0 0x700>;
679 #address-cells = <2>;
684 u2port0: usb-phy@1a0c4800 {
685 reg = <0 0x1a0c4800 0 0x0100>;
687 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
691 u3port0: usb-phy@1a0c4900 {
692 reg = <0 0x1a0c4900 0 0x0700>;
698 u2port1: usb-phy@1a0c5000 {
699 reg = <0 0x1a0c5000 0 0x0100>;
701 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
706 pciesys: pciesys@1a100800 {
707 compatible = "mediatek,mt7622-pciesys",
709 reg = <0 0x1a100800 0 0x1000>;
714 pcie: pcie@1a140000 {
715 compatible = "mediatek,mt7622-pcie";
717 reg = <0 0x1a140000 0 0x1000>,
718 <0 0x1a143000 0 0x1000>,
719 <0 0x1a145000 0 0x1000>;
720 reg-names = "subsys", "port0", "port1";
721 #address-cells = <3>;
723 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
724 <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
725 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
726 <&pciesys CLK_PCIE_P1_MAC_EN>,
727 <&pciesys CLK_PCIE_P0_AHB_EN>,
728 <&pciesys CLK_PCIE_P0_AHB_EN>,
729 <&pciesys CLK_PCIE_P0_AUX_EN>,
730 <&pciesys CLK_PCIE_P1_AUX_EN>,
731 <&pciesys CLK_PCIE_P0_AXI_EN>,
732 <&pciesys CLK_PCIE_P1_AXI_EN>,
733 <&pciesys CLK_PCIE_P0_OBFF_EN>,
734 <&pciesys CLK_PCIE_P1_OBFF_EN>,
735 <&pciesys CLK_PCIE_P0_PIPE_EN>,
736 <&pciesys CLK_PCIE_P1_PIPE_EN>;
737 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
738 "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
739 "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
740 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
741 bus-range = <0x00 0xff>;
742 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
746 reg = <0x0000 0 0 0 0>;
747 #address-cells = <3>;
749 #interrupt-cells = <1>;
754 interrupt-map-mask = <0 0 0 7>;
755 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
756 <0 0 0 2 &pcie_intc0 1>,
757 <0 0 0 3 &pcie_intc0 2>,
758 <0 0 0 4 &pcie_intc0 3>;
759 pcie_intc0: interrupt-controller {
760 interrupt-controller;
761 #address-cells = <0>;
762 #interrupt-cells = <1>;
767 reg = <0x0800 0 0 0 0>;
768 #address-cells = <3>;
770 #interrupt-cells = <1>;
775 interrupt-map-mask = <0 0 0 7>;
776 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
777 <0 0 0 2 &pcie_intc1 1>,
778 <0 0 0 3 &pcie_intc1 2>,
779 <0 0 0 4 &pcie_intc1 3>;
780 pcie_intc1: interrupt-controller {
781 interrupt-controller;
782 #address-cells = <0>;
783 #interrupt-cells = <1>;
788 sata: sata@1a200000 {
789 compatible = "mediatek,mt7622-ahci",
791 reg = <0 0x1a200000 0 0x1100>;
792 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
793 interrupt-names = "hostc";
794 clocks = <&pciesys CLK_SATA_AHB_EN>,
795 <&pciesys CLK_SATA_AXI_EN>,
796 <&pciesys CLK_SATA_ASIC_EN>,
797 <&pciesys CLK_SATA_RBC_EN>,
798 <&pciesys CLK_SATA_PM_EN>;
799 clock-names = "ahb", "axi", "asic", "rbc", "pm";
800 phys = <&sata_port PHY_TYPE_SATA>;
801 phy-names = "sata-phy";
802 ports-implemented = <0x1>;
803 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
804 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
805 <&pciesys MT7622_SATA_PHY_SW_RST>,
806 <&pciesys MT7622_SATA_PHY_REG_RST>;
807 reset-names = "axi", "sw", "reg";
808 mediatek,phy-mode = <&pciesys>;
812 sata_phy: sata-phy@1a243000 {
813 compatible = "mediatek,generic-tphy-v1";
814 #address-cells = <2>;
819 sata_port: sata-phy@1a243000 {
820 reg = <0 0x1a243000 0 0x0100>;
821 clocks = <&topckgen CLK_TOP_ETH_500M>;
827 ethsys: syscon@1b000000 {
828 compatible = "mediatek,mt7622-ethsys",
830 reg = <0 0x1b000000 0 0x1000>;
835 hsdma: dma-controller@1b007000 {
836 compatible = "mediatek,mt7622-hsdma";
837 reg = <0 0x1b007000 0 0x1000>;
838 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
839 clocks = <ðsys CLK_ETH_HSDMA_EN>;
840 clock-names = "hsdma";
841 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
845 eth: ethernet@1b100000 {
846 compatible = "mediatek,mt7622-eth",
847 "mediatek,mt2701-eth",
849 reg = <0 0x1b100000 0 0x20000>;
850 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
851 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
852 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
853 clocks = <&topckgen CLK_TOP_ETH_SEL>,
854 <ðsys CLK_ETH_ESW_EN>,
855 <ðsys CLK_ETH_GP0_EN>,
856 <ðsys CLK_ETH_GP1_EN>,
857 <ðsys CLK_ETH_GP2_EN>,
858 <&sgmiisys CLK_SGMII_TX250M_EN>,
859 <&sgmiisys CLK_SGMII_RX250M_EN>,
860 <&sgmiisys CLK_SGMII_CDR_REF>,
861 <&sgmiisys CLK_SGMII_CDR_FB>,
862 <&topckgen CLK_TOP_SGMIIPLL>,
863 <&apmixedsys CLK_APMIXED_ETH2PLL>;
864 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
865 "sgmii_tx250m", "sgmii_rx250m",
866 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
868 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
869 mediatek,ethsys = <ðsys>;
870 mediatek,sgmiisys = <&sgmiisys>;
871 #address-cells = <1>;
876 sgmiisys: sgmiisys@1b128000 {
877 compatible = "mediatek,mt7622-sgmiisys",
879 reg = <0 0x1b128000 0 0x1000>;