arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts

   1 /*
   2  * Copyright (c) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0 OR MIT)
   6  */
   7
   8 /dts-v1/;
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 #include "mt7622.dtsi"
  13 #include "mt6380.dtsi"
  14
  15 / {
  16         model = "Bananapi BPI-R64";
  17         compatible = "bananapi,bpi-r64", "mediatek,mt7622";
  18
  19         aliases {
  20                 serial0 = &uart0;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25                 bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
  26         };
  27
  28         cpus {
  29                 cpu@0 {
  30                         proc-supply = <&mt6380_vcpu_reg>;
  31                         sram-supply = <&mt6380_vm_reg>;
  32                 };
  33
  34                 cpu@1 {
  35                         proc-supply = <&mt6380_vcpu_reg>;
  36                         sram-supply = <&mt6380_vm_reg>;
  37                 };
  38         };
  39
  40         gpio-keys {
  41                 compatible = "gpio-keys";
  42
  43                 factory {
  44                         label = "factory";
  45                         linux,code = <BTN_0>;
  46                         gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  47                 };
  48
  49                 wps {
  50                         label = "wps";
  51                         linux,code = <KEY_WPS_BUTTON>;
  52                         gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
  53                 };
  54         };
  55
  56         leds {
  57                 compatible = "gpio-leds";
  58
  59                 green {
  60                         label = "bpi-r64:pio:green";
  61                         gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
  62                         default-state = "off";
  63                 };
  64
  65                 red {
  66                         label = "bpi-r64:pio:red";
  67                         gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
  68                         default-state = "off";
  69                 };
  70         };
  71
  72         memory {
  73                 reg = <0 0x40000000 0 0x40000000>;
  74         };
  75
  76         reg_1p8v: regulator-1p8v {
  77                 compatible = "regulator-fixed";
  78                 regulator-name = "fixed-1.8V";
  79                 regulator-min-microvolt = <1800000>;
  80                 regulator-max-microvolt = <1800000>;
  81                 regulator-always-on;
  82         };
  83
  84         reg_3p3v: regulator-3p3v {
  85                 compatible = "regulator-fixed";
  86                 regulator-name = "fixed-3.3V";
  87                 regulator-min-microvolt = <3300000>;
  88                 regulator-max-microvolt = <3300000>;
  89                 regulator-boot-on;
  90                 regulator-always-on;
  91         };
  92
  93         reg_5v: regulator-5v {
  94                 compatible = "regulator-fixed";
  95                 regulator-name = "fixed-5V";
  96                 regulator-min-microvolt = <5000000>;
  97                 regulator-max-microvolt = <5000000>;
  98                 regulator-boot-on;
  99                 regulator-always-on;
 100         };
 101 };
 102
 103 &bch {
 104         status = "disabled";
 105 };
 106
 107 &btif {
 108         status = "okay";
 109 };
 110
 111 &cir {
 112         pinctrl-names = "default";
 113         pinctrl-0 = <&irrx_pins>;
 114         status = "okay";
 115 };
 116
 117 &eth {
 118         status = "okay";
 119         gmac0: mac@0 {
 120                 compatible = "mediatek,eth-mac";
 121                 reg = <0>;
 122                 phy-mode = "2500base-x";
 123
 124                 fixed-link {
 125                         speed = <2500>;
 126                         full-duplex;
 127                         pause;
 128                 };
 129         };
 130
 131         gmac1: mac@1 {
 132                 compatible = "mediatek,eth-mac";
 133                 reg = <1>;
 134                 phy-mode = "rgmii";
 135
 136                 fixed-link {
 137                         speed = <1000>;
 138                         full-duplex;
 139                         pause;
 140                 };
 141         };
 142
 143         mdio: mdio-bus {
 144                 #address-cells = <1>;
 145                 #size-cells = <0>;
 146         };
 147 };
 148
 149 &i2c1 {
 150         pinctrl-names = "default";
 151         pinctrl-0 = <&i2c1_pins>;
 152         status = "okay";
 153 };
 154
 155 &i2c2 {
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&i2c2_pins>;
 158         status = "okay";
 159 };
 160
 161 &mmc0 {
 162         pinctrl-names = "default", "state_uhs";
 163         pinctrl-0 = <&emmc_pins_default>;
 164         pinctrl-1 = <&emmc_pins_uhs>;
 165         status = "okay";
 166         bus-width = <8>;
 167         max-frequency = <50000000>;
 168         cap-mmc-highspeed;
 169         mmc-hs200-1_8v;
 170         vmmc-supply = <&reg_3p3v>;
 171         vqmmc-supply = <&reg_1p8v>;
 172         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 173         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 174         non-removable;
 175 };
 176
 177 &mmc1 {
 178         pinctrl-names = "default", "state_uhs";
 179         pinctrl-0 = <&sd0_pins_default>;
 180         pinctrl-1 = <&sd0_pins_uhs>;
 181         status = "okay";
 182         bus-width = <4>;
 183         max-frequency = <50000000>;
 184         cap-sd-highspeed;
 185         r_smpl = <1>;
 186         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 187         vmmc-supply = <&reg_3p3v>;
 188         vqmmc-supply = <&reg_3p3v>;
 189         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 190         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 191 };
 192
 193 &nandc {
 194         pinctrl-names = "default";
 195         pinctrl-0 = <&parallel_nand_pins>;
 196         status = "disabled";
 197 };
 198
 199 &nor_flash {
 200         pinctrl-names = "default";
 201         pinctrl-0 = <&spi_nor_pins>;
 202         status = "disabled";
 203
 204         flash@0 {
 205                 compatible = "jedec,spi-nor";
 206                 reg = <0>;
 207         };
 208 };
 209
 210 &pcie {
 211         pinctrl-names = "default";
 212         pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
 213         status = "okay";
 214
 215         pcie@0,0 {
 216                 status = "okay";
 217         };
 218
 219         pcie@1,0 {
 220                 status = "okay";
 221         };
 222 };
 223
 224 &pio {
 225         /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 226          * SATA functions. i.e. output-high: PCIe, output-low: SATA
 227          */
 228         asm_sel {
 229                 gpio-hog;
 230                 gpios = <90 GPIO_ACTIVE_HIGH>;
 231                 output-high;
 232         };
 233
 234         /* eMMC is shared pin with parallel NAND */
 235         emmc_pins_default: emmc-pins-default {
 236                 mux {
 237                         function = "emmc", "emmc_rst";
 238                         groups = "emmc";
 239                 };
 240
 241                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 242                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 243                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 244                  */
 245                 conf-cmd-dat {
 246                         pins = "NDL0", "NDL1", "NDL2",
 247                                "NDL3", "NDL4", "NDL5",
 248                                "NDL6", "NDL7", "NRB";
 249                         input-enable;
 250                         bias-pull-up;
 251                 };
 252
 253                 conf-clk {
 254                         pins = "NCLE";
 255                         bias-pull-down;
 256                 };
 257         };
 258
 259         emmc_pins_uhs: emmc-pins-uhs {
 260                 mux {
 261                         function = "emmc";
 262                         groups = "emmc";
 263                 };
 264
 265                 conf-cmd-dat {
 266                         pins = "NDL0", "NDL1", "NDL2",
 267                                "NDL3", "NDL4", "NDL5",
 268                                "NDL6", "NDL7", "NRB";
 269                         input-enable;
 270                         drive-strength = <4>;
 271                         bias-pull-up;
 272                 };
 273
 274                 conf-clk {
 275                         pins = "NCLE";
 276                         drive-strength = <4>;
 277                         bias-pull-down;
 278                 };
 279         };
 280
 281         eth_pins: eth-pins {
 282                 mux {
 283                         function = "eth";
 284                         groups = "mdc_mdio", "rgmii_via_gmac2";
 285                 };
 286         };
 287
 288         i2c1_pins: i2c1-pins {
 289                 mux {
 290                         function = "i2c";
 291                         groups =  "i2c1_0";
 292                 };
 293         };
 294
 295         i2c2_pins: i2c2-pins {
 296                 mux {
 297                         function = "i2c";
 298                         groups =  "i2c2_0";
 299                 };
 300         };
 301
 302         i2s1_pins: i2s1-pins {
 303                 mux {
 304                         function = "i2s";
 305                         groups =  "i2s_out_mclk_bclk_ws",
 306                                   "i2s1_in_data",
 307                                   "i2s1_out_data";
 308                 };
 309
 310                 conf {
 311                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 312                                "I2S_WS", "I2S_MCLK";
 313                         drive-strength = <12>;
 314                         bias-pull-down;
 315                 };
 316         };
 317
 318         irrx_pins: irrx-pins {
 319                 mux {
 320                         function = "ir";
 321                         groups =  "ir_1_rx";
 322                 };
 323         };
 324
 325         irtx_pins: irtx-pins {
 326                 mux {
 327                         function = "ir";
 328                         groups =  "ir_1_tx";
 329                 };
 330         };
 331
 332         /* Parallel nand is shared pin with eMMC */
 333         parallel_nand_pins: parallel-nand-pins {
 334                 mux {
 335                         function = "flash";
 336                         groups = "par_nand";
 337                 };
 338         };
 339
 340         pcie0_pins: pcie0-pins {
 341                 mux {
 342                         function = "pcie";
 343                         groups = "pcie0_pad_perst",
 344                                  "pcie0_1_waken",
 345                                  "pcie0_1_clkreq";
 346                 };
 347         };
 348
 349         pcie1_pins: pcie1-pins {
 350                 mux {
 351                         function = "pcie";
 352                         groups = "pcie1_pad_perst",
 353                                  "pcie1_0_waken",
 354                                  "pcie1_0_clkreq";
 355                 };
 356         };
 357
 358         pmic_bus_pins: pmic-bus-pins {
 359                 mux {
 360                         function = "pmic";
 361                         groups = "pmic_bus";
 362                 };
 363         };
 364
 365         pwm7_pins: pwm1-2-pins {
 366                 mux {
 367                         function = "pwm";
 368                         groups = "pwm_ch7_2";
 369                 };
 370         };
 371
 372         wled_pins: wled-pins {
 373                 mux {
 374                         function = "led";
 375                         groups = "wled";
 376                 };
 377         };
 378
 379         sd0_pins_default: sd0-pins-default {
 380                 mux {
 381                         function = "sd";
 382                         groups = "sd_0";
 383                 };
 384
 385                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 386                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 387                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 388                  */
 389                 conf-cmd-data {
 390                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 391                                "I2S2_IN","I2S4_OUT";
 392                         input-enable;
 393                         drive-strength = <8>;
 394                         bias-pull-up;
 395                 };
 396                 conf-clk {
 397                         pins = "I2S3_OUT";
 398                         drive-strength = <12>;
 399                         bias-pull-down;
 400                 };
 401                 conf-cd {
 402                         pins = "TXD3";
 403                         bias-pull-up;
 404                 };
 405         };
 406
 407         sd0_pins_uhs: sd0-pins-uhs {
 408                 mux {
 409                         function = "sd";
 410                         groups = "sd_0";
 411                 };
 412
 413                 conf-cmd-data {
 414                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 415                                "I2S2_IN","I2S4_OUT";
 416                         input-enable;
 417                         bias-pull-up;
 418                 };
 419
 420                 conf-clk {
 421                         pins = "I2S3_OUT";
 422                         bias-pull-down;
 423                 };
 424         };
 425
 426         /* Serial NAND is shared pin with SPI-NOR */
 427         serial_nand_pins: serial-nand-pins {
 428                 mux {
 429                         function = "flash";
 430                         groups = "snfi";
 431                 };
 432         };
 433
 434         spic0_pins: spic0-pins {
 435                 mux {
 436                         function = "spi";
 437                         groups = "spic0_0";
 438                 };
 439         };
 440
 441         spic1_pins: spic1-pins {
 442                 mux {
 443                         function = "spi";
 444                         groups = "spic1_0";
 445                 };
 446         };
 447
 448         /* SPI-NOR is shared pin with serial NAND */
 449         spi_nor_pins: spi-nor-pins {
 450                 mux {
 451                         function = "flash";
 452                         groups = "spi_nor";
 453                 };
 454         };
 455
 456         /* serial NAND is shared pin with SPI-NOR */
 457         serial_nand_pins: serial-nand-pins {
 458                 mux {
 459                         function = "flash";
 460                         groups = "snfi";
 461                 };
 462         };
 463
 464         uart0_pins: uart0-pins {
 465                 mux {
 466                         function = "uart";
 467                         groups = "uart0_0_tx_rx" ;
 468                 };
 469         };
 470
 471         uart2_pins: uart2-pins {
 472                 mux {
 473                         function = "uart";
 474                         groups = "uart2_1_tx_rx" ;
 475                 };
 476         };
 477
 478         watchdog_pins: watchdog-pins {
 479                 mux {
 480                         function = "watchdog";
 481                         groups = "watchdog";
 482                 };
 483         };
 484 };
 485
 486 &pwm {
 487         pinctrl-names = "default";
 488         pinctrl-0 = <&pwm7_pins>;
 489         status = "okay";
 490 };
 491
 492 &pwrap {
 493         pinctrl-names = "default";
 494         pinctrl-0 = <&pmic_bus_pins>;
 495
 496         status = "okay";
 497 };
 498
 499 &sata {
 500         status = "disable";
 501 };
 502
 503 &sata_phy {
 504         status = "disable";
 505 };
 506
 507 &spi0 {
 508         pinctrl-names = "default";
 509         pinctrl-0 = <&spic0_pins>;
 510         status = "okay";
 511 };
 512
 513 &spi1 {
 514         pinctrl-names = "default";
 515         pinctrl-0 = <&spic1_pins>;
 516         status = "okay";
 517 };
 518
 519 &ssusb {
 520         vusb33-supply = <&reg_3p3v>;
 521         vbus-supply = <&reg_5v>;
 522         status = "okay";
 523 };
 524
 525 &u3phy {
 526         status = "okay";
 527 };
 528
 529 &uart0 {
 530         pinctrl-names = "default";
 531         pinctrl-0 = <&uart0_pins>;
 532         status = "okay";
 533 };
 534
 535 &uart2 {
 536         pinctrl-names = "default";
 537         pinctrl-0 = <&uart2_pins>;
 538         status = "okay";
 539 };
 540
 541 &watchdog {
 542         pinctrl-names = "default";
 543         pinctrl-0 = <&watchdog_pins>;
 544         status = "okay";
 545 };