arch/arm/mm/mmu.c

   1 /*
   2  *  linux/arch/arm/mm/mmu.c
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/init.h>
  14 #include <linux/mman.h>
  15 #include <linux/nodemask.h>
  16 #include <linux/memblock.h>
  17 #include <linux/fs.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/sizes.h>
  20
  21 #include <asm/cp15.h>
  22 #include <asm/cputype.h>
  23 #include <asm/sections.h>
  24 #include <asm/cachetype.h>
  25 #include <asm/setup.h>
  26 #include <asm/smp_plat.h>
  27 #include <asm/tlb.h>
  28 #include <asm/highmem.h>
  29 #include <asm/system_info.h>
  30 #include <asm/traps.h>
  31
  32 #include <asm/mach/arch.h>
  33 #include <asm/mach/map.h>
  34 #include <asm/mach/pci.h>
  35
  36 #include "mm.h"
  37 #include "tcm.h"
  38
  39 /*
  40  * empty_zero_page is a special page that is used for
  41  * zero-initialized data and COW.
  42  */
  43 struct page *empty_zero_page;
  44 EXPORT_SYMBOL(empty_zero_page);
  45
  46 /*
  47  * The pmd table for the upper-most set of pages.
  48  */
  49 pmd_t *top_pmd;
  50
  51 #define CPOLICY_UNCACHED        0
  52 #define CPOLICY_BUFFERED        1
  53 #define CPOLICY_WRITETHROUGH    2
  54 #define CPOLICY_WRITEBACK       3
  55 #define CPOLICY_WRITEALLOC      4
  56
  57 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  58 static unsigned int ecc_mask __initdata = 0;
  59 pgprot_t pgprot_user;
  60 pgprot_t pgprot_kernel;
  61 pgprot_t pgprot_hyp_device;
  62 pgprot_t pgprot_s2;
  63 pgprot_t pgprot_s2_device;
  64
  65 EXPORT_SYMBOL(pgprot_user);
  66 EXPORT_SYMBOL(pgprot_kernel);
  67
  68 struct cachepolicy {
  69         const char      policy[16];
  70         unsigned int    cr_mask;
  71         pmdval_t        pmd;
  72         pteval_t        pte;
  73         pteval_t        pte_s2;
  74 };
  75
  76 #ifdef CONFIG_ARM_LPAE
  77 #define s2_policy(policy)       policy
  78 #else
  79 #define s2_policy(policy)       0
  80 #endif
  81
  82 static struct cachepolicy cache_policies[] __initdata = {
  83         {
  84                 .policy         = "uncached",
  85                 .cr_mask        = CR_W|CR_C,
  86                 .pmd            = PMD_SECT_UNCACHED,
  87                 .pte            = L_PTE_MT_UNCACHED,
  88                 .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
  89         }, {
  90                 .policy         = "buffered",
  91                 .cr_mask        = CR_C,
  92                 .pmd            = PMD_SECT_BUFFERED,
  93                 .pte            = L_PTE_MT_BUFFERABLE,
  94                 .pte_s2         = s2_policy(L_PTE_S2_MT_UNCACHED),
  95         }, {
  96                 .policy         = "writethrough",
  97                 .cr_mask        = 0,
  98                 .pmd            = PMD_SECT_WT,
  99                 .pte            = L_PTE_MT_WRITETHROUGH,
 100                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
 101         }, {
 102                 .policy         = "writeback",
 103                 .cr_mask        = 0,
 104                 .pmd            = PMD_SECT_WB,
 105                 .pte            = L_PTE_MT_WRITEBACK,
 106                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
 107         }, {
 108                 .policy         = "writealloc",
 109                 .cr_mask        = 0,
 110                 .pmd            = PMD_SECT_WBWA,
 111                 .pte            = L_PTE_MT_WRITEALLOC,
 112                 .pte_s2         = s2_policy(L_PTE_S2_MT_WRITEBACK),
 113         }
 114 };
 115
 116 #ifdef CONFIG_CPU_CP15
 117 /*
 118  * These are useful for identifying cache coherency
 119  * problems by allowing the cache or the cache and
 120  * writebuffer to be turned off.  (Note: the write
 121  * buffer should not be on and the cache off).
 122  */
 123 static int __init early_cachepolicy(char *p)
 124 {
 125         int i;
 126
 127         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 128                 int len = strlen(cache_policies[i].policy);
 129
 130                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
 131                         cachepolicy = i;
 132                         cr_alignment &= ~cache_policies[i].cr_mask;
 133                         cr_no_alignment &= ~cache_policies[i].cr_mask;
 134                         break;
 135                 }
 136         }
 137         if (i == ARRAY_SIZE(cache_policies))
 138                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 139         /*
 140          * This restriction is partly to do with the way we boot; it is
 141          * unpredictable to have memory mapped using two different sets of
 142          * memory attributes (shared, type, and cache attribs).  We can not
 143          * change these attributes once the initial assembly has setup the
 144          * page tables.
 145          */
 146         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
 147                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
 148                 cachepolicy = CPOLICY_WRITEBACK;
 149         }
 150         flush_cache_all();
 151         set_cr(cr_alignment);
 152         return 0;
 153 }
 154 early_param("cachepolicy", early_cachepolicy);
 155
 156 static int __init early_nocache(char *__unused)
 157 {
 158         char *p = "buffered";
 159         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 160         early_cachepolicy(p);
 161         return 0;
 162 }
 163 early_param("nocache", early_nocache);
 164
 165 static int __init early_nowrite(char *__unused)
 166 {
 167         char *p = "uncached";
 168         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 169         early_cachepolicy(p);
 170         return 0;
 171 }
 172 early_param("nowb", early_nowrite);
 173
 174 #ifndef CONFIG_ARM_LPAE
 175 static int __init early_ecc(char *p)
 176 {
 177         if (memcmp(p, "on", 2) == 0)
 178                 ecc_mask = PMD_PROTECTION;
 179         else if (memcmp(p, "off", 3) == 0)
 180                 ecc_mask = 0;
 181         return 0;
 182 }
 183 early_param("ecc", early_ecc);
 184 #endif
 185
 186 static int __init noalign_setup(char *__unused)
 187 {
 188         cr_alignment &= ~CR_A;
 189         cr_no_alignment &= ~CR_A;
 190         set_cr(cr_alignment);
 191         return 1;
 192 }
 193 __setup("noalign", noalign_setup);
 194
 195 #ifndef CONFIG_SMP
 196 void adjust_cr(unsigned long mask, unsigned long set)
 197 {
 198         unsigned long flags;
 199
 200         mask &= ~CR_A;
 201
 202         set &= mask;
 203
 204         local_irq_save(flags);
 205
 206         cr_no_alignment = (cr_no_alignment & ~mask) | set;
 207         cr_alignment = (cr_alignment & ~mask) | set;
 208
 209         set_cr((get_cr() & ~mask) | set);
 210
 211         local_irq_restore(flags);
 212 }
 213 #endif
 214
 215 #else /* ifdef CONFIG_CPU_CP15 */
 216
 217 static int __init early_cachepolicy(char *p)
 218 {
 219         pr_warning("cachepolicy kernel parameter not supported without cp15\n");
 220 }
 221 early_param("cachepolicy", early_cachepolicy);
 222
 223 static int __init noalign_setup(char *__unused)
 224 {
 225         pr_warning("noalign kernel parameter not supported without cp15\n");
 226 }
 227 __setup("noalign", noalign_setup);
 228
 229 #endif /* ifdef CONFIG_CPU_CP15 / else */
 230
 231 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
 232 #define PROT_PTE_S2_DEVICE      PROT_PTE_DEVICE
 233 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 234
 235 static struct mem_type mem_types[] = {
 236         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
 237                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 238                                   L_PTE_SHARED,
 239                 .prot_pte_s2    = s2_policy(PROT_PTE_S2_DEVICE) |
 240                                   s2_policy(L_PTE_S2_MT_DEV_SHARED) |
 241                                   L_PTE_SHARED,
 242                 .prot_l1        = PMD_TYPE_TABLE,
 243                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
 244                 .domain         = DOMAIN_IO,
 245         },
 246         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 247                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 248                 .prot_l1        = PMD_TYPE_TABLE,
 249                 .prot_sect      = PROT_SECT_DEVICE,
 250                 .domain         = DOMAIN_IO,
 251         },
 252         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
 253                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 254                 .prot_l1        = PMD_TYPE_TABLE,
 255                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
 256                 .domain         = DOMAIN_IO,
 257         },
 258         [MT_DEVICE_WC] = {      /* ioremap_wc */
 259                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 260                 .prot_l1        = PMD_TYPE_TABLE,
 261                 .prot_sect      = PROT_SECT_DEVICE,
 262                 .domain         = DOMAIN_IO,
 263         },
 264         [MT_UNCACHED] = {
 265                 .prot_pte       = PROT_PTE_DEVICE,
 266                 .prot_l1        = PMD_TYPE_TABLE,
 267                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
 268                 .domain         = DOMAIN_IO,
 269         },
 270         [MT_CACHECLEAN] = {
 271                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 272                 .domain    = DOMAIN_KERNEL,
 273         },
 274 #ifndef CONFIG_ARM_LPAE
 275         [MT_MINICLEAN] = {
 276                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 277                 .domain    = DOMAIN_KERNEL,
 278         },
 279 #endif
 280         [MT_LOW_VECTORS] = {
 281                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 282                                 L_PTE_RDONLY,
 283                 .prot_l1   = PMD_TYPE_TABLE,
 284                 .domain    = DOMAIN_USER,
 285         },
 286         [MT_HIGH_VECTORS] = {
 287                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 288                                 L_PTE_USER | L_PTE_RDONLY,
 289                 .prot_l1   = PMD_TYPE_TABLE,
 290                 .domain    = DOMAIN_USER,
 291         },
 292         [MT_MEMORY] = {
 293                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 294                 .prot_l1   = PMD_TYPE_TABLE,
 295                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 296                 .domain    = DOMAIN_KERNEL,
 297         },
 298         [MT_ROM] = {
 299                 .prot_sect = PMD_TYPE_SECT,
 300                 .domain    = DOMAIN_KERNEL,
 301         },
 302         [MT_MEMORY_NONCACHED] = {
 303                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 304                                 L_PTE_MT_BUFFERABLE,
 305                 .prot_l1   = PMD_TYPE_TABLE,
 306                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 307                 .domain    = DOMAIN_KERNEL,
 308         },
 309         [MT_MEMORY_DTCM] = {
 310                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 311                                 L_PTE_XN,
 312                 .prot_l1   = PMD_TYPE_TABLE,
 313                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 314                 .domain    = DOMAIN_KERNEL,
 315         },
 316         [MT_MEMORY_ITCM] = {
 317                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 318                 .prot_l1   = PMD_TYPE_TABLE,
 319                 .domain    = DOMAIN_KERNEL,
 320         },
 321         [MT_MEMORY_SO] = {
 322                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 323                                 L_PTE_MT_UNCACHED | L_PTE_XN,
 324                 .prot_l1   = PMD_TYPE_TABLE,
 325                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
 326                                 PMD_SECT_UNCACHED | PMD_SECT_XN,
 327                 .domain    = DOMAIN_KERNEL,
 328         },
 329         [MT_MEMORY_DMA_READY] = {
 330                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
 331                 .prot_l1   = PMD_TYPE_TABLE,
 332                 .domain    = DOMAIN_KERNEL,
 333         },
 334 };
 335
 336 const struct mem_type *get_mem_type(unsigned int type)
 337 {
 338         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 339 }
 340 EXPORT_SYMBOL(get_mem_type);
 341
 342 /*
 343  * Adjust the PMD section entries according to the CPU in use.
 344  */
 345 static void __init build_mem_type_table(void)
 346 {
 347         struct cachepolicy *cp;
 348         unsigned int cr = get_cr();
 349         pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
 350         pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
 351         int cpu_arch = cpu_architecture();
 352         int i;
 353
 354         if (cpu_arch < CPU_ARCH_ARMv6) {
 355 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 356                 if (cachepolicy > CPOLICY_BUFFERED)
 357                         cachepolicy = CPOLICY_BUFFERED;
 358 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 359                 if (cachepolicy > CPOLICY_WRITETHROUGH)
 360                         cachepolicy = CPOLICY_WRITETHROUGH;
 361 #endif
 362         }
 363         if (cpu_arch < CPU_ARCH_ARMv5) {
 364                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 365                         cachepolicy = CPOLICY_WRITEBACK;
 366                 ecc_mask = 0;
 367         }
 368         if (is_smp())
 369                 cachepolicy = CPOLICY_WRITEALLOC;
 370
 371         /*
 372          * Strip out features not present on earlier architectures.
 373          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 374          * without extended page tables don't have the 'Shared' bit.
 375          */
 376         if (cpu_arch < CPU_ARCH_ARMv5)
 377                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 378                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 379         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 380                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 381                         mem_types[i].prot_sect &= ~PMD_SECT_S;
 382
 383         /*
 384          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 385          * "update-able on write" bit on ARM610).  However, Xscale and
 386          * Xscale3 require this bit to be cleared.
 387          */
 388         if (cpu_is_xscale() || cpu_is_xsc3()) {
 389                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 390                         mem_types[i].prot_sect &= ~PMD_BIT4;
 391                         mem_types[i].prot_l1 &= ~PMD_BIT4;
 392                 }
 393         } else if (cpu_arch < CPU_ARCH_ARMv6) {
 394                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 395                         if (mem_types[i].prot_l1)
 396                                 mem_types[i].prot_l1 |= PMD_BIT4;
 397                         if (mem_types[i].prot_sect)
 398                                 mem_types[i].prot_sect |= PMD_BIT4;
 399                 }
 400         }
 401
 402         /*
 403          * Mark the device areas according to the CPU/architecture.
 404          */
 405         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 406                 if (!cpu_is_xsc3()) {
 407                         /*
 408                          * Mark device regions on ARMv6+ as execute-never
 409                          * to prevent speculative instruction fetches.
 410                          */
 411                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 412                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 413                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 414                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 415                 }
 416                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 417                         /*
 418                          * For ARMv7 with TEX remapping,
 419                          * - shared device is SXCB=1100
 420                          * - nonshared device is SXCB=0100
 421                          * - write combine device mem is SXCB=0001
 422                          * (Uncached Normal memory)
 423                          */
 424                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 425                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 426                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 427                 } else if (cpu_is_xsc3()) {
 428                         /*
 429                          * For Xscale3,
 430                          * - shared device is TEXCB=00101
 431                          * - nonshared device is TEXCB=01000
 432                          * - write combine device mem is TEXCB=00100
 433                          * (Inner/Outer Uncacheable in xsc3 parlance)
 434                          */
 435                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 436                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 437                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 438                 } else {
 439                         /*
 440                          * For ARMv6 and ARMv7 without TEX remapping,
 441                          * - shared device is TEXCB=00001
 442                          * - nonshared device is TEXCB=01000
 443                          * - write combine device mem is TEXCB=00100
 444                          * (Uncached Normal in ARMv6 parlance).
 445                          */
 446                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 447                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 448                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 449                 }
 450         } else {
 451                 /*
 452                  * On others, write combining is "Uncached/Buffered"
 453                  */
 454                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 455         }
 456
 457         /*
 458          * Now deal with the memory-type mappings
 459          */
 460         cp = &cache_policies[cachepolicy];
 461         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 462         s2_pgprot = cp->pte_s2;
 463         hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
 464         s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
 465
 466         /*
 467          * ARMv6 and above have extended page tables.
 468          */
 469         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 470 #ifndef CONFIG_ARM_LPAE
 471                 /*
 472                  * Mark cache clean areas and XIP ROM read only
 473                  * from SVC mode and no access from userspace.
 474                  */
 475                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 476                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 477                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 478 #endif
 479
 480                 if (is_smp()) {
 481                         /*
 482                          * Mark memory with the "shared" attribute
 483                          * for SMP systems
 484                          */
 485                         user_pgprot |= L_PTE_SHARED;
 486                         kern_pgprot |= L_PTE_SHARED;
 487                         vecs_pgprot |= L_PTE_SHARED;
 488                         s2_pgprot |= L_PTE_SHARED;
 489                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
 490                         mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
 491                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
 492                         mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
 493                         mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 494                         mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED;
 495                         mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
 496                         mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 497                         mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED;
 498                 }
 499         }
 500
 501         /*
 502          * Non-cacheable Normal - intended for memory areas that must
 503          * not cause dirty cache line writebacks when used
 504          */
 505         if (cpu_arch >= CPU_ARCH_ARMv6) {
 506                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 507                         /* Non-cacheable Normal is XCB = 001 */
 508                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 509                                 PMD_SECT_BUFFERED;
 510                 } else {
 511                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
 512                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 513                                 PMD_SECT_TEX(1);
 514                 }
 515         } else {
 516                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 517         }
 518
 519 #ifdef CONFIG_ARM_LPAE
 520         /*
 521          * Do not generate access flag faults for the kernel mappings.
 522          */
 523         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 524                 mem_types[i].prot_pte |= PTE_EXT_AF;
 525                 if (mem_types[i].prot_sect)
 526                         mem_types[i].prot_sect |= PMD_SECT_AF;
 527         }
 528         kern_pgprot |= PTE_EXT_AF;
 529         vecs_pgprot |= PTE_EXT_AF;
 530 #endif
 531
 532         for (i = 0; i < 16; i++) {
 533                 pteval_t v = pgprot_val(protection_map[i]);
 534                 protection_map[i] = __pgprot(v | user_pgprot);
 535         }
 536
 537         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 538         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 539
 540         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 541         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 542                                  L_PTE_DIRTY | kern_pgprot);
 543         pgprot_s2  = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
 544         pgprot_s2_device  = __pgprot(s2_device_pgprot);
 545         pgprot_hyp_device  = __pgprot(hyp_device_pgprot);
 546
 547         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 548         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 549         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 550         mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
 551         mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
 552         mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask;
 553         mem_types[MT_ROM].prot_sect |= cp->pmd;
 554
 555         switch (cp->pmd) {
 556         case PMD_SECT_WT:
 557                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 558                 break;
 559         case PMD_SECT_WB:
 560         case PMD_SECT_WBWA:
 561                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 562                 break;
 563         }
 564         printk("Memory policy: ECC %sabled, Data cache %s\n",
 565                 ecc_mask ? "en" : "dis", cp->policy);
 566
 567         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 568                 struct mem_type *t = &mem_types[i];
 569                 if (t->prot_l1)
 570                         t->prot_l1 |= PMD_DOMAIN(t->domain);
 571                 if (t->prot_sect)
 572                         t->prot_sect |= PMD_DOMAIN(t->domain);
 573         }
 574 }
 575
 576 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 577 pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 578                               unsigned long size, pgprot_t vma_prot)
 579 {
 580         if (!pfn_valid(pfn))
 581                 return pgprot_noncached(vma_prot);
 582         else if (file->f_flags & O_SYNC)
 583                 return pgprot_writecombine(vma_prot);
 584         return vma_prot;
 585 }
 586 EXPORT_SYMBOL(phys_mem_access_prot);
 587 #endif
 588
 589 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 590
 591 static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
 592 {
 593         void *ptr = __va(memblock_alloc(sz, align));
 594         memset(ptr, 0, sz);
 595         return ptr;
 596 }
 597
 598 static void __init *early_alloc(unsigned long sz)
 599 {
 600         return early_alloc_aligned(sz, sz);
 601 }
 602
 603 static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot)
 604 {
 605         if (pmd_none(*pmd)) {
 606                 pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
 607                 __pmd_populate(pmd, __pa(pte), prot);
 608         }
 609         BUG_ON(pmd_bad(*pmd));
 610         return pte_offset_kernel(pmd, addr);
 611 }
 612
 613 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 614                                   unsigned long end, unsigned long pfn,
 615                                   const struct mem_type *type)
 616 {
 617         pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1);
 618         do {
 619                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
 620                 pfn++;
 621         } while (pte++, addr += PAGE_SIZE, addr != end);
 622 }
 623
 624 static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
 625                         unsigned long end, phys_addr_t phys,
 626                         const struct mem_type *type)
 627 {
 628         pmd_t *p = pmd;
 629
 630 #ifndef CONFIG_ARM_LPAE
 631         /*
 632          * In classic MMU format, puds and pmds are folded in to
 633          * the pgds. pmd_offset gives the PGD entry. PGDs refer to a
 634          * group of L1 entries making up one logical pointer to
 635          * an L2 table (2MB), where as PMDs refer to the individual
 636          * L1 entries (1MB). Hence increment to get the correct
 637          * offset for odd 1MB sections.
 638          * (See arch/arm/include/asm/pgtable-2level.h)
 639          */
 640         if (addr & SECTION_SIZE)
 641                 pmd++;
 642 #endif
 643         do {
 644                 *pmd = __pmd(phys | type->prot_sect);
 645                 phys += SECTION_SIZE;
 646         } while (pmd++, addr += SECTION_SIZE, addr != end);
 647
 648         flush_pmd_entry(p);
 649 }
 650
 651 static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
 652                                       unsigned long end, phys_addr_t phys,
 653                                       const struct mem_type *type)
 654 {
 655         pmd_t *pmd = pmd_offset(pud, addr);
 656         unsigned long next;
 657
 658         do {
 659                 /*
 660                  * With LPAE, we must loop over to map
 661                  * all the pmds for the given range.
 662                  */
 663                 next = pmd_addr_end(addr, end);
 664
 665                 /*
 666                  * Try a section mapping - addr, next and phys must all be
 667                  * aligned to a section boundary.
 668                  */
 669                 if (type->prot_sect &&
 670                                 ((addr | next | phys) & ~SECTION_MASK) == 0) {
 671                         __map_init_section(pmd, addr, next, phys, type);
 672                 } else {
 673                         alloc_init_pte(pmd, addr, next,
 674                                                 __phys_to_pfn(phys), type);
 675                 }
 676
 677                 phys += next - addr;
 678
 679         } while (pmd++, addr = next, addr != end);
 680 }
 681
 682 static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
 683                                   unsigned long end, phys_addr_t phys,
 684                                   const struct mem_type *type)
 685 {
 686         pud_t *pud = pud_offset(pgd, addr);
 687         unsigned long next;
 688
 689         do {
 690                 next = pud_addr_end(addr, end);
 691                 alloc_init_pmd(pud, addr, next, phys, type);
 692                 phys += next - addr;
 693         } while (pud++, addr = next, addr != end);
 694 }
 695
 696 #ifndef CONFIG_ARM_LPAE
 697 static void __init create_36bit_mapping(struct map_desc *md,
 698                                         const struct mem_type *type)
 699 {
 700         unsigned long addr, length, end;
 701         phys_addr_t phys;
 702         pgd_t *pgd;
 703
 704         addr = md->virtual;
 705         phys = __pfn_to_phys(md->pfn);
 706         length = PAGE_ALIGN(md->length);
 707
 708         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 709                 printk(KERN_ERR "MM: CPU does not support supersection "
 710                        "mapping for 0x%08llx at 0x%08lx\n",
 711                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 712                 return;
 713         }
 714
 715         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 716          *      Since domain assignments can in fact be arbitrary, the
 717          *      'domain == 0' check below is required to insure that ARMv6
 718          *      supersections are only allocated for domain 0 regardless
 719          *      of the actual domain assignments in use.
 720          */
 721         if (type->domain) {
 722                 printk(KERN_ERR "MM: invalid domain in supersection "
 723                        "mapping for 0x%08llx at 0x%08lx\n",
 724                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 725                 return;
 726         }
 727
 728         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 729                 printk(KERN_ERR "MM: cannot create mapping for 0x%08llx"
 730                        " at 0x%08lx invalid alignment\n",
 731                        (long long)__pfn_to_phys((u64)md->pfn), addr);
 732                 return;
 733         }
 734
 735         /*
 736          * Shift bits [35:32] of address into bits [23:20] of PMD
 737          * (See ARMv6 spec).
 738          */
 739         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 740
 741         pgd = pgd_offset_k(addr);
 742         end = addr + length;
 743         do {
 744                 pud_t *pud = pud_offset(pgd, addr);
 745                 pmd_t *pmd = pmd_offset(pud, addr);
 746                 int i;
 747
 748                 for (i = 0; i < 16; i++)
 749                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
 750
 751                 addr += SUPERSECTION_SIZE;
 752                 phys += SUPERSECTION_SIZE;
 753                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 754         } while (addr != end);
 755 }
 756 #endif  /* !CONFIG_ARM_LPAE */
 757
 758 /*
 759  * Create the page directory entries and any necessary
 760  * page tables for the mapping specified by `md'.  We
 761  * are able to cope here with varying sizes and address
 762  * offsets, and we take full advantage of sections and
 763  * supersections.
 764  */
 765 static void __init create_mapping(struct map_desc *md)
 766 {
 767         unsigned long addr, length, end;
 768         phys_addr_t phys;
 769         const struct mem_type *type;
 770         pgd_t *pgd;
 771
 772         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 773                 printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx"
 774                        " at 0x%08lx in user region\n",
 775                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 776                 return;
 777         }
 778
 779         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 780             md->virtual >= PAGE_OFFSET &&
 781             (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
 782                 printk(KERN_WARNING "BUG: mapping for 0x%08llx"
 783                        " at 0x%08lx out of vmalloc space\n",
 784                        (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
 785         }
 786
 787         type = &mem_types[md->type];
 788
 789 #ifndef CONFIG_ARM_LPAE
 790         /*
 791          * Catch 36-bit addresses
 792          */
 793         if (md->pfn >= 0x100000) {
 794                 create_36bit_mapping(md, type);
 795                 return;
 796         }
 797 #endif
 798
 799         addr = md->virtual & PAGE_MASK;
 800         phys = __pfn_to_phys(md->pfn);
 801         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 802
 803         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 804                 printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not "
 805                        "be mapped using pages, ignoring.\n",
 806                        (long long)__pfn_to_phys(md->pfn), addr);
 807                 return;
 808         }
 809
 810         pgd = pgd_offset_k(addr);
 811         end = addr + length;
 812         do {
 813                 unsigned long next = pgd_addr_end(addr, end);
 814
 815                 alloc_init_pud(pgd, addr, next, phys, type);
 816
 817                 phys += next - addr;
 818                 addr = next;
 819         } while (pgd++, addr != end);
 820 }
 821
 822 /*
 823  * Create the architecture specific mappings
 824  */
 825 void __init iotable_init(struct map_desc *io_desc, int nr)
 826 {
 827         struct map_desc *md;
 828         struct vm_struct *vm;
 829         struct static_vm *svm;
 830
 831         if (!nr)
 832                 return;
 833
 834         svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
 835
 836         for (md = io_desc; nr; md++, nr--) {
 837                 create_mapping(md);
 838
 839                 vm = &svm->vm;
 840                 vm->addr = (void *)(md->virtual & PAGE_MASK);
 841                 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 842                 vm->phys_addr = __pfn_to_phys(md->pfn);
 843                 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
 844                 vm->flags |= VM_ARM_MTYPE(md->type);
 845                 vm->caller = iotable_init;
 846                 add_static_vm_early(svm++);
 847         }
 848 }
 849
 850 void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
 851                                   void *caller)
 852 {
 853         struct vm_struct *vm;
 854         struct static_vm *svm;
 855
 856         svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
 857
 858         vm = &svm->vm;
 859         vm->addr = (void *)addr;
 860         vm->size = size;
 861         vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
 862         vm->caller = caller;
 863         add_static_vm_early(svm);
 864 }
 865
 866 #ifndef CONFIG_ARM_LPAE
 867
 868 /*
 869  * The Linux PMD is made of two consecutive section entries covering 2MB
 870  * (see definition in include/asm/pgtable-2level.h).  However a call to
 871  * create_mapping() may optimize static mappings by using individual
 872  * 1MB section mappings.  This leaves the actual PMD potentially half
 873  * initialized if the top or bottom section entry isn't used, leaving it
 874  * open to problems if a subsequent ioremap() or vmalloc() tries to use
 875  * the virtual space left free by that unused section entry.
 876  *
 877  * Let's avoid the issue by inserting dummy vm entries covering the unused
 878  * PMD halves once the static mappings are in place.
 879  */
 880
 881 static void __init pmd_empty_section_gap(unsigned long addr)
 882 {
 883         vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
 884 }
 885
 886 static void __init fill_pmd_gaps(void)
 887 {
 888         struct static_vm *svm;
 889         struct vm_struct *vm;
 890         unsigned long addr, next = 0;
 891         pmd_t *pmd;
 892
 893         list_for_each_entry(svm, &static_vmlist, list) {
 894                 vm = &svm->vm;
 895                 addr = (unsigned long)vm->addr;
 896                 if (addr < next)
 897                         continue;
 898
 899                 /*
 900                  * Check if this vm starts on an odd section boundary.
 901                  * If so and the first section entry for this PMD is free
 902                  * then we block the corresponding virtual address.
 903                  */
 904                 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
 905                         pmd = pmd_off_k(addr);
 906                         if (pmd_none(*pmd))
 907                                 pmd_empty_section_gap(addr & PMD_MASK);
 908                 }
 909
 910                 /*
 911                  * Then check if this vm ends on an odd section boundary.
 912                  * If so and the second section entry for this PMD is empty
 913                  * then we block the corresponding virtual address.
 914                  */
 915                 addr += vm->size;
 916                 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
 917                         pmd = pmd_off_k(addr) + 1;
 918                         if (pmd_none(*pmd))
 919                                 pmd_empty_section_gap(addr);
 920                 }
 921
 922                 /* no need to look at any vm entry until we hit the next PMD */
 923                 next = (addr + PMD_SIZE - 1) & PMD_MASK;
 924         }
 925 }
 926
 927 #else
 928 #define fill_pmd_gaps() do { } while (0)
 929 #endif
 930
 931 #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
 932 static void __init pci_reserve_io(void)
 933 {
 934         struct static_vm *svm;
 935
 936         svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
 937         if (svm)
 938                 return;
 939
 940         vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
 941 }
 942 #else
 943 #define pci_reserve_io() do { } while (0)
 944 #endif
 945
 946 #ifdef CONFIG_DEBUG_LL
 947 void __init debug_ll_io_init(void)
 948 {
 949         struct map_desc map;
 950
 951         debug_ll_addr(&map.pfn, &map.virtual);
 952         if (!map.pfn || !map.virtual)
 953                 return;
 954         map.pfn = __phys_to_pfn(map.pfn);
 955         map.virtual &= PAGE_MASK;
 956         map.length = PAGE_SIZE;
 957         map.type = MT_DEVICE;
 958         iotable_init(&map, 1);
 959 }
 960 #endif
 961
 962 static void * __initdata vmalloc_min =
 963         (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
 964
 965 /*
 966  * vmalloc=size forces the vmalloc area to be exactly 'size'
 967  * bytes. This can be used to increase (or decrease) the vmalloc
 968  * area - the default is 240m.
 969  */
 970 static int __init early_vmalloc(char *arg)
 971 {
 972         unsigned long vmalloc_reserve = memparse(arg, NULL);
 973
 974         if (vmalloc_reserve < SZ_16M) {
 975                 vmalloc_reserve = SZ_16M;
 976                 printk(KERN_WARNING
 977                         "vmalloc area too small, limiting to %luMB\n",
 978                         vmalloc_reserve >> 20);
 979         }
 980
 981         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
 982                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
 983                 printk(KERN_WARNING
 984                         "vmalloc area is too big, limiting to %luMB\n",
 985                         vmalloc_reserve >> 20);
 986         }
 987
 988         vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
 989         return 0;
 990 }
 991 early_param("vmalloc", early_vmalloc);
 992
 993 phys_addr_t arm_lowmem_limit __initdata = 0;
 994
 995 void __init sanity_check_meminfo(void)
 996 {
 997         phys_addr_t memblock_limit = 0;
 998         int i, j, highmem = 0;
 999         phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
1000
1001         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
1002                 struct membank *bank = &meminfo.bank[j];
1003                 phys_addr_t size_limit;
1004
1005                 *bank = meminfo.bank[i];
1006                 size_limit = bank->size;
1007
1008                 if (bank->start >= vmalloc_limit)
1009                         highmem = 1;
1010                 else
1011                         size_limit = vmalloc_limit - bank->start;
1012
1013                 bank->highmem = highmem;
1014
1015 #ifdef CONFIG_HIGHMEM
1016                 /*
1017                  * Split those memory banks which are partially overlapping
1018                  * the vmalloc area greatly simplifying things later.
1019                  */
1020                 if (!highmem && bank->size > size_limit) {
1021                         if (meminfo.nr_banks >= NR_BANKS) {
1022                                 printk(KERN_CRIT "NR_BANKS too low, "
1023                                                  "ignoring high memory\n");
1024                         } else {
1025                                 memmove(bank + 1, bank,
1026                                         (meminfo.nr_banks - i) * sizeof(*bank));
1027                                 meminfo.nr_banks++;
1028                                 i++;
1029                                 bank[1].size -= size_limit;
1030                                 bank[1].start = vmalloc_limit;
1031                                 bank[1].highmem = highmem = 1;
1032                                 j++;
1033                         }
1034                         bank->size = size_limit;
1035                 }
1036 #else
1037                 /*
1038                  * Highmem banks not allowed with !CONFIG_HIGHMEM.
1039                  */
1040                 if (highmem) {
1041                         printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
1042                                "(!CONFIG_HIGHMEM).\n",
1043                                (unsigned long long)bank->start,
1044                                (unsigned long long)bank->start + bank->size - 1);
1045                         continue;
1046                 }
1047
1048                 /*
1049                  * Check whether this memory bank would partially overlap
1050                  * the vmalloc area.
1051                  */
1052                 if (bank->size > size_limit) {
1053                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
1054                                "to -%.8llx (vmalloc region overlap).\n",
1055                                (unsigned long long)bank->start,
1056                                (unsigned long long)bank->start + bank->size - 1,
1057                                (unsigned long long)bank->start + size_limit - 1);
1058                         bank->size = size_limit;
1059                 }
1060 #endif
1061                 if (!bank->highmem) {
1062                         phys_addr_t bank_end = bank->start + bank->size;
1063
1064                         if (bank_end > arm_lowmem_limit)
1065                                 arm_lowmem_limit = bank_end;
1066
1067                         /*
1068                          * Find the first non-section-aligned page, and point
1069                          * memblock_limit at it. This relies on rounding the
1070                          * limit down to be section-aligned, which happens at
1071                          * the end of this function.
1072                          *
1073                          * With this algorithm, the start or end of almost any
1074                          * bank can be non-section-aligned. The only exception
1075                          * is that the start of the bank 0 must be section-
1076                          * aligned, since otherwise memory would need to be
1077                          * allocated when mapping the start of bank 0, which
1078                          * occurs before any free memory is mapped.
1079                          */
1080                         if (!memblock_limit) {
1081                                 if (!IS_ALIGNED(bank->start, SECTION_SIZE))
1082                                         memblock_limit = bank->start;
1083                                 else if (!IS_ALIGNED(bank_end, SECTION_SIZE))
1084                                         memblock_limit = bank_end;
1085                         }
1086                 }
1087                 j++;
1088         }
1089 #ifdef CONFIG_HIGHMEM
1090         if (highmem) {
1091                 const char *reason = NULL;
1092
1093                 if (cache_is_vipt_aliasing()) {
1094                         /*
1095                          * Interactions between kmap and other mappings
1096                          * make highmem support with aliasing VIPT caches
1097                          * rather difficult.
1098                          */
1099                         reason = "with VIPT aliasing cache";
1100                 }
1101                 if (reason) {
1102                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
1103                                 reason);
1104                         while (j > 0 && meminfo.bank[j - 1].highmem)
1105                                 j--;
1106                 }
1107         }
1108 #endif
1109         meminfo.nr_banks = j;
1110         high_memory = __va(arm_lowmem_limit - 1) + 1;
1111
1112         /*
1113          * Round the memblock limit down to a section size.  This
1114          * helps to ensure that we will allocate memory from the
1115          * last full section, which should be mapped.
1116          */
1117         if (memblock_limit)
1118                 memblock_limit = round_down(memblock_limit, SECTION_SIZE);
1119         if (!memblock_limit)
1120                 memblock_limit = arm_lowmem_limit;
1121
1122         memblock_set_current_limit(memblock_limit);
1123 }
1124
1125 static inline void prepare_page_table(void)
1126 {
1127         unsigned long addr;
1128         phys_addr_t end;
1129
1130         /*
1131          * Clear out all the mappings below the kernel image.
1132          */
1133         for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1134                 pmd_clear(pmd_off_k(addr));
1135
1136 #ifdef CONFIG_XIP_KERNEL
1137         /* The XIP kernel is mapped in the module area -- skip over it */
1138         addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK;
1139 #endif
1140         for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1141                 pmd_clear(pmd_off_k(addr));
1142
1143         /*
1144          * Find the end of the first block of lowmem.
1145          */
1146         end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1147         if (end >= arm_lowmem_limit)
1148                 end = arm_lowmem_limit;
1149
1150         /*
1151          * Clear out all the kernel space mappings, except for the first
1152          * memory bank, up to the vmalloc region.
1153          */
1154         for (addr = __phys_to_virt(end);
1155              addr < VMALLOC_START; addr += PMD_SIZE)
1156                 pmd_clear(pmd_off_k(addr));
1157 }
1158
1159 #ifdef CONFIG_ARM_LPAE
1160 /* the first page is reserved for pgd */
1161 #define SWAPPER_PG_DIR_SIZE     (PAGE_SIZE + \
1162                                  PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1163 #else
1164 #define SWAPPER_PG_DIR_SIZE     (PTRS_PER_PGD * sizeof(pgd_t))
1165 #endif
1166
1167 /*
1168  * Reserve the special regions of memory
1169  */
1170 void __init arm_mm_memblock_reserve(void)
1171 {
1172         /*
1173          * Reserve the page tables.  These are already in use,
1174          * and can only be in node 0.
1175          */
1176         memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1177
1178 #ifdef CONFIG_SA1111
1179         /*
1180          * Because of the SA1111 DMA bug, we want to preserve our
1181          * precious DMA-able memory...
1182          */
1183         memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1184 #endif
1185 }
1186
1187 /*
1188  * Set up the device mappings.  Since we clear out the page tables for all
1189  * mappings above VMALLOC_START, we will remove any debug device mappings.
1190  * This means you have to be careful how you debug this function, or any
1191  * called function.  This means you can't use any function or debugging
1192  * method which may touch any device, otherwise the kernel _will_ crash.
1193  */
1194 static void __init devicemaps_init(const struct machine_desc *mdesc)
1195 {
1196         struct map_desc map;
1197         unsigned long addr;
1198         void *vectors;
1199
1200         /*
1201          * Allocate the vector page early.
1202          */
1203         vectors = early_alloc(PAGE_SIZE * 2);
1204
1205         early_trap_init(vectors);
1206
1207         for (addr = VMALLOC_START; addr; addr += PMD_SIZE)
1208                 pmd_clear(pmd_off_k(addr));
1209
1210         /*
1211          * Map the kernel if it is XIP.
1212          * It is always first in the modulearea.
1213          */
1214 #ifdef CONFIG_XIP_KERNEL
1215         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1216         map.virtual = MODULES_VADDR;
1217         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1218         map.type = MT_ROM;
1219         create_mapping(&map);
1220 #endif
1221
1222         /*
1223          * Map the cache flushing regions.
1224          */
1225 #ifdef FLUSH_BASE
1226         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1227         map.virtual = FLUSH_BASE;
1228         map.length = SZ_1M;
1229         map.type = MT_CACHECLEAN;
1230         create_mapping(&map);
1231 #endif
1232 #ifdef FLUSH_BASE_MINICACHE
1233         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1234         map.virtual = FLUSH_BASE_MINICACHE;
1235         map.length = SZ_1M;
1236         map.type = MT_MINICLEAN;
1237         create_mapping(&map);
1238 #endif
1239
1240         /*
1241          * Create a mapping for the machine vectors at the high-vectors
1242          * location (0xffff0000).  If we aren't using high-vectors, also
1243          * create a mapping at the low-vectors virtual address.
1244          */
1245         map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1246         map.virtual = 0xffff0000;
1247         map.length = PAGE_SIZE;
1248 #ifdef CONFIG_KUSER_HELPERS
1249         map.type = MT_HIGH_VECTORS;
1250 #else
1251         map.type = MT_LOW_VECTORS;
1252 #endif
1253         create_mapping(&map);
1254
1255         if (!vectors_high()) {
1256                 map.virtual = 0;
1257                 map.length = PAGE_SIZE * 2;
1258                 map.type = MT_LOW_VECTORS;
1259                 create_mapping(&map);
1260         }
1261
1262         /* Now create a kernel read-only mapping */
1263         map.pfn += 1;
1264         map.virtual = 0xffff0000 + PAGE_SIZE;
1265         map.length = PAGE_SIZE;
1266         map.type = MT_LOW_VECTORS;
1267         create_mapping(&map);
1268
1269         /*
1270          * Ask the machine support to map in the statically mapped devices.
1271          */
1272         if (mdesc->map_io)
1273                 mdesc->map_io();
1274         else
1275                 debug_ll_io_init();
1276         fill_pmd_gaps();
1277
1278         /* Reserve fixed i/o space in VMALLOC region */
1279         pci_reserve_io();
1280
1281         /*
1282          * Finally flush the caches and tlb to ensure that we're in a
1283          * consistent state wrt the writebuffer.  This also ensures that
1284          * any write-allocated cache lines in the vector page are written
1285          * back.  After this point, we can start to touch devices again.
1286          */
1287         local_flush_tlb_all();
1288         flush_cache_all();
1289 }
1290
1291 static void __init kmap_init(void)
1292 {
1293 #ifdef CONFIG_HIGHMEM
1294         pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1295                 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1296 #endif
1297 }
1298
1299 static void __init map_lowmem(void)
1300 {
1301         struct memblock_region *reg;
1302
1303         /* Map all the lowmem memory banks. */
1304         for_each_memblock(memory, reg) {
1305                 phys_addr_t start = reg->base;
1306                 phys_addr_t end = start + reg->size;
1307                 struct map_desc map;
1308
1309                 if (end > arm_lowmem_limit)
1310                         end = arm_lowmem_limit;
1311                 if (start >= end)
1312                         break;
1313
1314                 map.pfn = __phys_to_pfn(start);
1315                 map.virtual = __phys_to_virt(start);
1316                 map.length = end - start;
1317                 map.type = MT_MEMORY;
1318
1319                 create_mapping(&map);
1320         }
1321 }
1322
1323 /*
1324  * paging_init() sets up the page tables, initialises the zone memory
1325  * maps, and sets up the zero page, bad page and bad page tables.
1326  */
1327 void __init paging_init(const struct machine_desc *mdesc)
1328 {
1329         void *zero_page;
1330
1331         build_mem_type_table();
1332         prepare_page_table();
1333         map_lowmem();
1334         dma_contiguous_remap();
1335         devicemaps_init(mdesc);
1336         kmap_init();
1337         tcm_init();
1338
1339         top_pmd = pmd_off_k(0xffff0000);
1340
1341         /* allocate the zero page. */
1342         zero_page = early_alloc(PAGE_SIZE);
1343
1344         bootmem_init();
1345
1346         empty_zero_page = virt_to_page(zero_page);
1347         __flush_dcache_page(NULL, empty_zero_page);
1348 }