arch/arm/mach-shmobile/setup-r8a7778.c

   1 /*
   2  * r8a7778 processor support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  * Copyright (C) 2013  Cogent Embedded, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/irqchip/arm-gic.h>
  25 #include <linux/of.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/irqchip.h>
  30 #include <linux/serial_sci.h>
  31 #include <linux/sh_timer.h>
  32 #include <mach/irqs.h>
  33 #include <mach/r8a7778.h>
  34 #include <mach/common.h>
  35 #include <asm/mach/arch.h>
  36 #include <asm/hardware/cache-l2x0.h>
  37
  38 /* SCIF */
  39 #define SCIF_INFO(baseaddr, irq)                                \
  40 {                                                               \
  41         .mapbase        = baseaddr,                             \
  42         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
  43         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,     \
  44         .scbrr_algo_id  = SCBRR_ALGO_2,                         \
  45         .type           = PORT_SCIF,                            \
  46         .irqs           = SCIx_IRQ_MUXED(irq),                  \
  47 }
  48
  49 static struct plat_sci_port scif_platform_data[] = {
  50         SCIF_INFO(0xffe40000, gic_iid(0x66)),
  51         SCIF_INFO(0xffe41000, gic_iid(0x67)),
  52         SCIF_INFO(0xffe42000, gic_iid(0x68)),
  53         SCIF_INFO(0xffe43000, gic_iid(0x69)),
  54         SCIF_INFO(0xffe44000, gic_iid(0x6a)),
  55         SCIF_INFO(0xffe45000, gic_iid(0x6b)),
  56 };
  57
  58 /* TMU */
  59 static struct resource sh_tmu0_resources[] = {
  60         DEFINE_RES_MEM(0xffd80008, 12),
  61         DEFINE_RES_IRQ(gic_iid(0x40)),
  62 };
  63
  64 static struct sh_timer_config sh_tmu0_platform_data = {
  65         .name                   = "TMU00",
  66         .channel_offset         = 0x4,
  67         .timer_bit              = 0,
  68         .clockevent_rating      = 200,
  69 };
  70
  71 static struct resource sh_tmu1_resources[] = {
  72         DEFINE_RES_MEM(0xffd80014, 12),
  73         DEFINE_RES_IRQ(gic_iid(0x41)),
  74 };
  75
  76 static struct sh_timer_config sh_tmu1_platform_data = {
  77         .name                   = "TMU01",
  78         .channel_offset         = 0x10,
  79         .timer_bit              = 1,
  80         .clocksource_rating     = 200,
  81 };
  82
  83 /* Ether */
  84 static struct resource ether_resources[] = {
  85         DEFINE_RES_MEM(0xfde00000, 0x400),
  86         DEFINE_RES_IRQ(gic_iid(0x89)),
  87 };
  88
  89 #define r8a7778_register_tmu(idx)                       \
  90         platform_device_register_resndata(              \
  91                 &platform_bus, "sh_tmu", idx,           \
  92                 sh_tmu##idx##_resources,                \
  93                 ARRAY_SIZE(sh_tmu##idx##_resources),    \
  94                 &sh_tmu##idx##_platform_data,           \
  95                 sizeof(sh_tmu##idx##_platform_data))
  96
  97 void __init r8a7778_add_standard_devices(void)
  98 {
  99         int i;
 100
 101 #ifdef CONFIG_CACHE_L2X0
 102         void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
 103         if (base) {
 104                 /*
 105                  * Early BRESP enable, Shared attribute override enable, 64K*16way
 106                  * don't call iounmap(base)
 107                  */
 108                 l2x0_init(base, 0x40470000, 0x82000fff);
 109         }
 110 #endif
 111
 112         for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
 113                 platform_device_register_data(&platform_bus, "sh-sci", i,
 114                                               &scif_platform_data[i],
 115                                               sizeof(struct plat_sci_port));
 116
 117         r8a7778_register_tmu(0);
 118         r8a7778_register_tmu(1);
 119 }
 120
 121 void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
 122 {
 123         platform_device_register_resndata(&platform_bus, "sh_eth", -1,
 124                                           ether_resources,
 125                                           ARRAY_SIZE(ether_resources),
 126                                           pdata, sizeof(*pdata));
 127 }
 128
 129 static struct renesas_intc_irqpin_config irqpin_platform_data = {
 130         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
 131         .sense_bitfield_width = 2,
 132 };
 133
 134 static struct resource irqpin_resources[] = {
 135         DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
 136         DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
 137         DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
 138         DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
 139         DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
 140         DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
 141         DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
 142         DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
 143         DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
 144 };
 145
 146 void __init r8a7778_init_irq_extpin(int irlm)
 147 {
 148         void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
 149         unsigned long tmp;
 150
 151         if (!icr0) {
 152                 pr_warn("r8a7778: unable to setup external irq pin mode\n");
 153                 return;
 154         }
 155
 156         tmp = ioread32(icr0);
 157         if (irlm)
 158                 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
 159         else
 160                 tmp &= ~(1 << 23); /* IRL mode - not supported */
 161         tmp |= (1 << 21); /* LVLMODE = 1 */
 162         iowrite32(tmp, icr0);
 163         iounmap(icr0);
 164
 165         if (irlm)
 166                 platform_device_register_resndata(
 167                         &platform_bus, "renesas_intc_irqpin", -1,
 168                         irqpin_resources, ARRAY_SIZE(irqpin_resources),
 169                         &irqpin_platform_data, sizeof(irqpin_platform_data));
 170 }
 171
 172 #define INT2SMSKCR0     0x82288 /* 0xfe782288 */
 173 #define INT2SMSKCR1     0x8228c /* 0xfe78228c */
 174
 175 #define INT2NTSR0       0x00018 /* 0xfe700018 */
 176 #define INT2NTSR1       0x0002c /* 0xfe70002c */
 177 static void __init r8a7778_init_irq_common(void)
 178 {
 179         void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
 180
 181         BUG_ON(!base);
 182
 183         /* route all interrupts to ARM */
 184         __raw_writel(0x73ffffff, base + INT2NTSR0);
 185         __raw_writel(0xffffffff, base + INT2NTSR1);
 186
 187         /* unmask all known interrupts in INTCS2 */
 188         __raw_writel(0x08330773, base + INT2SMSKCR0);
 189         __raw_writel(0x00311110, base + INT2SMSKCR1);
 190
 191         iounmap(base);
 192 }
 193
 194 void __init r8a7778_init_irq(void)
 195 {
 196         void __iomem *gic_dist_base;
 197         void __iomem *gic_cpu_base;
 198
 199         gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
 200         gic_cpu_base  = ioremap_nocache(0xfe430000, PAGE_SIZE);
 201         BUG_ON(!gic_dist_base || !gic_cpu_base);
 202
 203         /* use GIC to handle interrupts */
 204         gic_init(0, 29, gic_dist_base, gic_cpu_base);
 205
 206         r8a7778_init_irq_common();
 207 }
 208
 209 void __init r8a7778_init_delay(void)
 210 {
 211         shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
 212 }
 213
 214 #ifdef CONFIG_USE_OF
 215 void __init r8a7778_init_irq_dt(void)
 216 {
 217         irqchip_init();
 218         r8a7778_init_irq_common();
 219 }
 220
 221 static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = {
 222         {},
 223 };
 224
 225 void __init r8a7778_add_standard_devices_dt(void)
 226 {
 227         of_platform_populate(NULL, of_default_bus_match_table,
 228                              r8a7778_auxdata_lookup, NULL);
 229 }
 230
 231 static const char *r8a7778_compat_dt[] __initdata = {
 232         "renesas,r8a7778",
 233         NULL,
 234 };
 235
 236 DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
 237         .init_early     = r8a7778_init_delay,
 238         .init_irq       = r8a7778_init_irq_dt,
 239         .init_machine   = r8a7778_add_standard_devices_dt,
 240         .init_time      = shmobile_timer_init,
 241         .dt_compat      = r8a7778_compat_dt,
 242 MACHINE_END
 243
 244 #endif /* CONFIG_USE_OF */