2 * arch/arm/mach-pnx4008/time.c
6 * Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source@mvista.com>
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/sched.h>
19 #include <linux/spinlock.h>
20 #include <linux/module.h>
21 #include <linux/kallsyms.h>
22 #include <linux/time.h>
23 #include <linux/timex.h>
24 #include <linux/irq.h>
27 #include <mach/hardware.h>
29 #include <asm/mach/time.h>
30 #include <asm/errno.h>
34 /*! Note: all timers are UPCOUNTING */
37 * Returns number of us since last clock interrupt. Note that interrupts
38 * will have been disabled by do_gettimeoffset()
40 static unsigned long pnx4008_gettimeoffset(void)
43 __raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER);
44 u32 elapsed = LATCH - ticks_to_match;
45 return (elapsed * (tick_nsec / 1000)) / LATCH;
49 * IRQ handler for the timer
51 static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id)
53 if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
59 * this algorithm takes care of possible delay
60 * for this interrupt handling longer than a normal
63 __raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH,
65 __raw_writel(MATCH0_INT, HSTIM_INT); /* clear interrupt */
68 * The goal is to keep incrementing HSTIM_MATCH0
69 * register until HSTIM_MATCH0 indicates time after
70 * what HSTIM_COUNTER indicates.
73 (__raw_readl(HSTIM_MATCH0) -
74 __raw_readl(HSTIM_COUNTER)) < 0);
80 static struct irqaction pnx4008_timer_irq = {
81 .name = "PNX4008 Tick Timer",
82 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
83 .handler = pnx4008_timer_interrupt
87 * Set up timer and timer interrupt.
89 static __init void pnx4008_setup_timer(void)
91 __raw_writel(RESET_COUNT, MSTIM_CTRL);
92 while (__raw_readl(MSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */
93 __raw_writel(0, MSTIM_CTRL); /* stop the timer */
94 __raw_writel(0, MSTIM_MCTRL);
96 __raw_writel(RESET_COUNT, HSTIM_CTRL);
97 while (__raw_readl(HSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */
98 __raw_writel(0, HSTIM_CTRL);
99 __raw_writel(0, HSTIM_MCTRL);
100 __raw_writel(0, HSTIM_CCR);
101 __raw_writel(12, HSTIM_PMATCH); /* scale down to 1 MHZ */
102 __raw_writel(LATCH, HSTIM_MATCH0);
103 __raw_writel(MR0_INT, HSTIM_MCTRL);
105 setup_irq(HSTIMER_INT, &pnx4008_timer_irq);
107 __raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL); /*start timer, stop when JTAG active */
110 /* Timer Clock Control in PM register */
111 #define TIMCLK_CTRL_REG IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC))
112 #define WATCHDOG_CLK_EN 1
113 #define TIMER_CLK_EN 2 /* HS and MS timers? */
115 static u32 timclk_ctrl_reg_save;
117 void pnx4008_timer_suspend(void)
119 timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG);
120 __raw_writel(0, TIMCLK_CTRL_REG); /* disable timers */
123 void pnx4008_timer_resume(void)
125 __raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG); /* enable timers */
128 struct sys_timer pnx4008_timer = {
129 .init = pnx4008_setup_timer,
130 .offset = pnx4008_gettimeoffset,
131 .suspend = pnx4008_timer_suspend,
132 .resume = pnx4008_timer_resume,