arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

   1 /*
   2  * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
   3  *
   4  * Copyright (C) 2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/omap-dma.h>
  14
  15 #include "omap_hwmod.h"
  16 #include "omap_hwmod_common_data.h"
  17 #include "cm-regbits-24xx.h"
  18 #include "prm-regbits-24xx.h"
  19 #include "wd_timer.h"
  20
  21 /*
  22  * 'dispc' class
  23  * display controller
  24  */
  25
  26 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
  27         .rev_offs       = 0x0000,
  28         .sysc_offs      = 0x0010,
  29         .syss_offs      = 0x0014,
  30         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  31                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  32         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  33                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  34         .sysc_fields    = &omap_hwmod_sysc_type1,
  35 };
  36
  37 struct omap_hwmod_class omap2_dispc_hwmod_class = {
  38         .name   = "dispc",
  39         .sysc   = &omap2_dispc_sysc,
  40 };
  41
  42 /* OMAP2xxx Timer Common */
  43 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
  44         .rev_offs       = 0x0000,
  45         .sysc_offs      = 0x0010,
  46         .syss_offs      = 0x0014,
  47         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  48                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  49                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  50         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  51         .sysc_fields    = &omap_hwmod_sysc_type1,
  52 };
  53
  54 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
  55         .name   = "timer",
  56         .sysc   = &omap2xxx_timer_sysc,
  57 };
  58
  59 /*
  60  * 'wd_timer' class
  61  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  62  * overflow condition
  63  */
  64
  65 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
  66         .rev_offs       = 0x0000,
  67         .sysc_offs      = 0x0010,
  68         .syss_offs      = 0x0014,
  69         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
  70                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  71         .sysc_fields    = &omap_hwmod_sysc_type1,
  72 };
  73
  74 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
  75         .name           = "wd_timer",
  76         .sysc           = &omap2xxx_wd_timer_sysc,
  77         .pre_shutdown   = &omap2_wd_timer_disable,
  78         .reset          = &omap2_wd_timer_reset,
  79 };
  80
  81 /*
  82  * 'gpio' class
  83  * general purpose io module
  84  */
  85 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
  86         .rev_offs       = 0x0000,
  87         .sysc_offs      = 0x0010,
  88         .syss_offs      = 0x0014,
  89         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
  90                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  91                            SYSS_HAS_RESET_STATUS),
  92         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  93         .sysc_fields    = &omap_hwmod_sysc_type1,
  94 };
  95
  96 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
  97         .name = "gpio",
  98         .sysc = &omap2xxx_gpio_sysc,
  99         .rev = 0,
 100 };
 101
 102 /* system dma */
 103 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
 104         .rev_offs       = 0x0000,
 105         .sysc_offs      = 0x002c,
 106         .syss_offs      = 0x0028,
 107         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
 108                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
 109                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 110         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 111         .sysc_fields    = &omap_hwmod_sysc_type1,
 112 };
 113
 114 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
 115         .name   = "dma",
 116         .sysc   = &omap2xxx_dma_sysc,
 117 };
 118
 119 /*
 120  * 'mailbox' class
 121  * mailbox module allowing communication between the on-chip processors
 122  * using a queued mailbox-interrupt mechanism.
 123  */
 124
 125 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
 126         .rev_offs       = 0x000,
 127         .sysc_offs      = 0x010,
 128         .syss_offs      = 0x014,
 129         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 130                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 131         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 132         .sysc_fields    = &omap_hwmod_sysc_type1,
 133 };
 134
 135 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
 136         .name   = "mailbox",
 137         .sysc   = &omap2xxx_mailbox_sysc,
 138 };
 139
 140 /*
 141  * 'mcspi' class
 142  * multichannel serial port interface (mcspi) / master/slave synchronous serial
 143  * bus
 144  */
 145
 146 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
 147         .rev_offs       = 0x0000,
 148         .sysc_offs      = 0x0010,
 149         .syss_offs      = 0x0014,
 150         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 151                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 152                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 153         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 154         .sysc_fields    = &omap_hwmod_sysc_type1,
 155 };
 156
 157 struct omap_hwmod_class omap2xxx_mcspi_class = {
 158         .name   = "mcspi",
 159         .sysc   = &omap2xxx_mcspi_sysc,
 160 };
 161
 162 /*
 163  * 'gpmc' class
 164  * general purpose memory controller
 165  */
 166
 167 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
 168         .rev_offs       = 0x0000,
 169         .sysc_offs      = 0x0010,
 170         .syss_offs      = 0x0014,
 171         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 172                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 173         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 174         .sysc_fields    = &omap_hwmod_sysc_type1,
 175 };
 176
 177 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
 178         .name   = "gpmc",
 179         .sysc   = &omap2xxx_gpmc_sysc,
 180 };
 181
 182 /*
 183  * IP blocks
 184  */
 185
 186 /* L3 */
 187 struct omap_hwmod omap2xxx_l3_main_hwmod = {
 188         .name           = "l3_main",
 189         .class          = &l3_hwmod_class,
 190         .flags          = HWMOD_NO_IDLEST,
 191 };
 192
 193 /* L4 CORE */
 194 struct omap_hwmod omap2xxx_l4_core_hwmod = {
 195         .name           = "l4_core",
 196         .class          = &l4_hwmod_class,
 197         .flags          = HWMOD_NO_IDLEST,
 198 };
 199
 200 /* L4 WKUP */
 201 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 202         .name           = "l4_wkup",
 203         .class          = &l4_hwmod_class,
 204         .flags          = HWMOD_NO_IDLEST,
 205 };
 206
 207 /* MPU */
 208 struct omap_hwmod omap2xxx_mpu_hwmod = {
 209         .name           = "mpu",
 210         .class          = &mpu_hwmod_class,
 211         .main_clk       = "mpu_ck",
 212 };
 213
 214 /* IVA2 */
 215 struct omap_hwmod omap2xxx_iva_hwmod = {
 216         .name           = "iva",
 217         .class          = &iva_hwmod_class,
 218 };
 219
 220 /* timer1 */
 221 struct omap_hwmod omap2xxx_timer1_hwmod = {
 222         .name           = "timer1",
 223         .main_clk       = "gpt1_fck",
 224         .prcm           = {
 225                 .omap2 = {
 226                         .module_offs = WKUP_MOD,
 227                         .idlest_reg_id = 1,
 228                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 229                 },
 230         },
 231         .class          = &omap2xxx_timer_hwmod_class,
 232         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 233 };
 234
 235 /* timer2 */
 236 struct omap_hwmod omap2xxx_timer2_hwmod = {
 237         .name           = "timer2",
 238         .main_clk       = "gpt2_fck",
 239         .prcm           = {
 240                 .omap2 = {
 241                         .module_offs = CORE_MOD,
 242                         .idlest_reg_id = 1,
 243                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 244                 },
 245         },
 246         .class          = &omap2xxx_timer_hwmod_class,
 247         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 248 };
 249
 250 /* timer3 */
 251 struct omap_hwmod omap2xxx_timer3_hwmod = {
 252         .name           = "timer3",
 253         .main_clk       = "gpt3_fck",
 254         .prcm           = {
 255                 .omap2 = {
 256                         .module_offs = CORE_MOD,
 257                         .idlest_reg_id = 1,
 258                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 259                 },
 260         },
 261         .class          = &omap2xxx_timer_hwmod_class,
 262         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 263 };
 264
 265 /* timer4 */
 266 struct omap_hwmod omap2xxx_timer4_hwmod = {
 267         .name           = "timer4",
 268         .main_clk       = "gpt4_fck",
 269         .prcm           = {
 270                 .omap2 = {
 271                         .module_offs = CORE_MOD,
 272                         .idlest_reg_id = 1,
 273                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 274                 },
 275         },
 276         .class          = &omap2xxx_timer_hwmod_class,
 277         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 278 };
 279
 280 /* timer5 */
 281 struct omap_hwmod omap2xxx_timer5_hwmod = {
 282         .name           = "timer5",
 283         .main_clk       = "gpt5_fck",
 284         .prcm           = {
 285                 .omap2 = {
 286                         .module_offs = CORE_MOD,
 287                         .idlest_reg_id = 1,
 288                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 289                 },
 290         },
 291         .class          = &omap2xxx_timer_hwmod_class,
 292         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 293 };
 294
 295 /* timer6 */
 296 struct omap_hwmod omap2xxx_timer6_hwmod = {
 297         .name           = "timer6",
 298         .main_clk       = "gpt6_fck",
 299         .prcm           = {
 300                 .omap2 = {
 301                         .module_offs = CORE_MOD,
 302                         .idlest_reg_id = 1,
 303                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 304                 },
 305         },
 306         .class          = &omap2xxx_timer_hwmod_class,
 307         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 308 };
 309
 310 /* timer7 */
 311 struct omap_hwmod omap2xxx_timer7_hwmod = {
 312         .name           = "timer7",
 313         .main_clk       = "gpt7_fck",
 314         .prcm           = {
 315                 .omap2 = {
 316                         .module_offs = CORE_MOD,
 317                         .idlest_reg_id = 1,
 318                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 319                 },
 320         },
 321         .class          = &omap2xxx_timer_hwmod_class,
 322         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 323 };
 324
 325 /* timer8 */
 326 struct omap_hwmod omap2xxx_timer8_hwmod = {
 327         .name           = "timer8",
 328         .main_clk       = "gpt8_fck",
 329         .prcm           = {
 330                 .omap2 = {
 331                         .module_offs = CORE_MOD,
 332                         .idlest_reg_id = 1,
 333                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 334                 },
 335         },
 336         .class          = &omap2xxx_timer_hwmod_class,
 337         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 338 };
 339
 340 /* timer9 */
 341 struct omap_hwmod omap2xxx_timer9_hwmod = {
 342         .name           = "timer9",
 343         .main_clk       = "gpt9_fck",
 344         .prcm           = {
 345                 .omap2 = {
 346                         .module_offs = CORE_MOD,
 347                         .idlest_reg_id = 1,
 348                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 349                 },
 350         },
 351         .class          = &omap2xxx_timer_hwmod_class,
 352         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 353 };
 354
 355 /* timer10 */
 356 struct omap_hwmod omap2xxx_timer10_hwmod = {
 357         .name           = "timer10",
 358         .main_clk       = "gpt10_fck",
 359         .prcm           = {
 360                 .omap2 = {
 361                         .module_offs = CORE_MOD,
 362                         .idlest_reg_id = 1,
 363                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 364                 },
 365         },
 366         .class          = &omap2xxx_timer_hwmod_class,
 367         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 368 };
 369
 370 /* timer11 */
 371 struct omap_hwmod omap2xxx_timer11_hwmod = {
 372         .name           = "timer11",
 373         .main_clk       = "gpt11_fck",
 374         .prcm           = {
 375                 .omap2 = {
 376                         .module_offs = CORE_MOD,
 377                         .idlest_reg_id = 1,
 378                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 379                 },
 380         },
 381         .class          = &omap2xxx_timer_hwmod_class,
 382         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 383 };
 384
 385 /* timer12 */
 386 struct omap_hwmod omap2xxx_timer12_hwmod = {
 387         .name           = "timer12",
 388         .main_clk       = "gpt12_fck",
 389         .prcm           = {
 390                 .omap2 = {
 391                         .module_offs = CORE_MOD,
 392                         .idlest_reg_id = 1,
 393                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 394                 },
 395         },
 396         .class          = &omap2xxx_timer_hwmod_class,
 397         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 398 };
 399
 400 /* wd_timer2 */
 401 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
 402         .name           = "wd_timer2",
 403         .class          = &omap2xxx_wd_timer_hwmod_class,
 404         .main_clk       = "mpu_wdt_fck",
 405         .prcm           = {
 406                 .omap2 = {
 407                         .module_offs = WKUP_MOD,
 408                         .idlest_reg_id = 1,
 409                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 410                 },
 411         },
 412 };
 413
 414 /* UART1 */
 415
 416 struct omap_hwmod omap2xxx_uart1_hwmod = {
 417         .name           = "uart1",
 418         .main_clk       = "uart1_fck",
 419         .flags          = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 420         .prcm           = {
 421                 .omap2 = {
 422                         .module_offs = CORE_MOD,
 423                         .idlest_reg_id = 1,
 424                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 425                 },
 426         },
 427         .class          = &omap2_uart_class,
 428 };
 429
 430 /* UART2 */
 431
 432 struct omap_hwmod omap2xxx_uart2_hwmod = {
 433         .name           = "uart2",
 434         .main_clk       = "uart2_fck",
 435         .flags          = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 436         .prcm           = {
 437                 .omap2 = {
 438                         .module_offs = CORE_MOD,
 439                         .idlest_reg_id = 1,
 440                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 441                 },
 442         },
 443         .class          = &omap2_uart_class,
 444 };
 445
 446 /* UART3 */
 447
 448 struct omap_hwmod omap2xxx_uart3_hwmod = {
 449         .name           = "uart3",
 450         .main_clk       = "uart3_fck",
 451         .flags          = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
 452         .prcm           = {
 453                 .omap2 = {
 454                         .module_offs = CORE_MOD,
 455                         .idlest_reg_id = 2,
 456                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 457                 },
 458         },
 459         .class          = &omap2_uart_class,
 460 };
 461
 462 /* dss */
 463
 464 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 465         /*
 466          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 467          * driver does not use these clocks.
 468          */
 469         { .role = "tv_clk", .clk = "dss_54m_fck" },
 470         { .role = "sys_clk", .clk = "dss2_fck" },
 471 };
 472
 473 struct omap_hwmod omap2xxx_dss_core_hwmod = {
 474         .name           = "dss_core",
 475         .class          = &omap2_dss_hwmod_class,
 476         .main_clk       = "dss1_fck", /* instead of dss_fck */
 477         .prcm           = {
 478                 .omap2 = {
 479                         .module_offs = CORE_MOD,
 480                         .idlest_reg_id = 1,
 481                 },
 482         },
 483         .opt_clks       = dss_opt_clks,
 484         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 485         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 486 };
 487
 488 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
 489         .name           = "dss_dispc",
 490         .class          = &omap2_dispc_hwmod_class,
 491         .main_clk       = "dss1_fck",
 492         .prcm           = {
 493                 .omap2 = {
 494                         .module_offs = CORE_MOD,
 495                         .idlest_reg_id = 1,
 496                 },
 497         },
 498         .flags          = HWMOD_NO_IDLEST,
 499         .dev_attr       = &omap2_3_dss_dispc_dev_attr,
 500 };
 501
 502 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 503         { .role = "ick", .clk = "dss_ick" },
 504 };
 505
 506 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
 507         .name           = "dss_rfbi",
 508         .class          = &omap2_rfbi_hwmod_class,
 509         .main_clk       = "dss1_fck",
 510         .prcm           = {
 511                 .omap2 = {
 512                         .module_offs = CORE_MOD,
 513                 },
 514         },
 515         .opt_clks       = dss_rfbi_opt_clks,
 516         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 517         .flags          = HWMOD_NO_IDLEST,
 518 };
 519
 520 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
 521         .name           = "dss_venc",
 522         .class          = &omap2_venc_hwmod_class,
 523         .main_clk       = "dss_54m_fck",
 524         .prcm           = {
 525                 .omap2 = {
 526                         .module_offs = CORE_MOD,
 527                 },
 528         },
 529         .flags          = HWMOD_NO_IDLEST,
 530 };
 531
 532 /* gpio1 */
 533 struct omap_hwmod omap2xxx_gpio1_hwmod = {
 534         .name           = "gpio1",
 535         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 536         .main_clk       = "gpios_fck",
 537         .prcm           = {
 538                 .omap2 = {
 539                         .module_offs = WKUP_MOD,
 540                         .idlest_reg_id = 1,
 541                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 542                 },
 543         },
 544         .class          = &omap2xxx_gpio_hwmod_class,
 545 };
 546
 547 /* gpio2 */
 548 struct omap_hwmod omap2xxx_gpio2_hwmod = {
 549         .name           = "gpio2",
 550         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 551         .main_clk       = "gpios_fck",
 552         .prcm           = {
 553                 .omap2 = {
 554                         .module_offs = WKUP_MOD,
 555                         .idlest_reg_id = 1,
 556                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 557                 },
 558         },
 559         .class          = &omap2xxx_gpio_hwmod_class,
 560 };
 561
 562 /* gpio3 */
 563 struct omap_hwmod omap2xxx_gpio3_hwmod = {
 564         .name           = "gpio3",
 565         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 566         .main_clk       = "gpios_fck",
 567         .prcm           = {
 568                 .omap2 = {
 569                         .module_offs = WKUP_MOD,
 570                         .idlest_reg_id = 1,
 571                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 572                 },
 573         },
 574         .class          = &omap2xxx_gpio_hwmod_class,
 575 };
 576
 577 /* gpio4 */
 578 struct omap_hwmod omap2xxx_gpio4_hwmod = {
 579         .name           = "gpio4",
 580         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 581         .main_clk       = "gpios_fck",
 582         .prcm           = {
 583                 .omap2 = {
 584                         .module_offs = WKUP_MOD,
 585                         .idlest_reg_id = 1,
 586                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 587                 },
 588         },
 589         .class          = &omap2xxx_gpio_hwmod_class,
 590 };
 591
 592 /* mcspi1 */
 593 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
 594         .name           = "mcspi1",
 595         .main_clk       = "mcspi1_fck",
 596         .prcm           = {
 597                 .omap2 = {
 598                         .module_offs = CORE_MOD,
 599                         .idlest_reg_id = 1,
 600                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
 601                 },
 602         },
 603         .class          = &omap2xxx_mcspi_class,
 604 };
 605
 606 /* mcspi2 */
 607 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
 608         .name           = "mcspi2",
 609         .main_clk       = "mcspi2_fck",
 610         .prcm           = {
 611                 .omap2 = {
 612                         .module_offs = CORE_MOD,
 613                         .idlest_reg_id = 1,
 614                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
 615                 },
 616         },
 617         .class          = &omap2xxx_mcspi_class,
 618 };
 619
 620 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
 621         .name   = "counter",
 622 };
 623
 624 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
 625         .name           = "counter_32k",
 626         .main_clk       = "func_32k_ck",
 627         .prcm           = {
 628                 .omap2  = {
 629                         .module_offs = WKUP_MOD,
 630                         .idlest_reg_id = 1,
 631                         .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 632                 },
 633         },
 634         .class          = &omap2xxx_counter_hwmod_class,
 635 };
 636
 637 /* gpmc */
 638 struct omap_hwmod omap2xxx_gpmc_hwmod = {
 639         .name           = "gpmc",
 640         .class          = &omap2xxx_gpmc_hwmod_class,
 641         .main_clk       = "gpmc_fck",
 642         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
 643         .flags          = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
 644         .prcm           = {
 645                 .omap2  = {
 646                         .module_offs = CORE_MOD,
 647                 },
 648         },
 649 };
 650
 651 /* RNG */
 652
 653 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
 654         .rev_offs       = 0x3c,
 655         .sysc_offs      = 0x40,
 656         .syss_offs      = 0x44,
 657         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 658                            SYSS_HAS_RESET_STATUS),
 659         .sysc_fields    = &omap_hwmod_sysc_type1,
 660 };
 661
 662 static struct omap_hwmod_class omap2_rng_hwmod_class = {
 663         .name           = "rng",
 664         .sysc           = &omap2_rng_sysc,
 665 };
 666
 667 struct omap_hwmod omap2xxx_rng_hwmod = {
 668         .name           = "rng",
 669         .main_clk       = "l4_ck",
 670         .prcm           = {
 671                 .omap2 = {
 672                         .module_offs = CORE_MOD,
 673                         .idlest_reg_id = 4,
 674                         .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
 675                 },
 676         },
 677         /*
 678          * XXX The first read from the SYSSTATUS register of the RNG
 679          * after the SYSCONFIG SOFTRESET bit is set triggers an
 680          * imprecise external abort.  It's unclear why this happens.
 681          * Until this is analyzed, skip the IP block reset.
 682          */
 683         .flags          = HWMOD_INIT_NO_RESET,
 684         .class          = &omap2_rng_hwmod_class,
 685 };
 686
 687 /* SHAM */
 688
 689 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
 690         .rev_offs       = 0x5c,
 691         .sysc_offs      = 0x60,
 692         .syss_offs      = 0x64,
 693         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 694                            SYSS_HAS_RESET_STATUS),
 695         .sysc_fields    = &omap_hwmod_sysc_type1,
 696 };
 697
 698 static struct omap_hwmod_class omap2xxx_sham_class = {
 699         .name   = "sham",
 700         .sysc   = &omap2_sham_sysc,
 701 };
 702
 703 struct omap_hwmod omap2xxx_sham_hwmod = {
 704         .name           = "sham",
 705         .main_clk       = "l4_ck",
 706         .prcm           = {
 707                 .omap2 = {
 708                         .module_offs = CORE_MOD,
 709                         .idlest_reg_id = 4,
 710                         .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
 711                 },
 712         },
 713         .class          = &omap2xxx_sham_class,
 714 };
 715
 716 /* AES */
 717
 718 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
 719         .rev_offs       = 0x44,
 720         .sysc_offs      = 0x48,
 721         .syss_offs      = 0x4c,
 722         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 723                            SYSS_HAS_RESET_STATUS),
 724         .sysc_fields    = &omap_hwmod_sysc_type1,
 725 };
 726
 727 static struct omap_hwmod_class omap2xxx_aes_class = {
 728         .name   = "aes",
 729         .sysc   = &omap2_aes_sysc,
 730 };
 731
 732 struct omap_hwmod omap2xxx_aes_hwmod = {
 733         .name           = "aes",
 734         .main_clk       = "l4_ck",
 735         .prcm           = {
 736                 .omap2 = {
 737                         .module_offs = CORE_MOD,
 738                         .idlest_reg_id = 4,
 739                         .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
 740                 },
 741         },
 742         .class          = &omap2xxx_aes_class,
 743 };