arch/arm/mach-omap2/id.c

   1 /*
   2  * linux/arch/arm/mach-omap2/id.c
   3  *
   4  * OMAP2 CPU identification code
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009-11 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/io.h>
  21 #include <linux/random.h>
  22 #include <linux/slab.h>
  23
  24 #ifdef CONFIG_SOC_BUS
  25 #include <linux/sys_soc.h>
  26 #endif
  27
  28 #include <asm/cputype.h>
  29
  30 #include "common.h"
  31
  32 #include "id.h"
  33
  34 #include "soc.h"
  35 #include "control.h"
  36
  37 #define OMAP4_SILICON_TYPE_STANDARD             0x01
  38 #define OMAP4_SILICON_TYPE_PERFORMANCE          0x02
  39
  40 #define OMAP_SOC_MAX_NAME_LENGTH                16
  41
  42 static unsigned int omap_revision;
  43 static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
  44 static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
  45 u32 omap_features;
  46
  47 unsigned int omap_rev(void)
  48 {
  49         return omap_revision;
  50 }
  51 EXPORT_SYMBOL(omap_rev);
  52
  53 int omap_type(void)
  54 {
  55         static u32 val = OMAP2_DEVICETYPE_MASK;
  56
  57         if (val < OMAP2_DEVICETYPE_MASK)
  58                 return val;
  59
  60         if (soc_is_omap24xx()) {
  61                 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
  62         } else if (soc_is_ti81xx()) {
  63                 val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
  64         } else if (soc_is_am33xx() || soc_is_am43xx()) {
  65                 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
  66         } else if (soc_is_omap34xx()) {
  67                 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
  68         } else if (soc_is_omap44xx()) {
  69                 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
  70         } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
  71                 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
  72                 val &= OMAP5_DEVICETYPE_MASK;
  73                 val >>= 6;
  74                 goto out;
  75         } else {
  76                 pr_err("Cannot detect omap type!\n");
  77                 goto out;
  78         }
  79
  80         val &= OMAP2_DEVICETYPE_MASK;
  81         val >>= 8;
  82
  83 out:
  84         return val;
  85 }
  86 EXPORT_SYMBOL(omap_type);
  87
  88
  89 /*----------------------------------------------------------------------------*/
  90
  91 #define OMAP_TAP_IDCODE         0x0204
  92 #define OMAP_TAP_DIE_ID_0       0x0218
  93 #define OMAP_TAP_DIE_ID_1       0x021C
  94 #define OMAP_TAP_DIE_ID_2       0x0220
  95 #define OMAP_TAP_DIE_ID_3       0x0224
  96
  97 #define OMAP_TAP_DIE_ID_44XX_0  0x0200
  98 #define OMAP_TAP_DIE_ID_44XX_1  0x0208
  99 #define OMAP_TAP_DIE_ID_44XX_2  0x020c
 100 #define OMAP_TAP_DIE_ID_44XX_3  0x0210
 101
 102 #define read_tap_reg(reg)       readl_relaxed(tap_base  + (reg))
 103
 104 struct omap_id {
 105         u16     hawkeye;        /* Silicon type (Hawkeye id) */
 106         u8      dev;            /* Device type from production_id reg */
 107         u32     type;           /* Combined type id copied to omap_revision */
 108 };
 109
 110 /* Register values to detect the OMAP version */
 111 static struct omap_id omap_ids[] __initdata = {
 112         { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
 113         { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
 114         { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
 115         { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
 116         { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
 117         { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
 118 };
 119
 120 static void __iomem *tap_base;
 121 static u16 tap_prod_id;
 122
 123 void omap_get_die_id(struct omap_die_id *odi)
 124 {
 125         if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
 126                 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
 127                 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
 128                 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
 129                 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
 130
 131                 return;
 132         }
 133         odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
 134         odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
 135         odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
 136         odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
 137 }
 138
 139 static int __init omap_feed_randpool(void)
 140 {
 141         struct omap_die_id odi;
 142
 143         /* Throw the die ID into the entropy pool at boot */
 144         omap_get_die_id(&odi);
 145         add_device_randomness(&odi, sizeof(odi));
 146         return 0;
 147 }
 148 omap_device_initcall(omap_feed_randpool);
 149
 150 void __init omap2xxx_check_revision(void)
 151 {
 152         int i, j;
 153         u32 idcode, prod_id;
 154         u16 hawkeye;
 155         u8  dev_type, rev;
 156         struct omap_die_id odi;
 157
 158         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 159         prod_id = read_tap_reg(tap_prod_id);
 160         hawkeye = (idcode >> 12) & 0xffff;
 161         rev = (idcode >> 28) & 0x0f;
 162         dev_type = (prod_id >> 16) & 0x0f;
 163         omap_get_die_id(&odi);
 164
 165         pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
 166                  idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
 167         pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
 168         pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
 169                  odi.id_1, (odi.id_1 >> 28) & 0xf);
 170         pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
 171         pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
 172         pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
 173                  prod_id, dev_type);
 174
 175         /* Check hawkeye ids */
 176         for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
 177                 if (hawkeye == omap_ids[i].hawkeye)
 178                         break;
 179         }
 180
 181         if (i == ARRAY_SIZE(omap_ids)) {
 182                 printk(KERN_ERR "Unknown OMAP CPU id\n");
 183                 return;
 184         }
 185
 186         for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
 187                 if (dev_type == omap_ids[j].dev)
 188                         break;
 189         }
 190
 191         if (j == ARRAY_SIZE(omap_ids)) {
 192                 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
 193                        omap_ids[i].type >> 16);
 194                 j = i;
 195         }
 196
 197         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 198         sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
 199
 200         pr_info("%s", soc_name);
 201         if ((omap_rev() >> 8) & 0x0f)
 202                 pr_info("%s", soc_rev);
 203         pr_info("\n");
 204 }
 205
 206 #define OMAP3_SHOW_FEATURE(feat)                \
 207         if (omap3_has_ ##feat())                \
 208                 n += scnprintf(buf + n, sizeof(buf) - n, #feat " ");
 209
 210 static void __init omap3_cpuinfo(void)
 211 {
 212         const char *cpu_name;
 213         char buf[64];
 214         int n = 0;
 215
 216         memset(buf, 0, sizeof(buf));
 217
 218         /*
 219          * OMAP3430 and OMAP3530 are assumed to be same.
 220          *
 221          * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
 222          * on available features. Upon detection, update the CPU id
 223          * and CPU class bits.
 224          */
 225         if (soc_is_omap3630()) {
 226                 cpu_name = "OMAP3630";
 227         } else if (soc_is_am35xx()) {
 228                 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
 229         } else if (soc_is_ti816x()) {
 230                 cpu_name = "TI816X";
 231         } else if (soc_is_am335x()) {
 232                 cpu_name =  "AM335X";
 233         } else if (soc_is_am437x()) {
 234                 cpu_name =  "AM437x";
 235         } else if (soc_is_ti814x()) {
 236                 cpu_name = "TI814X";
 237         } else if (omap3_has_iva() && omap3_has_sgx()) {
 238                 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
 239                 cpu_name = "OMAP3430/3530";
 240         } else if (omap3_has_iva()) {
 241                 cpu_name = "OMAP3525";
 242         } else if (omap3_has_sgx()) {
 243                 cpu_name = "OMAP3515";
 244         } else {
 245                 cpu_name = "OMAP3503";
 246         }
 247
 248         scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name);
 249
 250         /* Print verbose information */
 251         n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev);
 252
 253         OMAP3_SHOW_FEATURE(l2cache);
 254         OMAP3_SHOW_FEATURE(iva);
 255         OMAP3_SHOW_FEATURE(sgx);
 256         OMAP3_SHOW_FEATURE(neon);
 257         OMAP3_SHOW_FEATURE(isp);
 258         OMAP3_SHOW_FEATURE(192mhz_clk);
 259         if (*(buf + n - 1) == ' ')
 260                 n--;
 261         n += scnprintf(buf + n, sizeof(buf) - n, ")\n");
 262         pr_info("%s", buf);
 263 }
 264
 265 #define OMAP3_CHECK_FEATURE(status,feat)                                \
 266         if (((status & OMAP3_ ##feat## _MASK)                           \
 267                 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) {   \
 268                 omap_features |= OMAP3_HAS_ ##feat;                     \
 269         }
 270
 271 void __init omap3xxx_check_features(void)
 272 {
 273         u32 status;
 274
 275         omap_features = 0;
 276
 277         status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
 278
 279         OMAP3_CHECK_FEATURE(status, L2CACHE);
 280         OMAP3_CHECK_FEATURE(status, IVA);
 281         OMAP3_CHECK_FEATURE(status, SGX);
 282         OMAP3_CHECK_FEATURE(status, NEON);
 283         OMAP3_CHECK_FEATURE(status, ISP);
 284         if (soc_is_omap3630())
 285                 omap_features |= OMAP3_HAS_192MHZ_CLK;
 286         if (soc_is_omap3430() || soc_is_omap3630())
 287                 omap_features |= OMAP3_HAS_IO_WAKEUP;
 288         if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
 289             omap_rev() == OMAP3430_REV_ES3_1_2)
 290                 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
 291
 292         omap_features |= OMAP3_HAS_SDRC;
 293
 294         /*
 295          * am35x fixups:
 296          * - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
 297          *   reserved and therefore return 0 when read.  Unfortunately,
 298          *   OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
 299          *   mean that a feature is present even though it isn't so clear
 300          *   the incorrectly set feature bits.
 301          */
 302         if (soc_is_am35xx())
 303                 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
 304
 305         /*
 306          * TODO: Get additional info (where applicable)
 307          *       e.g. Size of L2 cache.
 308          */
 309
 310         omap3_cpuinfo();
 311 }
 312
 313 void __init omap4xxx_check_features(void)
 314 {
 315         u32 si_type;
 316
 317         si_type =
 318         (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
 319
 320         if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
 321                 omap_features = OMAP4_HAS_PERF_SILICON;
 322 }
 323
 324 void __init ti81xx_check_features(void)
 325 {
 326         omap_features = OMAP3_HAS_NEON;
 327         omap3_cpuinfo();
 328 }
 329
 330 void __init am33xx_check_features(void)
 331 {
 332         u32 status;
 333
 334         omap_features = OMAP3_HAS_NEON;
 335
 336         status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
 337         if (status & AM33XX_SGX_MASK)
 338                 omap_features |= OMAP3_HAS_SGX;
 339
 340         omap3_cpuinfo();
 341 }
 342
 343 void __init omap3xxx_check_revision(void)
 344 {
 345         const char *cpu_rev;
 346         u32 cpuid, idcode;
 347         u16 hawkeye;
 348         u8 rev;
 349
 350         /*
 351          * We cannot access revision registers on ES1.0.
 352          * If the processor type is Cortex-A8 and the revision is 0x0
 353          * it means its Cortex r0p0 which is 3430 ES1.0.
 354          */
 355         cpuid = read_cpuid_id();
 356         if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
 357                 omap_revision = OMAP3430_REV_ES1_0;
 358                 cpu_rev = "1.0";
 359                 return;
 360         }
 361
 362         /*
 363          * Detection for 34xx ES2.0 and above can be done with just
 364          * hawkeye and rev. See TRM 1.5.2 Device Identification.
 365          * Note that rev does not map directly to our defined processor
 366          * revision numbers as ES1.0 uses value 0.
 367          */
 368         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 369         hawkeye = (idcode >> 12) & 0xffff;
 370         rev = (idcode >> 28) & 0xff;
 371
 372         switch (hawkeye) {
 373         case 0xb7ae:
 374                 /* Handle 34xx/35xx devices */
 375                 switch (rev) {
 376                 case 0: /* Take care of early samples */
 377                 case 1:
 378                         omap_revision = OMAP3430_REV_ES2_0;
 379                         cpu_rev = "2.0";
 380                         break;
 381                 case 2:
 382                         omap_revision = OMAP3430_REV_ES2_1;
 383                         cpu_rev = "2.1";
 384                         break;
 385                 case 3:
 386                         omap_revision = OMAP3430_REV_ES3_0;
 387                         cpu_rev = "3.0";
 388                         break;
 389                 case 4:
 390                         omap_revision = OMAP3430_REV_ES3_1;
 391                         cpu_rev = "3.1";
 392                         break;
 393                 case 7:
 394                 /* FALLTHROUGH */
 395                 default:
 396                         /* Use the latest known revision as default */
 397                         omap_revision = OMAP3430_REV_ES3_1_2;
 398                         cpu_rev = "3.1.2";
 399                 }
 400                 break;
 401         case 0xb868:
 402                 /*
 403                  * Handle OMAP/AM 3505/3517 devices
 404                  *
 405                  * Set the device to be OMAP3517 here. Actual device
 406                  * is identified later based on the features.
 407                  */
 408                 switch (rev) {
 409                 case 0:
 410                         omap_revision = AM35XX_REV_ES1_0;
 411                         cpu_rev = "1.0";
 412                         break;
 413                 case 1:
 414                 /* FALLTHROUGH */
 415                 default:
 416                         omap_revision = AM35XX_REV_ES1_1;
 417                         cpu_rev = "1.1";
 418                 }
 419                 break;
 420         case 0xb891:
 421                 /* Handle 36xx devices */
 422
 423                 switch(rev) {
 424                 case 0: /* Take care of early samples */
 425                         omap_revision = OMAP3630_REV_ES1_0;
 426                         cpu_rev = "1.0";
 427                         break;
 428                 case 1:
 429                         omap_revision = OMAP3630_REV_ES1_1;
 430                         cpu_rev = "1.1";
 431                         break;
 432                 case 2:
 433                 /* FALLTHROUGH */
 434                 default:
 435                         omap_revision = OMAP3630_REV_ES1_2;
 436                         cpu_rev = "1.2";
 437                 }
 438                 break;
 439         case 0xb81e:
 440                 switch (rev) {
 441                 case 0:
 442                         omap_revision = TI8168_REV_ES1_0;
 443                         cpu_rev = "1.0";
 444                         break;
 445                 case 1:
 446                         omap_revision = TI8168_REV_ES1_1;
 447                         cpu_rev = "1.1";
 448                         break;
 449                 case 2:
 450                         omap_revision = TI8168_REV_ES2_0;
 451                         cpu_rev = "2.0";
 452                         break;
 453                 case 3:
 454                         /* FALLTHROUGH */
 455                 default:
 456                         omap_revision = TI8168_REV_ES2_1;
 457                         cpu_rev = "2.1";
 458                 }
 459                 break;
 460         case 0xb944:
 461                 switch (rev) {
 462                 case 0:
 463                         omap_revision = AM335X_REV_ES1_0;
 464                         cpu_rev = "1.0";
 465                         break;
 466                 case 1:
 467                         omap_revision = AM335X_REV_ES2_0;
 468                         cpu_rev = "2.0";
 469                         break;
 470                 case 2:
 471                 /* FALLTHROUGH */
 472                 default:
 473                         omap_revision = AM335X_REV_ES2_1;
 474                         cpu_rev = "2.1";
 475                         break;
 476                 }
 477                 break;
 478         case 0xb98c:
 479                 switch (rev) {
 480                 case 0:
 481                         omap_revision = AM437X_REV_ES1_0;
 482                         cpu_rev = "1.0";
 483                         break;
 484                 case 1:
 485                         omap_revision = AM437X_REV_ES1_1;
 486                         cpu_rev = "1.1";
 487                         break;
 488                 case 2:
 489                 /* FALLTHROUGH */
 490                 default:
 491                         omap_revision = AM437X_REV_ES1_2;
 492                         cpu_rev = "1.2";
 493                         break;
 494                 }
 495                 break;
 496         case 0xb8f2:
 497         case 0xb968:
 498                 switch (rev) {
 499                 case 0:
 500                 /* FALLTHROUGH */
 501                 case 1:
 502                         omap_revision = TI8148_REV_ES1_0;
 503                         cpu_rev = "1.0";
 504                         break;
 505                 case 2:
 506                         omap_revision = TI8148_REV_ES2_0;
 507                         cpu_rev = "2.0";
 508                         break;
 509                 case 3:
 510                 /* FALLTHROUGH */
 511                 default:
 512                         omap_revision = TI8148_REV_ES2_1;
 513                         cpu_rev = "2.1";
 514                         break;
 515                 }
 516                 break;
 517         default:
 518                 /* Unknown default to latest silicon rev as default */
 519                 omap_revision = OMAP3630_REV_ES1_2;
 520                 cpu_rev = "1.2";
 521                 pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n",
 522                         hawkeye);
 523         }
 524         sprintf(soc_rev, "ES%s", cpu_rev);
 525 }
 526
 527 void __init omap4xxx_check_revision(void)
 528 {
 529         u32 idcode;
 530         u16 hawkeye;
 531         u8 rev;
 532
 533         /*
 534          * The IC rev detection is done with hawkeye and rev.
 535          * Note that rev does not map directly to defined processor
 536          * revision numbers as ES1.0 uses value 0.
 537          */
 538         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 539         hawkeye = (idcode >> 12) & 0xffff;
 540         rev = (idcode >> 28) & 0xf;
 541
 542         /*
 543          * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
 544          * Use ARM register to detect the correct ES version
 545          */
 546         if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
 547                 idcode = read_cpuid_id();
 548                 rev = (idcode & 0xf) - 1;
 549         }
 550
 551         switch (hawkeye) {
 552         case 0xb852:
 553                 switch (rev) {
 554                 case 0:
 555                         omap_revision = OMAP4430_REV_ES1_0;
 556                         break;
 557                 case 1:
 558                 default:
 559                         omap_revision = OMAP4430_REV_ES2_0;
 560                 }
 561                 break;
 562         case 0xb95c:
 563                 switch (rev) {
 564                 case 3:
 565                         omap_revision = OMAP4430_REV_ES2_1;
 566                         break;
 567                 case 4:
 568                         omap_revision = OMAP4430_REV_ES2_2;
 569                         break;
 570                 case 6:
 571                 default:
 572                         omap_revision = OMAP4430_REV_ES2_3;
 573                 }
 574                 break;
 575         case 0xb94e:
 576                 switch (rev) {
 577                 case 0:
 578                         omap_revision = OMAP4460_REV_ES1_0;
 579                         break;
 580                 case 2:
 581                 default:
 582                         omap_revision = OMAP4460_REV_ES1_1;
 583                         break;
 584                 }
 585                 break;
 586         case 0xb975:
 587                 switch (rev) {
 588                 case 0:
 589                 default:
 590                         omap_revision = OMAP4470_REV_ES1_0;
 591                         break;
 592                 }
 593                 break;
 594         default:
 595                 /* Unknown default to latest silicon rev as default */
 596                 omap_revision = OMAP4430_REV_ES2_3;
 597         }
 598
 599         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 600         sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
 601                                                 (omap_rev() >> 8) & 0xf);
 602         pr_info("%s %s\n", soc_name, soc_rev);
 603 }
 604
 605 void __init omap5xxx_check_revision(void)
 606 {
 607         u32 idcode;
 608         u16 hawkeye;
 609         u8 rev;
 610
 611         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 612         hawkeye = (idcode >> 12) & 0xffff;
 613         rev = (idcode >> 28) & 0xff;
 614         switch (hawkeye) {
 615         case 0xb942:
 616                 switch (rev) {
 617                 case 0:
 618                         /* No support for ES1.0 Test chip */
 619                         BUG();
 620                 case 1:
 621                 default:
 622                         omap_revision = OMAP5430_REV_ES2_0;
 623                 }
 624                 break;
 625
 626         case 0xb998:
 627                 switch (rev) {
 628                 case 0:
 629                         /* No support for ES1.0 Test chip */
 630                         BUG();
 631                 case 1:
 632                 default:
 633                         omap_revision = OMAP5432_REV_ES2_0;
 634                 }
 635                 break;
 636
 637         default:
 638                 /* Unknown default to latest silicon rev as default*/
 639                 omap_revision = OMAP5430_REV_ES2_0;
 640         }
 641
 642         sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
 643         sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
 644
 645         pr_info("%s %s\n", soc_name, soc_rev);
 646 }
 647
 648 void __init dra7xxx_check_revision(void)
 649 {
 650         u32 idcode;
 651         u16 hawkeye;
 652         u8 rev;
 653
 654         idcode = read_tap_reg(OMAP_TAP_IDCODE);
 655         hawkeye = (idcode >> 12) & 0xffff;
 656         rev = (idcode >> 28) & 0xff;
 657         switch (hawkeye) {
 658         case 0xb990:
 659                 switch (rev) {
 660                 case 0:
 661                         omap_revision = DRA752_REV_ES1_0;
 662                         break;
 663                 case 1:
 664                         omap_revision = DRA752_REV_ES1_1;
 665                         break;
 666                 case 2:
 667                 default:
 668                         omap_revision = DRA752_REV_ES2_0;
 669                         break;
 670                 }
 671                 break;
 672
 673         case 0xb9bc:
 674                 switch (rev) {
 675                 case 0:
 676                         omap_revision = DRA722_REV_ES1_0;
 677                         break;
 678                 case 1:
 679                 default:
 680                         omap_revision = DRA722_REV_ES2_0;
 681                         break;
 682                 }
 683                 break;
 684
 685         default:
 686                 /* Unknown default to latest silicon rev as default*/
 687                 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
 688                         __func__, idcode, hawkeye, rev);
 689                 omap_revision = DRA752_REV_ES2_0;
 690         }
 691
 692         sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
 693         sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
 694                 (omap_rev() >> 8) & 0xf);
 695
 696         pr_info("%s %s\n", soc_name, soc_rev);
 697 }
 698
 699 /*
 700  * Set up things for map_io and processor detection later on. Gets called
 701  * pretty much first thing from board init. For multi-omap, this gets
 702  * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
 703  * detect the exact revision later on in omap2_detect_revision() once map_io
 704  * is done.
 705  */
 706 void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
 707 {
 708         omap_revision = class;
 709         tap_base = tap;
 710
 711         /* XXX What is this intended to do? */
 712         if (soc_is_omap34xx())
 713                 tap_prod_id = 0x0210;
 714         else
 715                 tap_prod_id = 0x0208;
 716 }
 717
 718 #ifdef CONFIG_SOC_BUS
 719
 720 static const char * const omap_types[] = {
 721         [OMAP2_DEVICE_TYPE_TEST]        = "TST",
 722         [OMAP2_DEVICE_TYPE_EMU]         = "EMU",
 723         [OMAP2_DEVICE_TYPE_SEC]         = "HS",
 724         [OMAP2_DEVICE_TYPE_GP]          = "GP",
 725         [OMAP2_DEVICE_TYPE_BAD]         = "BAD",
 726 };
 727
 728 static const char * __init omap_get_family(void)
 729 {
 730         if (soc_is_omap24xx())
 731                 return kasprintf(GFP_KERNEL, "OMAP2");
 732         else if (soc_is_omap34xx())
 733                 return kasprintf(GFP_KERNEL, "OMAP3");
 734         else if (soc_is_omap44xx())
 735                 return kasprintf(GFP_KERNEL, "OMAP4");
 736         else if (soc_is_omap54xx())
 737                 return kasprintf(GFP_KERNEL, "OMAP5");
 738         else if (soc_is_am33xx() || soc_is_am335x())
 739                 return kasprintf(GFP_KERNEL, "AM33xx");
 740         else if (soc_is_am43xx())
 741                 return kasprintf(GFP_KERNEL, "AM43xx");
 742         else if (soc_is_dra7xx())
 743                 return kasprintf(GFP_KERNEL, "DRA7");
 744         else
 745                 return kasprintf(GFP_KERNEL, "Unknown");
 746 }
 747
 748 static ssize_t omap_get_type(struct device *dev,
 749                                         struct device_attribute *attr,
 750                                         char *buf)
 751 {
 752         return sprintf(buf, "%s\n", omap_types[omap_type()]);
 753 }
 754
 755 static struct device_attribute omap_soc_attr =
 756         __ATTR(type,  S_IRUGO, omap_get_type,  NULL);
 757
 758 void __init omap_soc_device_init(void)
 759 {
 760         struct device *parent;
 761         struct soc_device *soc_dev;
 762         struct soc_device_attribute *soc_dev_attr;
 763
 764         soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
 765         if (!soc_dev_attr)
 766                 return;
 767
 768         soc_dev_attr->machine  = soc_name;
 769         soc_dev_attr->family   = omap_get_family();
 770         soc_dev_attr->revision = soc_rev;
 771
 772         soc_dev = soc_device_register(soc_dev_attr);
 773         if (IS_ERR(soc_dev)) {
 774                 kfree(soc_dev_attr);
 775                 return;
 776         }
 777
 778         parent = soc_device_to_device(soc_dev);
 779         device_create_file(parent, &omap_soc_attr);
 780 }
 781 #endif /* CONFIG_SOC_BUS */