arch/arm/mach-omap2/cm3xxx.c

   1 /*
   2  * OMAP3xxx CM module functions
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20
  21 #include "prm2xxx_3xxx.h"
  22 #include "cm.h"
  23 #include "cm3xxx.h"
  24 #include "cm-regbits-34xx.h"
  25 #include "clockdomain.h"
  26
  27 static const u8 omap3xxx_cm_idlest_offs[] = {
  28         CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
  29 };
  30
  31 /*
  32  *
  33  */
  34
  35 static void _write_clktrctrl(u8 c, s16 module, u32 mask)
  36 {
  37         u32 v;
  38
  39         v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
  40         v &= ~mask;
  41         v |= c << __ffs(mask);
  42         omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL);
  43 }
  44
  45 bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask)
  46 {
  47         u32 v;
  48
  49         v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL);
  50         v &= mask;
  51         v >>= __ffs(mask);
  52
  53         return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0;
  54 }
  55
  56 void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask)
  57 {
  58         _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask);
  59 }
  60
  61 void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask)
  62 {
  63         _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask);
  64 }
  65
  66 void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask)
  67 {
  68         _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask);
  69 }
  70
  71 void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
  72 {
  73         _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
  74 }
  75
  76 /*
  77  *
  78  */
  79
  80 /**
  81  * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby
  82  * @prcm_mod: PRCM module offset
  83  * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3)
  84  * @idlest_shift: shift of the bit in the CM_IDLEST* register to check
  85  *
  86  * Wait for the PRCM to indicate that the module identified by
  87  * (@prcm_mod, @idlest_id, @idlest_shift) is clocked.  Return 0 upon
  88  * success or -EBUSY if the module doesn't enable in time.
  89  */
  90 int omap3xxx_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
  91 {
  92         int ena = 0, i = 0;
  93         u8 cm_idlest_reg;
  94         u32 mask;
  95
  96         if (!idlest_id || (idlest_id > ARRAY_SIZE(omap3xxx_cm_idlest_offs)))
  97                 return -EINVAL;
  98
  99         cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1];
 100
 101         mask = 1 << idlest_shift;
 102         ena = 0;
 103
 104         omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) &
 105                             mask) == ena), MAX_MODULE_READY_TIME, i);
 106
 107         return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
 108 }
 109
 110 /**
 111  * omap3xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components
 112  * @idlest_reg: CM_IDLEST* virtual address
 113  * @prcm_inst: pointer to an s16 to return the PRCM instance offset
 114  * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID
 115  *
 116  * XXX This function is only needed until absolute register addresses are
 117  * removed from the OMAP struct clk records.
 118  */
 119 int omap3xxx_cm_split_idlest_reg(void __iomem *idlest_reg, s16 *prcm_inst,
 120                                  u8 *idlest_reg_id)
 121 {
 122         unsigned long offs;
 123         u8 idlest_offs;
 124         int i;
 125
 126         if (idlest_reg < (cm_base + OMAP3430_IVA2_MOD) ||
 127             idlest_reg > (cm_base + 0x1ffff))
 128                 return -EINVAL;
 129
 130         idlest_offs = (unsigned long)idlest_reg & 0xff;
 131         for (i = 0; i < ARRAY_SIZE(omap3xxx_cm_idlest_offs); i++) {
 132                 if (idlest_offs == omap3xxx_cm_idlest_offs[i]) {
 133                         *idlest_reg_id = i + 1;
 134                         break;
 135                 }
 136         }
 137
 138         if (i == ARRAY_SIZE(omap3xxx_cm_idlest_offs))
 139                 return -EINVAL;
 140
 141         offs = idlest_reg - cm_base;
 142         offs &= 0xff00;
 143         *prcm_inst = offs;
 144
 145         return 0;
 146 }
 147
 148 /* Clockdomain low-level operations */
 149
 150 static int omap3xxx_clkdm_add_sleepdep(struct clockdomain *clkdm1,
 151                                        struct clockdomain *clkdm2)
 152 {
 153         omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
 154                                   clkdm1->pwrdm.ptr->prcm_offs,
 155                                   OMAP3430_CM_SLEEPDEP);
 156         return 0;
 157 }
 158
 159 static int omap3xxx_clkdm_del_sleepdep(struct clockdomain *clkdm1,
 160                                        struct clockdomain *clkdm2)
 161 {
 162         omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
 163                                     clkdm1->pwrdm.ptr->prcm_offs,
 164                                     OMAP3430_CM_SLEEPDEP);
 165         return 0;
 166 }
 167
 168 static int omap3xxx_clkdm_read_sleepdep(struct clockdomain *clkdm1,
 169                                         struct clockdomain *clkdm2)
 170 {
 171         return omap2_cm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
 172                                             OMAP3430_CM_SLEEPDEP,
 173                                             (1 << clkdm2->dep_bit));
 174 }
 175
 176 static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
 177 {
 178         struct clkdm_dep *cd;
 179         u32 mask = 0;
 180
 181         for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
 182                 if (!cd->clkdm)
 183                         continue; /* only happens if data is erroneous */
 184
 185                 mask |= 1 << cd->clkdm->dep_bit;
 186                 cd->sleepdep_usecount = 0;
 187         }
 188         omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
 189                                     OMAP3430_CM_SLEEPDEP);
 190         return 0;
 191 }
 192
 193 static int omap3xxx_clkdm_sleep(struct clockdomain *clkdm)
 194 {
 195         omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
 196                                       clkdm->clktrctrl_mask);
 197         return 0;
 198 }
 199
 200 static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm)
 201 {
 202         omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
 203                                        clkdm->clktrctrl_mask);
 204         return 0;
 205 }
 206
 207 static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm)
 208 {
 209         if (clkdm->usecount > 0)
 210                 clkdm_add_autodeps(clkdm);
 211
 212         omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 213                                        clkdm->clktrctrl_mask);
 214 }
 215
 216 static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm)
 217 {
 218         omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 219                                         clkdm->clktrctrl_mask);
 220
 221         if (clkdm->usecount > 0)
 222                 clkdm_del_autodeps(clkdm);
 223 }
 224
 225 static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
 226 {
 227         bool hwsup = false;
 228
 229         if (!clkdm->clktrctrl_mask)
 230                 return 0;
 231
 232         /*
 233          * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
 234          * more details on the unpleasant problem this is working
 235          * around
 236          */
 237         if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
 238             (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
 239                 omap3xxx_clkdm_wakeup(clkdm);
 240                 return 0;
 241         }
 242
 243         hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 244                                               clkdm->clktrctrl_mask);
 245
 246         if (hwsup) {
 247                 /* Disable HW transitions when we are changing deps */
 248                 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 249                                                 clkdm->clktrctrl_mask);
 250                 clkdm_add_autodeps(clkdm);
 251                 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 252                                                clkdm->clktrctrl_mask);
 253         } else {
 254                 if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
 255                         omap3xxx_clkdm_wakeup(clkdm);
 256         }
 257
 258         return 0;
 259 }
 260
 261 static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
 262 {
 263         bool hwsup = false;
 264
 265         if (!clkdm->clktrctrl_mask)
 266                 return 0;
 267
 268         /*
 269          * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
 270          * more details on the unpleasant problem this is working
 271          * around
 272          */
 273         if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
 274             !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
 275                 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 276                                                clkdm->clktrctrl_mask);
 277                 return 0;
 278         }
 279
 280         hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 281                                               clkdm->clktrctrl_mask);
 282
 283         if (hwsup) {
 284                 /* Disable HW transitions when we are changing deps */
 285                 omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 286                                                 clkdm->clktrctrl_mask);
 287                 clkdm_del_autodeps(clkdm);
 288                 omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs,
 289                                                clkdm->clktrctrl_mask);
 290         } else {
 291                 if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
 292                         omap3xxx_clkdm_sleep(clkdm);
 293         }
 294
 295         return 0;
 296 }
 297
 298 struct clkdm_ops omap3_clkdm_operations = {
 299         .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
 300         .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
 301         .clkdm_read_wkdep       = omap2_clkdm_read_wkdep,
 302         .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
 303         .clkdm_add_sleepdep     = omap3xxx_clkdm_add_sleepdep,
 304         .clkdm_del_sleepdep     = omap3xxx_clkdm_del_sleepdep,
 305         .clkdm_read_sleepdep    = omap3xxx_clkdm_read_sleepdep,
 306         .clkdm_clear_all_sleepdeps      = omap3xxx_clkdm_clear_all_sleepdeps,
 307         .clkdm_sleep            = omap3xxx_clkdm_sleep,
 308         .clkdm_wakeup           = omap3xxx_clkdm_wakeup,
 309         .clkdm_allow_idle       = omap3xxx_clkdm_allow_idle,
 310         .clkdm_deny_idle        = omap3xxx_clkdm_deny_idle,
 311         .clkdm_clk_enable       = omap3xxx_clkdm_clk_enable,
 312         .clkdm_clk_disable      = omap3xxx_clkdm_clk_disable,
 313 };
 314
 315 /*
 316  * Context save/restore code - OMAP3 only
 317  */
 318 struct omap3_cm_regs {
 319         u32 iva2_cm_clksel1;
 320         u32 iva2_cm_clksel2;
 321         u32 cm_sysconfig;
 322         u32 sgx_cm_clksel;
 323         u32 dss_cm_clksel;
 324         u32 cam_cm_clksel;
 325         u32 per_cm_clksel;
 326         u32 emu_cm_clksel;
 327         u32 emu_cm_clkstctrl;
 328         u32 pll_cm_autoidle;
 329         u32 pll_cm_autoidle2;
 330         u32 pll_cm_clksel4;
 331         u32 pll_cm_clksel5;
 332         u32 pll_cm_clken2;
 333         u32 cm_polctrl;
 334         u32 iva2_cm_fclken;
 335         u32 iva2_cm_clken_pll;
 336         u32 core_cm_fclken1;
 337         u32 core_cm_fclken3;
 338         u32 sgx_cm_fclken;
 339         u32 wkup_cm_fclken;
 340         u32 dss_cm_fclken;
 341         u32 cam_cm_fclken;
 342         u32 per_cm_fclken;
 343         u32 usbhost_cm_fclken;
 344         u32 core_cm_iclken1;
 345         u32 core_cm_iclken2;
 346         u32 core_cm_iclken3;
 347         u32 sgx_cm_iclken;
 348         u32 wkup_cm_iclken;
 349         u32 dss_cm_iclken;
 350         u32 cam_cm_iclken;
 351         u32 per_cm_iclken;
 352         u32 usbhost_cm_iclken;
 353         u32 iva2_cm_autoidle2;
 354         u32 mpu_cm_autoidle2;
 355         u32 iva2_cm_clkstctrl;
 356         u32 mpu_cm_clkstctrl;
 357         u32 core_cm_clkstctrl;
 358         u32 sgx_cm_clkstctrl;
 359         u32 dss_cm_clkstctrl;
 360         u32 cam_cm_clkstctrl;
 361         u32 per_cm_clkstctrl;
 362         u32 neon_cm_clkstctrl;
 363         u32 usbhost_cm_clkstctrl;
 364         u32 core_cm_autoidle1;
 365         u32 core_cm_autoidle2;
 366         u32 core_cm_autoidle3;
 367         u32 wkup_cm_autoidle;
 368         u32 dss_cm_autoidle;
 369         u32 cam_cm_autoidle;
 370         u32 per_cm_autoidle;
 371         u32 usbhost_cm_autoidle;
 372         u32 sgx_cm_sleepdep;
 373         u32 dss_cm_sleepdep;
 374         u32 cam_cm_sleepdep;
 375         u32 per_cm_sleepdep;
 376         u32 usbhost_cm_sleepdep;
 377         u32 cm_clkout_ctrl;
 378 };
 379
 380 static struct omap3_cm_regs cm_context;
 381
 382 void omap3_cm_save_context(void)
 383 {
 384         cm_context.iva2_cm_clksel1 =
 385                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
 386         cm_context.iva2_cm_clksel2 =
 387                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
 388         cm_context.cm_sysconfig =
 389                 omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_SYSCONFIG);
 390         cm_context.sgx_cm_clksel =
 391                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
 392         cm_context.dss_cm_clksel =
 393                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
 394         cm_context.cam_cm_clksel =
 395                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
 396         cm_context.per_cm_clksel =
 397                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
 398         cm_context.emu_cm_clksel =
 399                 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
 400         cm_context.emu_cm_clkstctrl =
 401                 omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
 402         /*
 403          * As per erratum i671, ROM code does not respect the PER DPLL
 404          * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
 405          * In this case, even though this register has been saved in
 406          * scratchpad contents, we need to restore AUTO_PERIPH_DPLL
 407          * by ourselves. So, we need to save it anyway.
 408          */
 409         cm_context.pll_cm_autoidle =
 410                 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
 411         cm_context.pll_cm_autoidle2 =
 412                 omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
 413         cm_context.pll_cm_clksel4 =
 414                 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
 415         cm_context.pll_cm_clksel5 =
 416                 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
 417         cm_context.pll_cm_clken2 =
 418                 omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
 419         cm_context.cm_polctrl =
 420                 omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_POLCTRL);
 421         cm_context.iva2_cm_fclken =
 422                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
 423         cm_context.iva2_cm_clken_pll =
 424                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL);
 425         cm_context.core_cm_fclken1 =
 426                 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 427         cm_context.core_cm_fclken3 =
 428                 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
 429         cm_context.sgx_cm_fclken =
 430                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
 431         cm_context.wkup_cm_fclken =
 432                 omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
 433         cm_context.dss_cm_fclken =
 434                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
 435         cm_context.cam_cm_fclken =
 436                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
 437         cm_context.per_cm_fclken =
 438                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
 439         cm_context.usbhost_cm_fclken =
 440                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
 441         cm_context.core_cm_iclken1 =
 442                 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
 443         cm_context.core_cm_iclken2 =
 444                 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
 445         cm_context.core_cm_iclken3 =
 446                 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
 447         cm_context.sgx_cm_iclken =
 448                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
 449         cm_context.wkup_cm_iclken =
 450                 omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
 451         cm_context.dss_cm_iclken =
 452                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
 453         cm_context.cam_cm_iclken =
 454                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
 455         cm_context.per_cm_iclken =
 456                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
 457         cm_context.usbhost_cm_iclken =
 458                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
 459         cm_context.iva2_cm_autoidle2 =
 460                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 461         cm_context.mpu_cm_autoidle2 =
 462                 omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
 463         cm_context.iva2_cm_clkstctrl =
 464                 omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 465         cm_context.mpu_cm_clkstctrl =
 466                 omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
 467         cm_context.core_cm_clkstctrl =
 468                 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
 469         cm_context.sgx_cm_clkstctrl =
 470                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL);
 471         cm_context.dss_cm_clkstctrl =
 472                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
 473         cm_context.cam_cm_clkstctrl =
 474                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
 475         cm_context.per_cm_clkstctrl =
 476                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
 477         cm_context.neon_cm_clkstctrl =
 478                 omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
 479         cm_context.usbhost_cm_clkstctrl =
 480                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 481                                       OMAP2_CM_CLKSTCTRL);
 482         cm_context.core_cm_autoidle1 =
 483                 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
 484         cm_context.core_cm_autoidle2 =
 485                 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
 486         cm_context.core_cm_autoidle3 =
 487                 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
 488         cm_context.wkup_cm_autoidle =
 489                 omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
 490         cm_context.dss_cm_autoidle =
 491                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
 492         cm_context.cam_cm_autoidle =
 493                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
 494         cm_context.per_cm_autoidle =
 495                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 496         cm_context.usbhost_cm_autoidle =
 497                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 498         cm_context.sgx_cm_sleepdep =
 499                 omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 500                                       OMAP3430_CM_SLEEPDEP);
 501         cm_context.dss_cm_sleepdep =
 502                 omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
 503         cm_context.cam_cm_sleepdep =
 504                 omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
 505         cm_context.per_cm_sleepdep =
 506                 omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
 507         cm_context.usbhost_cm_sleepdep =
 508                 omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 509                                       OMAP3430_CM_SLEEPDEP);
 510         cm_context.cm_clkout_ctrl =
 511                 omap2_cm_read_mod_reg(OMAP3430_CCR_MOD,
 512                                       OMAP3_CM_CLKOUT_CTRL_OFFSET);
 513 }
 514
 515 void omap3_cm_restore_context(void)
 516 {
 517         omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
 518                                CM_CLKSEL1);
 519         omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
 520                                CM_CLKSEL2);
 521         omap2_cm_write_mod_reg(cm_context.cm_sysconfig, OCP_MOD,
 522                                OMAP3430_CM_SYSCONFIG);
 523         omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
 524                                CM_CLKSEL);
 525         omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
 526                                CM_CLKSEL);
 527         omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
 528                                CM_CLKSEL);
 529         omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD,
 530                                CM_CLKSEL);
 531         omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
 532                                CM_CLKSEL1);
 533         omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
 534                                OMAP2_CM_CLKSTCTRL);
 535         /*
 536          * As per erratum i671, ROM code does not respect the PER DPLL
 537          * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1.
 538          * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves.
 539          */
 540         omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD,
 541                                CM_AUTOIDLE);
 542         omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD,
 543                                CM_AUTOIDLE2);
 544         omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD,
 545                                OMAP3430ES2_CM_CLKSEL4);
 546         omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD,
 547                                OMAP3430ES2_CM_CLKSEL5);
 548         omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
 549                                OMAP3430ES2_CM_CLKEN2);
 550         omap2_cm_write_mod_reg(cm_context.cm_polctrl, OCP_MOD,
 551                                OMAP3430_CM_POLCTRL);
 552         omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
 553                                CM_FCLKEN);
 554         omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
 555                                OMAP3430_CM_CLKEN_PLL);
 556         omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD,
 557                                CM_FCLKEN1);
 558         omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD,
 559                                OMAP3430ES2_CM_FCLKEN3);
 560         omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
 561                                CM_FCLKEN);
 562         omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
 563         omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
 564                                CM_FCLKEN);
 565         omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
 566                                CM_FCLKEN);
 567         omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD,
 568                                CM_FCLKEN);
 569         omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken,
 570                                OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
 571         omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD,
 572                                CM_ICLKEN1);
 573         omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD,
 574                                CM_ICLKEN2);
 575         omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD,
 576                                CM_ICLKEN3);
 577         omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
 578                                CM_ICLKEN);
 579         omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
 580         omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
 581                                CM_ICLKEN);
 582         omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
 583                                CM_ICLKEN);
 584         omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD,
 585                                CM_ICLKEN);
 586         omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken,
 587                                OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
 588         omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD,
 589                                CM_AUTOIDLE2);
 590         omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD,
 591                                CM_AUTOIDLE2);
 592         omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
 593                                OMAP2_CM_CLKSTCTRL);
 594         omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD,
 595                                OMAP2_CM_CLKSTCTRL);
 596         omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD,
 597                                OMAP2_CM_CLKSTCTRL);
 598         omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
 599                                OMAP2_CM_CLKSTCTRL);
 600         omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
 601                                OMAP2_CM_CLKSTCTRL);
 602         omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
 603                                OMAP2_CM_CLKSTCTRL);
 604         omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
 605                                OMAP2_CM_CLKSTCTRL);
 606         omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
 607                                OMAP2_CM_CLKSTCTRL);
 608         omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl,
 609                                OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
 610         omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD,
 611                                CM_AUTOIDLE1);
 612         omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD,
 613                                CM_AUTOIDLE2);
 614         omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD,
 615                                CM_AUTOIDLE3);
 616         omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD,
 617                                CM_AUTOIDLE);
 618         omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
 619                                CM_AUTOIDLE);
 620         omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
 621                                CM_AUTOIDLE);
 622         omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD,
 623                                CM_AUTOIDLE);
 624         omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle,
 625                                OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 626         omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
 627                                OMAP3430_CM_SLEEPDEP);
 628         omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
 629                                OMAP3430_CM_SLEEPDEP);
 630         omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
 631                                OMAP3430_CM_SLEEPDEP);
 632         omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
 633                                OMAP3430_CM_SLEEPDEP);
 634         omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep,
 635                                OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 636         omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
 637                                OMAP3_CM_CLKOUT_CTRL_OFFSET);
 638 }
 639
 640 void omap3_cm_save_scratchpad_contents(u32 *ptr)
 641 {
 642         *ptr++ = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL);
 643         *ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
 644         *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN);
 645
 646         /*
 647          * As per erratum i671, ROM code does not respect the PER DPLL
 648          * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1.
 649          * Then,  in anycase, clear these bits to avoid extra latencies.
 650          */
 651         *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) &
 652                 ~OMAP3430_AUTO_PERIPH_DPLL_MASK;
 653         *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL);
 654         *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL);
 655         *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3);
 656         *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL);
 657         *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL);
 658         *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL);
 659         *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL);
 660 }
 661
 662 /*
 663  *
 664  */
 665
 666 static struct cm_ll_data omap3xxx_cm_ll_data = {
 667         .split_idlest_reg       = &omap3xxx_cm_split_idlest_reg,
 668         .wait_module_ready      = &omap3xxx_cm_wait_module_ready,
 669 };
 670
 671 int __init omap3xxx_cm_init(void)
 672 {
 673         return cm_register(&omap3xxx_cm_ll_data);
 674 }
 675
 676 static void __exit omap3xxx_cm_exit(void)
 677 {
 678         cm_unregister(&omap3xxx_cm_ll_data);
 679 }
 680 __exitcall(omap3xxx_cm_exit);