arch/arm/mach-davinci/dm355.c

   1 /*
   2  * TI DaVinci DM355 chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11
  12 #include <linux/clk-provider.h>
  13 #include <linux/clk/davinci.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/dmaengine.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/irqchip/irq-davinci-aintc.h>
  20 #include <linux/platform_data/edma.h>
  21 #include <linux/platform_data/gpio-davinci.h>
  22 #include <linux/platform_data/spi-davinci.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/serial_8250.h>
  25 #include <linux/spi/spi.h>
  26
  27 #include <asm/mach/map.h>
  28
  29 #include <mach/common.h>
  30 #include <mach/cputype.h>
  31 #include <mach/mux.h>
  32 #include <mach/serial.h>
  33
  34 #include <clocksource/timer-davinci.h>
  35
  36 #include "asp.h"
  37 #include "davinci.h"
  38 #include "irqs.h"
  39 #include "mux.h"
  40
  41 #define DM355_UART2_BASE        (IO_PHYS + 0x206000)
  42 #define DM355_OSD_BASE          (IO_PHYS + 0x70200)
  43 #define DM355_VENC_BASE         (IO_PHYS + 0x70400)
  44
  45 /*
  46  * Device specific clocks
  47  */
  48 #define DM355_REF_FREQ          24000000        /* 24 or 36 MHz */
  49
  50 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
  51
  52 static struct resource dm355_spi0_resources[] = {
  53         {
  54                 .start = 0x01c66000,
  55                 .end   = 0x01c667ff,
  56                 .flags = IORESOURCE_MEM,
  57         },
  58         {
  59                 .start = DAVINCI_INTC_IRQ(IRQ_DM355_SPINT0_0),
  60                 .flags = IORESOURCE_IRQ,
  61         },
  62 };
  63
  64 static struct davinci_spi_platform_data dm355_spi0_pdata = {
  65         .version        = SPI_VERSION_1,
  66         .num_chipselect = 2,
  67         .cshold_bug     = true,
  68         .dma_event_q    = EVENTQ_1,
  69         .prescaler_limit = 1,
  70 };
  71 static struct platform_device dm355_spi0_device = {
  72         .name = "spi_davinci",
  73         .id = 0,
  74         .dev = {
  75                 .dma_mask = &dm355_spi0_dma_mask,
  76                 .coherent_dma_mask = DMA_BIT_MASK(32),
  77                 .platform_data = &dm355_spi0_pdata,
  78         },
  79         .num_resources = ARRAY_SIZE(dm355_spi0_resources),
  80         .resource = dm355_spi0_resources,
  81 };
  82
  83 void __init dm355_init_spi0(unsigned chipselect_mask,
  84                 const struct spi_board_info *info, unsigned len)
  85 {
  86         /* for now, assume we need MISO */
  87         davinci_cfg_reg(DM355_SPI0_SDI);
  88
  89         /* not all slaves will be wired up */
  90         if (chipselect_mask & BIT(0))
  91                 davinci_cfg_reg(DM355_SPI0_SDENA0);
  92         if (chipselect_mask & BIT(1))
  93                 davinci_cfg_reg(DM355_SPI0_SDENA1);
  94
  95         spi_register_board_info(info, len);
  96
  97         platform_device_register(&dm355_spi0_device);
  98 }
  99
 100 /*----------------------------------------------------------------------*/
 101
 102 #define INTMUX          0x18
 103 #define EVTMUX          0x1c
 104
 105 /*
 106  * Device specific mux setup
 107  *
 108  *      soc     description     mux  mode   mode  mux    dbg
 109  *                              reg  offset mask  mode
 110  */
 111 static const struct mux_config dm355_pins[] = {
 112 #ifdef CONFIG_DAVINCI_MUX
 113 MUX_CFG(DM355,  MMCSD0,         4,   2,     1,    0,     false)
 114
 115 MUX_CFG(DM355,  SD1_CLK,        3,   6,     1,    1,     false)
 116 MUX_CFG(DM355,  SD1_CMD,        3,   7,     1,    1,     false)
 117 MUX_CFG(DM355,  SD1_DATA3,      3,   8,     3,    1,     false)
 118 MUX_CFG(DM355,  SD1_DATA2,      3,   10,    3,    1,     false)
 119 MUX_CFG(DM355,  SD1_DATA1,      3,   12,    3,    1,     false)
 120 MUX_CFG(DM355,  SD1_DATA0,      3,   14,    3,    1,     false)
 121
 122 MUX_CFG(DM355,  I2C_SDA,        3,   19,    1,    1,     false)
 123 MUX_CFG(DM355,  I2C_SCL,        3,   20,    1,    1,     false)
 124
 125 MUX_CFG(DM355,  MCBSP0_BDX,     3,   0,     1,    1,     false)
 126 MUX_CFG(DM355,  MCBSP0_X,       3,   1,     1,    1,     false)
 127 MUX_CFG(DM355,  MCBSP0_BFSX,    3,   2,     1,    1,     false)
 128 MUX_CFG(DM355,  MCBSP0_BDR,     3,   3,     1,    1,     false)
 129 MUX_CFG(DM355,  MCBSP0_R,       3,   4,     1,    1,     false)
 130 MUX_CFG(DM355,  MCBSP0_BFSR,    3,   5,     1,    1,     false)
 131
 132 MUX_CFG(DM355,  SPI0_SDI,       4,   1,     1,    0,     false)
 133 MUX_CFG(DM355,  SPI0_SDENA0,    4,   0,     1,    0,     false)
 134 MUX_CFG(DM355,  SPI0_SDENA1,    3,   28,    1,    1,     false)
 135
 136 INT_CFG(DM355,  INT_EDMA_CC,          2,    1,    1,     false)
 137 INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
 138 INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
 139
 140 EVT_CFG(DM355,  EVT8_ASP1_TX,         0,    1,    0,     false)
 141 EVT_CFG(DM355,  EVT9_ASP1_RX,         1,    1,    0,     false)
 142 EVT_CFG(DM355,  EVT26_MMC0_RX,        2,    1,    0,     false)
 143
 144 MUX_CFG(DM355,  VOUT_FIELD,     1,   18,    3,    1,     false)
 145 MUX_CFG(DM355,  VOUT_FIELD_G70, 1,   18,    3,    0,     false)
 146 MUX_CFG(DM355,  VOUT_HVSYNC,    1,   16,    1,    0,     false)
 147 MUX_CFG(DM355,  VOUT_COUTL_EN,  1,   0,     0xff, 0x55,  false)
 148 MUX_CFG(DM355,  VOUT_COUTH_EN,  1,   8,     0xff, 0x55,  false)
 149
 150 MUX_CFG(DM355,  VIN_PCLK,       0,   14,    1,    1,     false)
 151 MUX_CFG(DM355,  VIN_CAM_WEN,    0,   13,    1,    1,     false)
 152 MUX_CFG(DM355,  VIN_CAM_VD,     0,   12,    1,    1,     false)
 153 MUX_CFG(DM355,  VIN_CAM_HD,     0,   11,    1,    1,     false)
 154 MUX_CFG(DM355,  VIN_YIN_EN,     0,   10,    1,    1,     false)
 155 MUX_CFG(DM355,  VIN_CINL_EN,    0,   0,   0xff, 0x55,    false)
 156 MUX_CFG(DM355,  VIN_CINH_EN,    0,   8,     3,    3,     false)
 157 #endif
 158 };
 159
 160 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 161         [IRQ_DM355_CCDC_VDINT0]         = 2,
 162         [IRQ_DM355_CCDC_VDINT1]         = 6,
 163         [IRQ_DM355_CCDC_VDINT2]         = 6,
 164         [IRQ_DM355_IPIPE_HST]           = 6,
 165         [IRQ_DM355_H3AINT]              = 6,
 166         [IRQ_DM355_IPIPE_SDR]           = 6,
 167         [IRQ_DM355_IPIPEIFINT]          = 6,
 168         [IRQ_DM355_OSDINT]              = 7,
 169         [IRQ_DM355_VENCINT]             = 6,
 170         [IRQ_ASQINT]                    = 6,
 171         [IRQ_IMXINT]                    = 6,
 172         [IRQ_USBINT]                    = 4,
 173         [IRQ_DM355_RTOINT]              = 4,
 174         [IRQ_DM355_UARTINT2]            = 7,
 175         [IRQ_DM355_TINT6]               = 7,
 176         [IRQ_CCINT0]                    = 5,    /* dma */
 177         [IRQ_CCERRINT]                  = 5,    /* dma */
 178         [IRQ_TCERRINT0]                 = 5,    /* dma */
 179         [IRQ_TCERRINT]                  = 5,    /* dma */
 180         [IRQ_DM355_SPINT2_1]            = 7,
 181         [IRQ_DM355_TINT7]               = 4,
 182         [IRQ_DM355_SDIOINT0]            = 7,
 183         [IRQ_MBXINT]                    = 7,
 184         [IRQ_MBRINT]                    = 7,
 185         [IRQ_MMCINT]                    = 7,
 186         [IRQ_DM355_MMCINT1]             = 7,
 187         [IRQ_DM355_PWMINT3]             = 7,
 188         [IRQ_DDRINT]                    = 7,
 189         [IRQ_AEMIFINT]                  = 7,
 190         [IRQ_DM355_SDIOINT1]            = 4,
 191         [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
 192         [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
 193         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 194         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 195         [IRQ_PWMINT0]                   = 7,
 196         [IRQ_PWMINT1]                   = 7,
 197         [IRQ_PWMINT2]                   = 7,
 198         [IRQ_I2C]                       = 3,
 199         [IRQ_UARTINT0]                  = 3,
 200         [IRQ_UARTINT1]                  = 3,
 201         [IRQ_DM355_SPINT0_0]            = 3,
 202         [IRQ_DM355_SPINT0_1]            = 3,
 203         [IRQ_DM355_GPIO0]               = 3,
 204         [IRQ_DM355_GPIO1]               = 7,
 205         [IRQ_DM355_GPIO2]               = 4,
 206         [IRQ_DM355_GPIO3]               = 4,
 207         [IRQ_DM355_GPIO4]               = 7,
 208         [IRQ_DM355_GPIO5]               = 7,
 209         [IRQ_DM355_GPIO6]               = 7,
 210         [IRQ_DM355_GPIO7]               = 7,
 211         [IRQ_DM355_GPIO8]               = 7,
 212         [IRQ_DM355_GPIO9]               = 7,
 213         [IRQ_DM355_GPIOBNK0]            = 7,
 214         [IRQ_DM355_GPIOBNK1]            = 7,
 215         [IRQ_DM355_GPIOBNK2]            = 7,
 216         [IRQ_DM355_GPIOBNK3]            = 7,
 217         [IRQ_DM355_GPIOBNK4]            = 7,
 218         [IRQ_DM355_GPIOBNK5]            = 7,
 219         [IRQ_DM355_GPIOBNK6]            = 7,
 220         [IRQ_COMMTX]                    = 7,
 221         [IRQ_COMMRX]                    = 7,
 222         [IRQ_EMUINT]                    = 7,
 223 };
 224
 225 /*----------------------------------------------------------------------*/
 226
 227 static s8 queue_priority_mapping[][2] = {
 228         /* {event queue no, Priority} */
 229         {0, 3},
 230         {1, 7},
 231         {-1, -1},
 232 };
 233
 234 static const struct dma_slave_map dm355_edma_map[] = {
 235         { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
 236         { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
 237         { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 8) },
 238         { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 9) },
 239         { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
 240         { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
 241         { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
 242         { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
 243         { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
 244         { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
 245         { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
 246         { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
 247         { "dm6441-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
 248         { "dm6441-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
 249 };
 250
 251 static struct edma_soc_info dm355_edma_pdata = {
 252         .queue_priority_mapping = queue_priority_mapping,
 253         .default_queue          = EVENTQ_1,
 254         .slave_map              = dm355_edma_map,
 255         .slavecnt               = ARRAY_SIZE(dm355_edma_map),
 256 };
 257
 258 static struct resource edma_resources[] = {
 259         {
 260                 .name   = "edma3_cc",
 261                 .start  = 0x01c00000,
 262                 .end    = 0x01c00000 + SZ_64K - 1,
 263                 .flags  = IORESOURCE_MEM,
 264         },
 265         {
 266                 .name   = "edma3_tc0",
 267                 .start  = 0x01c10000,
 268                 .end    = 0x01c10000 + SZ_1K - 1,
 269                 .flags  = IORESOURCE_MEM,
 270         },
 271         {
 272                 .name   = "edma3_tc1",
 273                 .start  = 0x01c10400,
 274                 .end    = 0x01c10400 + SZ_1K - 1,
 275                 .flags  = IORESOURCE_MEM,
 276         },
 277         {
 278                 .name   = "edma3_ccint",
 279                 .start  = DAVINCI_INTC_IRQ(IRQ_CCINT0),
 280                 .flags  = IORESOURCE_IRQ,
 281         },
 282         {
 283                 .name   = "edma3_ccerrint",
 284                 .start  = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
 285                 .flags  = IORESOURCE_IRQ,
 286         },
 287         /* not using (or muxing) TC*_ERR */
 288 };
 289
 290 static const struct platform_device_info dm355_edma_device __initconst = {
 291         .name           = "edma",
 292         .id             = 0,
 293         .dma_mask       = DMA_BIT_MASK(32),
 294         .res            = edma_resources,
 295         .num_res        = ARRAY_SIZE(edma_resources),
 296         .data           = &dm355_edma_pdata,
 297         .size_data      = sizeof(dm355_edma_pdata),
 298 };
 299
 300 static struct resource dm355_asp1_resources[] = {
 301         {
 302                 .name   = "mpu",
 303                 .start  = DAVINCI_ASP1_BASE,
 304                 .end    = DAVINCI_ASP1_BASE + SZ_8K - 1,
 305                 .flags  = IORESOURCE_MEM,
 306         },
 307         {
 308                 .start  = DAVINCI_DMA_ASP1_TX,
 309                 .end    = DAVINCI_DMA_ASP1_TX,
 310                 .flags  = IORESOURCE_DMA,
 311         },
 312         {
 313                 .start  = DAVINCI_DMA_ASP1_RX,
 314                 .end    = DAVINCI_DMA_ASP1_RX,
 315                 .flags  = IORESOURCE_DMA,
 316         },
 317 };
 318
 319 static struct platform_device dm355_asp1_device = {
 320         .name           = "davinci-mcbsp",
 321         .id             = 1,
 322         .num_resources  = ARRAY_SIZE(dm355_asp1_resources),
 323         .resource       = dm355_asp1_resources,
 324 };
 325
 326 static void dm355_ccdc_setup_pinmux(void)
 327 {
 328         davinci_cfg_reg(DM355_VIN_PCLK);
 329         davinci_cfg_reg(DM355_VIN_CAM_WEN);
 330         davinci_cfg_reg(DM355_VIN_CAM_VD);
 331         davinci_cfg_reg(DM355_VIN_CAM_HD);
 332         davinci_cfg_reg(DM355_VIN_YIN_EN);
 333         davinci_cfg_reg(DM355_VIN_CINL_EN);
 334         davinci_cfg_reg(DM355_VIN_CINH_EN);
 335 }
 336
 337 static struct resource dm355_vpss_resources[] = {
 338         {
 339                 /* VPSS BL Base address */
 340                 .name           = "vpss",
 341                 .start          = 0x01c70800,
 342                 .end            = 0x01c70800 + 0xff,
 343                 .flags          = IORESOURCE_MEM,
 344         },
 345         {
 346                 /* VPSS CLK Base address */
 347                 .name           = "vpss",
 348                 .start          = 0x01c70000,
 349                 .end            = 0x01c70000 + 0xf,
 350                 .flags          = IORESOURCE_MEM,
 351         },
 352 };
 353
 354 static struct platform_device dm355_vpss_device = {
 355         .name                   = "vpss",
 356         .id                     = -1,
 357         .dev.platform_data      = "dm355_vpss",
 358         .num_resources          = ARRAY_SIZE(dm355_vpss_resources),
 359         .resource               = dm355_vpss_resources,
 360 };
 361
 362 static struct resource vpfe_resources[] = {
 363         {
 364                 .start          = DAVINCI_INTC_IRQ(IRQ_VDINT0),
 365                 .end            = DAVINCI_INTC_IRQ(IRQ_VDINT0),
 366                 .flags          = IORESOURCE_IRQ,
 367         },
 368         {
 369                 .start          = DAVINCI_INTC_IRQ(IRQ_VDINT1),
 370                 .end            = DAVINCI_INTC_IRQ(IRQ_VDINT1),
 371                 .flags          = IORESOURCE_IRQ,
 372         },
 373 };
 374
 375 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
 376 static struct resource dm355_ccdc_resource[] = {
 377         /* CCDC Base address */
 378         {
 379                 .flags          = IORESOURCE_MEM,
 380                 .start          = 0x01c70600,
 381                 .end            = 0x01c70600 + 0x1ff,
 382         },
 383 };
 384 static struct platform_device dm355_ccdc_dev = {
 385         .name           = "dm355_ccdc",
 386         .id             = -1,
 387         .num_resources  = ARRAY_SIZE(dm355_ccdc_resource),
 388         .resource       = dm355_ccdc_resource,
 389         .dev = {
 390                 .dma_mask               = &vpfe_capture_dma_mask,
 391                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 392                 .platform_data          = dm355_ccdc_setup_pinmux,
 393         },
 394 };
 395
 396 static struct platform_device vpfe_capture_dev = {
 397         .name           = CAPTURE_DRV_NAME,
 398         .id             = -1,
 399         .num_resources  = ARRAY_SIZE(vpfe_resources),
 400         .resource       = vpfe_resources,
 401         .dev = {
 402                 .dma_mask               = &vpfe_capture_dma_mask,
 403                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 404         },
 405 };
 406
 407 static struct resource dm355_osd_resources[] = {
 408         {
 409                 .start  = DM355_OSD_BASE,
 410                 .end    = DM355_OSD_BASE + 0x17f,
 411                 .flags  = IORESOURCE_MEM,
 412         },
 413 };
 414
 415 static struct platform_device dm355_osd_dev = {
 416         .name           = DM355_VPBE_OSD_SUBDEV_NAME,
 417         .id             = -1,
 418         .num_resources  = ARRAY_SIZE(dm355_osd_resources),
 419         .resource       = dm355_osd_resources,
 420         .dev            = {
 421                 .dma_mask               = &vpfe_capture_dma_mask,
 422                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 423         },
 424 };
 425
 426 static struct resource dm355_venc_resources[] = {
 427         {
 428                 .start  = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 429                 .end    = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 430                 .flags  = IORESOURCE_IRQ,
 431         },
 432         /* venc registers io space */
 433         {
 434                 .start  = DM355_VENC_BASE,
 435                 .end    = DM355_VENC_BASE + 0x17f,
 436                 .flags  = IORESOURCE_MEM,
 437         },
 438         /* VDAC config register io space */
 439         {
 440                 .start  = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
 441                 .end    = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
 442                 .flags  = IORESOURCE_MEM,
 443         },
 444 };
 445
 446 static struct resource dm355_v4l2_disp_resources[] = {
 447         {
 448                 .start  = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 449                 .end    = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 450                 .flags  = IORESOURCE_IRQ,
 451         },
 452         /* venc registers io space */
 453         {
 454                 .start  = DM355_VENC_BASE,
 455                 .end    = DM355_VENC_BASE + 0x17f,
 456                 .flags  = IORESOURCE_MEM,
 457         },
 458 };
 459
 460 static int dm355_vpbe_setup_pinmux(u32 if_type, int field)
 461 {
 462         switch (if_type) {
 463         case MEDIA_BUS_FMT_SGRBG8_1X8:
 464                 davinci_cfg_reg(DM355_VOUT_FIELD_G70);
 465                 break;
 466         case MEDIA_BUS_FMT_YUYV10_1X20:
 467                 if (field)
 468                         davinci_cfg_reg(DM355_VOUT_FIELD);
 469                 else
 470                         davinci_cfg_reg(DM355_VOUT_FIELD_G70);
 471                 break;
 472         default:
 473                 return -EINVAL;
 474         }
 475
 476         davinci_cfg_reg(DM355_VOUT_COUTL_EN);
 477         davinci_cfg_reg(DM355_VOUT_COUTH_EN);
 478
 479         return 0;
 480 }
 481
 482 static int dm355_venc_setup_clock(enum vpbe_enc_timings_type type,
 483                                    unsigned int pclock)
 484 {
 485         void __iomem *vpss_clk_ctrl_reg;
 486
 487         vpss_clk_ctrl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
 488
 489         switch (type) {
 490         case VPBE_ENC_STD:
 491                 writel(VPSS_DACCLKEN_ENABLE | VPSS_VENCCLKEN_ENABLE,
 492                        vpss_clk_ctrl_reg);
 493                 break;
 494         case VPBE_ENC_DV_TIMINGS:
 495                 if (pclock > 27000000)
 496                         /*
 497                          * For HD, use external clock source since we cannot
 498                          * support HD mode with internal clocks.
 499                          */
 500                         writel(VPSS_MUXSEL_EXTCLK_ENABLE, vpss_clk_ctrl_reg);
 501                 break;
 502         default:
 503                 return -EINVAL;
 504         }
 505
 506         return 0;
 507 }
 508
 509 static struct platform_device dm355_vpbe_display = {
 510         .name           = "vpbe-v4l2",
 511         .id             = -1,
 512         .num_resources  = ARRAY_SIZE(dm355_v4l2_disp_resources),
 513         .resource       = dm355_v4l2_disp_resources,
 514         .dev            = {
 515                 .dma_mask               = &vpfe_capture_dma_mask,
 516                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 517         },
 518 };
 519
 520 static struct venc_platform_data dm355_venc_pdata = {
 521         .setup_pinmux   = dm355_vpbe_setup_pinmux,
 522         .setup_clock    = dm355_venc_setup_clock,
 523 };
 524
 525 static struct platform_device dm355_venc_dev = {
 526         .name           = DM355_VPBE_VENC_SUBDEV_NAME,
 527         .id             = -1,
 528         .num_resources  = ARRAY_SIZE(dm355_venc_resources),
 529         .resource       = dm355_venc_resources,
 530         .dev            = {
 531                 .dma_mask               = &vpfe_capture_dma_mask,
 532                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 533                 .platform_data          = (void *)&dm355_venc_pdata,
 534         },
 535 };
 536
 537 static struct platform_device dm355_vpbe_dev = {
 538         .name           = "vpbe_controller",
 539         .id             = -1,
 540         .dev            = {
 541                 .dma_mask               = &vpfe_capture_dma_mask,
 542                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 543         },
 544 };
 545
 546 static struct resource dm355_gpio_resources[] = {
 547         {       /* registers */
 548                 .start  = DAVINCI_GPIO_BASE,
 549                 .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
 550                 .flags  = IORESOURCE_MEM,
 551         },
 552         {       /* interrupt */
 553                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
 554                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK0),
 555                 .flags  = IORESOURCE_IRQ,
 556         },
 557         {
 558                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
 559                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK1),
 560                 .flags  = IORESOURCE_IRQ,
 561         },
 562         {
 563                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
 564                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK2),
 565                 .flags  = IORESOURCE_IRQ,
 566         },
 567         {
 568                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
 569                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK3),
 570                 .flags  = IORESOURCE_IRQ,
 571         },
 572         {
 573                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
 574                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK4),
 575                 .flags  = IORESOURCE_IRQ,
 576         },
 577         {
 578                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
 579                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK5),
 580                 .flags  = IORESOURCE_IRQ,
 581         },
 582         {
 583                 .start  = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
 584                 .end    = DAVINCI_INTC_IRQ(IRQ_DM355_GPIOBNK6),
 585                 .flags  = IORESOURCE_IRQ,
 586         },
 587 };
 588
 589 static struct davinci_gpio_platform_data dm355_gpio_platform_data = {
 590         .no_auto_base   = true,
 591         .base           = 0,
 592         .ngpio          = 104,
 593 };
 594
 595 int __init dm355_gpio_register(void)
 596 {
 597         return davinci_gpio_register(dm355_gpio_resources,
 598                                      ARRAY_SIZE(dm355_gpio_resources),
 599                                      &dm355_gpio_platform_data);
 600 }
 601 /*----------------------------------------------------------------------*/
 602
 603 static struct map_desc dm355_io_desc[] = {
 604         {
 605                 .virtual        = IO_VIRT,
 606                 .pfn            = __phys_to_pfn(IO_PHYS),
 607                 .length         = IO_SIZE,
 608                 .type           = MT_DEVICE
 609         },
 610 };
 611
 612 /* Contents of JTAG ID register used to identify exact cpu type */
 613 static struct davinci_id dm355_ids[] = {
 614         {
 615                 .variant        = 0x0,
 616                 .part_no        = 0xb73b,
 617                 .manufacturer   = 0x00f,
 618                 .cpu_id         = DAVINCI_CPU_ID_DM355,
 619                 .name           = "dm355",
 620         },
 621 };
 622
 623 /*
 624  * Bottom half of timer0 is used for clockevent, top half is used for
 625  * clocksource.
 626  */
 627 static const struct davinci_timer_cfg dm355_timer_cfg = {
 628         .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
 629         .irq = {
 630                 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
 631                 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
 632         },
 633 };
 634
 635 static struct plat_serial8250_port dm355_serial0_platform_data[] = {
 636         {
 637                 .mapbase        = DAVINCI_UART0_BASE,
 638                 .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
 639                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 640                                   UPF_IOREMAP,
 641                 .iotype         = UPIO_MEM,
 642                 .regshift       = 2,
 643         },
 644         {
 645                 .flags  = 0,
 646         }
 647 };
 648 static struct plat_serial8250_port dm355_serial1_platform_data[] = {
 649         {
 650                 .mapbase        = DAVINCI_UART1_BASE,
 651                 .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
 652                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 653                                   UPF_IOREMAP,
 654                 .iotype         = UPIO_MEM,
 655                 .regshift       = 2,
 656         },
 657         {
 658                 .flags  = 0,
 659         }
 660 };
 661 static struct plat_serial8250_port dm355_serial2_platform_data[] = {
 662         {
 663                 .mapbase        = DM355_UART2_BASE,
 664                 .irq            = DAVINCI_INTC_IRQ(IRQ_DM355_UARTINT2),
 665                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 666                                   UPF_IOREMAP,
 667                 .iotype         = UPIO_MEM,
 668                 .regshift       = 2,
 669         },
 670         {
 671                 .flags  = 0,
 672         }
 673 };
 674
 675 struct platform_device dm355_serial_device[] = {
 676         {
 677                 .name                   = "serial8250",
 678                 .id                     = PLAT8250_DEV_PLATFORM,
 679                 .dev                    = {
 680                         .platform_data  = dm355_serial0_platform_data,
 681                 }
 682         },
 683         {
 684                 .name                   = "serial8250",
 685                 .id                     = PLAT8250_DEV_PLATFORM1,
 686                 .dev                    = {
 687                         .platform_data  = dm355_serial1_platform_data,
 688                 }
 689         },
 690         {
 691                 .name                   = "serial8250",
 692                 .id                     = PLAT8250_DEV_PLATFORM2,
 693                 .dev                    = {
 694                         .platform_data  = dm355_serial2_platform_data,
 695                 }
 696         },
 697         {
 698         }
 699 };
 700
 701 static const struct davinci_soc_info davinci_soc_info_dm355 = {
 702         .io_desc                = dm355_io_desc,
 703         .io_desc_num            = ARRAY_SIZE(dm355_io_desc),
 704         .jtag_id_reg            = 0x01c40028,
 705         .ids                    = dm355_ids,
 706         .ids_num                = ARRAY_SIZE(dm355_ids),
 707         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
 708         .pinmux_pins            = dm355_pins,
 709         .pinmux_pins_num        = ARRAY_SIZE(dm355_pins),
 710         .sram_dma               = 0x00010000,
 711         .sram_len               = SZ_32K,
 712 };
 713
 714 void __init dm355_init_asp1(u32 evt_enable)
 715 {
 716         /* we don't use ASP1 IRQs, or we'd need to mux them ... */
 717         if (evt_enable & ASP1_TX_EVT_EN)
 718                 davinci_cfg_reg(DM355_EVT8_ASP1_TX);
 719
 720         if (evt_enable & ASP1_RX_EVT_EN)
 721                 davinci_cfg_reg(DM355_EVT9_ASP1_RX);
 722
 723         platform_device_register(&dm355_asp1_device);
 724 }
 725
 726 void __init dm355_init(void)
 727 {
 728         davinci_common_init(&davinci_soc_info_dm355);
 729         davinci_map_sysmod();
 730 }
 731
 732 void __init dm355_init_time(void)
 733 {
 734         void __iomem *pll1, *psc;
 735         struct clk *clk;
 736         int rv;
 737
 738         clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM355_REF_FREQ);
 739
 740         pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
 741         dm355_pll1_init(NULL, pll1, NULL);
 742
 743         psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
 744         dm355_psc_init(NULL, psc);
 745
 746         clk = clk_get(NULL, "timer0");
 747         if (WARN_ON(IS_ERR(clk))) {
 748                 pr_err("Unable to get the timer clock\n");
 749                 return;
 750         }
 751
 752         rv = davinci_timer_register(clk, &dm355_timer_cfg);
 753         WARN(rv, "Unable to register the timer: %d\n", rv);
 754 }
 755
 756 static struct resource dm355_pll2_resources[] = {
 757         {
 758                 .start  = DAVINCI_PLL2_BASE,
 759                 .end    = DAVINCI_PLL2_BASE + SZ_1K - 1,
 760                 .flags  = IORESOURCE_MEM,
 761         },
 762 };
 763
 764 static struct platform_device dm355_pll2_device = {
 765         .name           = "dm355-pll2",
 766         .id             = -1,
 767         .resource       = dm355_pll2_resources,
 768         .num_resources  = ARRAY_SIZE(dm355_pll2_resources),
 769 };
 770
 771 void __init dm355_register_clocks(void)
 772 {
 773         /* PLL1 and PSC are registered in dm355_init_time() */
 774         platform_device_register(&dm355_pll2_device);
 775 }
 776
 777 int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
 778                                 struct vpbe_config *vpbe_cfg)
 779 {
 780         if (vpfe_cfg || vpbe_cfg)
 781                 platform_device_register(&dm355_vpss_device);
 782
 783         if (vpfe_cfg) {
 784                 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
 785                 platform_device_register(&dm355_ccdc_dev);
 786                 platform_device_register(&vpfe_capture_dev);
 787         }
 788
 789         if (vpbe_cfg) {
 790                 dm355_vpbe_dev.dev.platform_data = vpbe_cfg;
 791                 platform_device_register(&dm355_osd_dev);
 792                 platform_device_register(&dm355_venc_dev);
 793                 platform_device_register(&dm355_vpbe_dev);
 794                 platform_device_register(&dm355_vpbe_display);
 795         }
 796
 797         return 0;
 798 }
 799
 800 static const struct davinci_aintc_config dm355_aintc_config = {
 801         .reg = {
 802                 .start          = DAVINCI_ARM_INTC_BASE,
 803                 .end            = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
 804                 .flags          = IORESOURCE_MEM,
 805         },
 806         .num_irqs               = 64,
 807         .prios                  = dm355_default_priorities,
 808 };
 809
 810 void __init dm355_init_irq(void)
 811 {
 812         davinci_aintc_init(&dm355_aintc_config);
 813 }
 814
 815 static int __init dm355_init_devices(void)
 816 {
 817         struct platform_device *edma_pdev;
 818         int ret = 0;
 819
 820         if (!cpu_is_davinci_dm355())
 821                 return 0;
 822
 823         davinci_cfg_reg(DM355_INT_EDMA_CC);
 824         edma_pdev = platform_device_register_full(&dm355_edma_device);
 825         if (IS_ERR(edma_pdev)) {
 826                 pr_warn("%s: Failed to register eDMA\n", __func__);
 827                 return PTR_ERR(edma_pdev);
 828         }
 829
 830         ret = davinci_init_wdt();
 831         if (ret)
 832                 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
 833
 834         return ret;
 835 }
 836 postcore_initcall(dm355_init_devices);