arch/arm/mach-davinci/da850.c

   1 /*
   2  * TI DA850/OMAP-L138 chip specific setup
   3  *
   4  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * Derived from: arch/arm/mach-davinci/da830.c
   7  * Original Copyrights follow:
   8  *
   9  * 2009 (c) MontaVista Software, Inc. This file is licensed under
  10  * the terms of the GNU General Public License version 2. This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14 #include <linux/clkdev.h>
  15 #include <linux/gpio.h>
  16 #include <linux/init.h>
  17 #include <linux/clk.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/cpufreq.h>
  20 #include <linux/regulator/consumer.h>
  21 #include <linux/platform_data/gpio-davinci.h>
  22
  23 #include <asm/mach/map.h>
  24
  25 #include "psc.h"
  26 #include <mach/irqs.h>
  27 #include <mach/cputype.h>
  28 #include <mach/common.h>
  29 #include <mach/time.h>
  30 #include <mach/da8xx.h>
  31 #include <mach/cpufreq.h>
  32 #include <mach/pm.h>
  33
  34 #include "clock.h"
  35 #include "mux.h"
  36
  37 #define DA850_PLL1_BASE         0x01e1a000
  38 #define DA850_TIMER64P2_BASE    0x01f0c000
  39 #define DA850_TIMER64P3_BASE    0x01f0d000
  40
  41 #define DA850_REF_FREQ          24000000
  42
  43 #define CFGCHIP3_ASYNC3_CLKSRC  BIT(4)
  44 #define CFGCHIP3_PLL1_MASTER_LOCK       BIT(5)
  45 #define CFGCHIP0_PLL_MASTER_LOCK        BIT(4)
  46
  47 static int da850_set_armrate(struct clk *clk, unsigned long rate);
  48 static int da850_round_armrate(struct clk *clk, unsigned long rate);
  49 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
  50
  51 static struct pll_data pll0_data = {
  52         .num            = 1,
  53         .phys_base      = DA8XX_PLL0_BASE,
  54         .flags          = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
  55 };
  56
  57 static struct clk ref_clk = {
  58         .name           = "ref_clk",
  59         .rate           = DA850_REF_FREQ,
  60         .set_rate       = davinci_simple_set_rate,
  61 };
  62
  63 static struct clk pll0_clk = {
  64         .name           = "pll0",
  65         .parent         = &ref_clk,
  66         .pll_data       = &pll0_data,
  67         .flags          = CLK_PLL,
  68         .set_rate       = da850_set_pll0rate,
  69 };
  70
  71 static struct clk pll0_aux_clk = {
  72         .name           = "pll0_aux_clk",
  73         .parent         = &pll0_clk,
  74         .flags          = CLK_PLL | PRE_PLL,
  75 };
  76
  77 static struct clk pll0_sysclk1 = {
  78         .name           = "pll0_sysclk1",
  79         .parent         = &pll0_clk,
  80         .flags          = CLK_PLL,
  81         .div_reg        = PLLDIV1,
  82 };
  83
  84 static struct clk pll0_sysclk2 = {
  85         .name           = "pll0_sysclk2",
  86         .parent         = &pll0_clk,
  87         .flags          = CLK_PLL,
  88         .div_reg        = PLLDIV2,
  89 };
  90
  91 static struct clk pll0_sysclk3 = {
  92         .name           = "pll0_sysclk3",
  93         .parent         = &pll0_clk,
  94         .flags          = CLK_PLL,
  95         .div_reg        = PLLDIV3,
  96         .set_rate       = davinci_set_sysclk_rate,
  97         .maxrate        = 100000000,
  98 };
  99
 100 static struct clk pll0_sysclk4 = {
 101         .name           = "pll0_sysclk4",
 102         .parent         = &pll0_clk,
 103         .flags          = CLK_PLL,
 104         .div_reg        = PLLDIV4,
 105 };
 106
 107 static struct clk pll0_sysclk5 = {
 108         .name           = "pll0_sysclk5",
 109         .parent         = &pll0_clk,
 110         .flags          = CLK_PLL,
 111         .div_reg        = PLLDIV5,
 112 };
 113
 114 static struct clk pll0_sysclk6 = {
 115         .name           = "pll0_sysclk6",
 116         .parent         = &pll0_clk,
 117         .flags          = CLK_PLL,
 118         .div_reg        = PLLDIV6,
 119 };
 120
 121 static struct clk pll0_sysclk7 = {
 122         .name           = "pll0_sysclk7",
 123         .parent         = &pll0_clk,
 124         .flags          = CLK_PLL,
 125         .div_reg        = PLLDIV7,
 126 };
 127
 128 static struct pll_data pll1_data = {
 129         .num            = 2,
 130         .phys_base      = DA850_PLL1_BASE,
 131         .flags          = PLL_HAS_POSTDIV,
 132 };
 133
 134 static struct clk pll1_clk = {
 135         .name           = "pll1",
 136         .parent         = &ref_clk,
 137         .pll_data       = &pll1_data,
 138         .flags          = CLK_PLL,
 139 };
 140
 141 static struct clk pll1_aux_clk = {
 142         .name           = "pll1_aux_clk",
 143         .parent         = &pll1_clk,
 144         .flags          = CLK_PLL | PRE_PLL,
 145 };
 146
 147 static struct clk pll1_sysclk2 = {
 148         .name           = "pll1_sysclk2",
 149         .parent         = &pll1_clk,
 150         .flags          = CLK_PLL,
 151         .div_reg        = PLLDIV2,
 152 };
 153
 154 static struct clk pll1_sysclk3 = {
 155         .name           = "pll1_sysclk3",
 156         .parent         = &pll1_clk,
 157         .flags          = CLK_PLL,
 158         .div_reg        = PLLDIV3,
 159 };
 160
 161 static int da850_async3_set_parent(struct clk *clk, struct clk *parent)
 162 {
 163         u32 val;
 164
 165         val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
 166
 167         if (parent == &pll0_sysclk2) {
 168                 val &= ~CFGCHIP3_ASYNC3_CLKSRC;
 169         } else if (parent == &pll1_sysclk2) {
 170                 val |= CFGCHIP3_ASYNC3_CLKSRC;
 171         } else {
 172                 pr_err("Bad parent on async3 clock mux\n");
 173                 return -EINVAL;
 174         }
 175
 176         writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
 177
 178         return 0;
 179 }
 180
 181 static struct clk async3_clk = {
 182         .name           = "async3",
 183         .parent         = &pll1_sysclk2,
 184         .set_parent     = da850_async3_set_parent,
 185 };
 186
 187 static struct clk i2c0_clk = {
 188         .name           = "i2c0",
 189         .parent         = &pll0_aux_clk,
 190 };
 191
 192 static struct clk timerp64_0_clk = {
 193         .name           = "timer0",
 194         .parent         = &pll0_aux_clk,
 195 };
 196
 197 static struct clk timerp64_1_clk = {
 198         .name           = "timer1",
 199         .parent         = &pll0_aux_clk,
 200 };
 201
 202 static struct clk arm_rom_clk = {
 203         .name           = "arm_rom",
 204         .parent         = &pll0_sysclk2,
 205         .lpsc           = DA8XX_LPSC0_ARM_RAM_ROM,
 206         .flags          = ALWAYS_ENABLED,
 207 };
 208
 209 static struct clk tpcc0_clk = {
 210         .name           = "tpcc0",
 211         .parent         = &pll0_sysclk2,
 212         .lpsc           = DA8XX_LPSC0_TPCC,
 213         .flags          = ALWAYS_ENABLED | CLK_PSC,
 214 };
 215
 216 static struct clk tptc0_clk = {
 217         .name           = "tptc0",
 218         .parent         = &pll0_sysclk2,
 219         .lpsc           = DA8XX_LPSC0_TPTC0,
 220         .flags          = ALWAYS_ENABLED,
 221 };
 222
 223 static struct clk tptc1_clk = {
 224         .name           = "tptc1",
 225         .parent         = &pll0_sysclk2,
 226         .lpsc           = DA8XX_LPSC0_TPTC1,
 227         .flags          = ALWAYS_ENABLED,
 228 };
 229
 230 static struct clk tpcc1_clk = {
 231         .name           = "tpcc1",
 232         .parent         = &pll0_sysclk2,
 233         .lpsc           = DA850_LPSC1_TPCC1,
 234         .gpsc           = 1,
 235         .flags          = CLK_PSC | ALWAYS_ENABLED,
 236 };
 237
 238 static struct clk tptc2_clk = {
 239         .name           = "tptc2",
 240         .parent         = &pll0_sysclk2,
 241         .lpsc           = DA850_LPSC1_TPTC2,
 242         .gpsc           = 1,
 243         .flags          = ALWAYS_ENABLED,
 244 };
 245
 246 static struct clk pruss_clk = {
 247         .name           = "pruss",
 248         .parent         = &pll0_sysclk2,
 249         .lpsc           = DA8XX_LPSC0_PRUSS,
 250 };
 251
 252 static struct clk uart0_clk = {
 253         .name           = "uart0",
 254         .parent         = &pll0_sysclk2,
 255         .lpsc           = DA8XX_LPSC0_UART0,
 256 };
 257
 258 static struct clk uart1_clk = {
 259         .name           = "uart1",
 260         .parent         = &async3_clk,
 261         .lpsc           = DA8XX_LPSC1_UART1,
 262         .gpsc           = 1,
 263 };
 264
 265 static struct clk uart2_clk = {
 266         .name           = "uart2",
 267         .parent         = &async3_clk,
 268         .lpsc           = DA8XX_LPSC1_UART2,
 269         .gpsc           = 1,
 270 };
 271
 272 static struct clk aintc_clk = {
 273         .name           = "aintc",
 274         .parent         = &pll0_sysclk4,
 275         .lpsc           = DA8XX_LPSC0_AINTC,
 276         .flags          = ALWAYS_ENABLED,
 277 };
 278
 279 static struct clk gpio_clk = {
 280         .name           = "gpio",
 281         .parent         = &pll0_sysclk4,
 282         .lpsc           = DA8XX_LPSC1_GPIO,
 283         .gpsc           = 1,
 284 };
 285
 286 static struct clk i2c1_clk = {
 287         .name           = "i2c1",
 288         .parent         = &pll0_sysclk4,
 289         .lpsc           = DA8XX_LPSC1_I2C,
 290         .gpsc           = 1,
 291 };
 292
 293 static struct clk emif3_clk = {
 294         .name           = "emif3",
 295         .parent         = &pll0_sysclk5,
 296         .lpsc           = DA8XX_LPSC1_EMIF3C,
 297         .gpsc           = 1,
 298         .flags          = ALWAYS_ENABLED,
 299 };
 300
 301 static struct clk arm_clk = {
 302         .name           = "arm",
 303         .parent         = &pll0_sysclk6,
 304         .lpsc           = DA8XX_LPSC0_ARM,
 305         .flags          = ALWAYS_ENABLED,
 306         .set_rate       = da850_set_armrate,
 307         .round_rate     = da850_round_armrate,
 308 };
 309
 310 static struct clk rmii_clk = {
 311         .name           = "rmii",
 312         .parent         = &pll0_sysclk7,
 313 };
 314
 315 static struct clk emac_clk = {
 316         .name           = "emac",
 317         .parent         = &pll0_sysclk4,
 318         .lpsc           = DA8XX_LPSC1_CPGMAC,
 319         .gpsc           = 1,
 320 };
 321
 322 /*
 323  * In order to avoid adding the emac_clk to the clock lookup table twice (and
 324  * screwing up the linked list in the process) create a separate clock for
 325  * mdio inheriting the rate from emac_clk.
 326  */
 327 static struct clk mdio_clk = {
 328         .name           = "mdio",
 329         .parent         = &emac_clk,
 330 };
 331
 332 static struct clk mcasp_clk = {
 333         .name           = "mcasp",
 334         .parent         = &async3_clk,
 335         .lpsc           = DA8XX_LPSC1_McASP0,
 336         .gpsc           = 1,
 337 };
 338
 339 static struct clk mcbsp0_clk = {
 340         .name           = "mcbsp0",
 341         .parent         = &async3_clk,
 342         .lpsc           = DA850_LPSC1_McBSP0,
 343         .gpsc           = 1,
 344 };
 345
 346 static struct clk mcbsp1_clk = {
 347         .name           = "mcbsp1",
 348         .parent         = &async3_clk,
 349         .lpsc           = DA850_LPSC1_McBSP1,
 350         .gpsc           = 1,
 351 };
 352
 353 static struct clk lcdc_clk = {
 354         .name           = "lcdc",
 355         .parent         = &pll0_sysclk2,
 356         .lpsc           = DA8XX_LPSC1_LCDC,
 357         .gpsc           = 1,
 358 };
 359
 360 static struct clk mmcsd0_clk = {
 361         .name           = "mmcsd0",
 362         .parent         = &pll0_sysclk2,
 363         .lpsc           = DA8XX_LPSC0_MMC_SD,
 364 };
 365
 366 static struct clk mmcsd1_clk = {
 367         .name           = "mmcsd1",
 368         .parent         = &pll0_sysclk2,
 369         .lpsc           = DA850_LPSC1_MMC_SD1,
 370         .gpsc           = 1,
 371 };
 372
 373 static struct clk aemif_clk = {
 374         .name           = "aemif",
 375         .parent         = &pll0_sysclk3,
 376         .lpsc           = DA8XX_LPSC0_EMIF25,
 377         .flags          = ALWAYS_ENABLED,
 378 };
 379
 380 /*
 381  * In order to avoid adding the aemif_clk to the clock lookup table twice (and
 382  * screwing up the linked list in the process) create a separate clock for
 383  * nand inheriting the rate from aemif_clk.
 384  */
 385 static struct clk aemif_nand_clk = {
 386         .name           = "nand",
 387         .parent         = &aemif_clk,
 388 };
 389
 390 static struct clk usb11_clk = {
 391         .name           = "usb11",
 392         .parent         = &pll0_sysclk4,
 393         .lpsc           = DA8XX_LPSC1_USB11,
 394         .gpsc           = 1,
 395 };
 396
 397 static struct clk usb20_clk = {
 398         .name           = "usb20",
 399         .parent         = &pll0_sysclk2,
 400         .lpsc           = DA8XX_LPSC1_USB20,
 401         .gpsc           = 1,
 402 };
 403
 404 static struct clk cppi41_clk = {
 405         .name           = "cppi41",
 406         .parent         = &usb20_clk,
 407 };
 408
 409 static struct clk spi0_clk = {
 410         .name           = "spi0",
 411         .parent         = &pll0_sysclk2,
 412         .lpsc           = DA8XX_LPSC0_SPI0,
 413 };
 414
 415 static struct clk spi1_clk = {
 416         .name           = "spi1",
 417         .parent         = &async3_clk,
 418         .lpsc           = DA8XX_LPSC1_SPI1,
 419         .gpsc           = 1,
 420 };
 421
 422 static struct clk vpif_clk = {
 423         .name           = "vpif",
 424         .parent         = &pll0_sysclk2,
 425         .lpsc           = DA850_LPSC1_VPIF,
 426         .gpsc           = 1,
 427 };
 428
 429 static struct clk sata_clk = {
 430         .name           = "sata",
 431         .parent         = &pll0_sysclk2,
 432         .lpsc           = DA850_LPSC1_SATA,
 433         .gpsc           = 1,
 434         .flags          = PSC_FORCE,
 435 };
 436
 437 static struct clk dsp_clk = {
 438         .name           = "dsp",
 439         .parent         = &pll0_sysclk1,
 440         .domain         = DAVINCI_GPSC_DSPDOMAIN,
 441         .lpsc           = DA8XX_LPSC0_GEM,
 442         .flags          = PSC_LRST | PSC_FORCE,
 443 };
 444
 445 static struct clk ehrpwm_clk = {
 446         .name           = "ehrpwm",
 447         .parent         = &async3_clk,
 448         .lpsc           = DA8XX_LPSC1_PWM,
 449         .gpsc           = 1,
 450 };
 451
 452 static struct clk ehrpwm0_clk = {
 453         .name           = "ehrpwm0",
 454         .parent         = &ehrpwm_clk,
 455 };
 456
 457 static struct clk ehrpwm1_clk = {
 458         .name           = "ehrpwm1",
 459         .parent         = &ehrpwm_clk,
 460 };
 461
 462 #define DA8XX_EHRPWM_TBCLKSYNC  BIT(12)
 463
 464 static void ehrpwm_tblck_enable(struct clk *clk)
 465 {
 466         u32 val;
 467
 468         val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
 469         val |= DA8XX_EHRPWM_TBCLKSYNC;
 470         writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
 471 }
 472
 473 static void ehrpwm_tblck_disable(struct clk *clk)
 474 {
 475         u32 val;
 476
 477         val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
 478         val &= ~DA8XX_EHRPWM_TBCLKSYNC;
 479         writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP1_REG));
 480 }
 481
 482 static struct clk ehrpwm_tbclk = {
 483         .name           = "ehrpwm_tbclk",
 484         .parent         = &ehrpwm_clk,
 485         .clk_enable     = ehrpwm_tblck_enable,
 486         .clk_disable    = ehrpwm_tblck_disable,
 487 };
 488
 489 static struct clk ehrpwm0_tbclk = {
 490         .name           = "ehrpwm0_tbclk",
 491         .parent         = &ehrpwm_tbclk,
 492 };
 493
 494 static struct clk ehrpwm1_tbclk = {
 495         .name           = "ehrpwm1_tbclk",
 496         .parent         = &ehrpwm_tbclk,
 497 };
 498
 499 static struct clk ecap_clk = {
 500         .name           = "ecap",
 501         .parent         = &async3_clk,
 502         .lpsc           = DA8XX_LPSC1_ECAP,
 503         .gpsc           = 1,
 504 };
 505
 506 static struct clk ecap0_clk = {
 507         .name           = "ecap0_clk",
 508         .parent         = &ecap_clk,
 509 };
 510
 511 static struct clk ecap1_clk = {
 512         .name           = "ecap1_clk",
 513         .parent         = &ecap_clk,
 514 };
 515
 516 static struct clk ecap2_clk = {
 517         .name           = "ecap2_clk",
 518         .parent         = &ecap_clk,
 519 };
 520
 521 static struct clk_lookup da850_clks[] = {
 522         CLK(NULL,               "ref",          &ref_clk),
 523         CLK(NULL,               "pll0",         &pll0_clk),
 524         CLK(NULL,               "pll0_aux",     &pll0_aux_clk),
 525         CLK(NULL,               "pll0_sysclk1", &pll0_sysclk1),
 526         CLK(NULL,               "pll0_sysclk2", &pll0_sysclk2),
 527         CLK(NULL,               "pll0_sysclk3", &pll0_sysclk3),
 528         CLK(NULL,               "pll0_sysclk4", &pll0_sysclk4),
 529         CLK(NULL,               "pll0_sysclk5", &pll0_sysclk5),
 530         CLK(NULL,               "pll0_sysclk6", &pll0_sysclk6),
 531         CLK(NULL,               "pll0_sysclk7", &pll0_sysclk7),
 532         CLK(NULL,               "pll1",         &pll1_clk),
 533         CLK(NULL,               "pll1_aux",     &pll1_aux_clk),
 534         CLK(NULL,               "pll1_sysclk2", &pll1_sysclk2),
 535         CLK(NULL,               "pll1_sysclk3", &pll1_sysclk3),
 536         CLK(NULL,               "async3",       &async3_clk),
 537         CLK("i2c_davinci.1",    NULL,           &i2c0_clk),
 538         CLK(NULL,               "timer0",       &timerp64_0_clk),
 539         CLK("davinci-wdt",      NULL,           &timerp64_1_clk),
 540         CLK(NULL,               "arm_rom",      &arm_rom_clk),
 541         CLK(NULL,               "tpcc0",        &tpcc0_clk),
 542         CLK(NULL,               "tptc0",        &tptc0_clk),
 543         CLK(NULL,               "tptc1",        &tptc1_clk),
 544         CLK(NULL,               "tpcc1",        &tpcc1_clk),
 545         CLK(NULL,               "tptc2",        &tptc2_clk),
 546         CLK("pruss_uio",        "pruss",        &pruss_clk),
 547         CLK("serial8250.0",     NULL,           &uart0_clk),
 548         CLK("serial8250.1",     NULL,           &uart1_clk),
 549         CLK("serial8250.2",     NULL,           &uart2_clk),
 550         CLK(NULL,               "aintc",        &aintc_clk),
 551         CLK(NULL,               "gpio",         &gpio_clk),
 552         CLK("i2c_davinci.2",    NULL,           &i2c1_clk),
 553         CLK(NULL,               "emif3",        &emif3_clk),
 554         CLK(NULL,               "arm",          &arm_clk),
 555         CLK(NULL,               "rmii",         &rmii_clk),
 556         CLK("davinci_emac.1",   NULL,           &emac_clk),
 557         CLK("davinci_mdio.0",   "fck",          &mdio_clk),
 558         CLK("davinci-mcasp.0",  NULL,           &mcasp_clk),
 559         CLK("davinci-mcbsp.0",  NULL,           &mcbsp0_clk),
 560         CLK("davinci-mcbsp.1",  NULL,           &mcbsp1_clk),
 561         CLK("da8xx_lcdc.0",     "fck",          &lcdc_clk),
 562         CLK("da830-mmc.0",      NULL,           &mmcsd0_clk),
 563         CLK("da830-mmc.1",      NULL,           &mmcsd1_clk),
 564         CLK("ti-aemif",         NULL,           &aemif_clk),
 565         CLK("davinci-nand.0",   "aemif",        &aemif_nand_clk),
 566         CLK("ohci-da8xx",       "usb11",        &usb11_clk),
 567         CLK("musb-da8xx",       "usb20",        &usb20_clk),
 568         CLK("cppi41-dmaengine", NULL,           &cppi41_clk),
 569         CLK("spi_davinci.0",    NULL,           &spi0_clk),
 570         CLK("spi_davinci.1",    NULL,           &spi1_clk),
 571         CLK("vpif",             NULL,           &vpif_clk),
 572         CLK("ahci_da850",       "fck",          &sata_clk),
 573         CLK("davinci-rproc.0",  NULL,           &dsp_clk),
 574         CLK(NULL,               NULL,           &ehrpwm_clk),
 575         CLK("ehrpwm.0",         "fck",          &ehrpwm0_clk),
 576         CLK("ehrpwm.1",         "fck",          &ehrpwm1_clk),
 577         CLK(NULL,               NULL,           &ehrpwm_tbclk),
 578         CLK("ehrpwm.0",         "tbclk",        &ehrpwm0_tbclk),
 579         CLK("ehrpwm.1",         "tbclk",        &ehrpwm1_tbclk),
 580         CLK(NULL,               NULL,           &ecap_clk),
 581         CLK("ecap.0",           "fck",          &ecap0_clk),
 582         CLK("ecap.1",           "fck",          &ecap1_clk),
 583         CLK("ecap.2",           "fck",          &ecap2_clk),
 584         CLK(NULL,               NULL,           NULL),
 585 };
 586
 587 /*
 588  * Device specific mux setup
 589  *
 590  *              soc     description     mux     mode    mode    mux     dbg
 591  *                                      reg     offset  mask    mode
 592  */
 593 static const struct mux_config da850_pins[] = {
 594 #ifdef CONFIG_DAVINCI_MUX
 595         /* UART0 function */
 596         MUX_CFG(DA850, NUART0_CTS,      3,      24,     15,     2,      false)
 597         MUX_CFG(DA850, NUART0_RTS,      3,      28,     15,     2,      false)
 598         MUX_CFG(DA850, UART0_RXD,       3,      16,     15,     2,      false)
 599         MUX_CFG(DA850, UART0_TXD,       3,      20,     15,     2,      false)
 600         /* UART1 function */
 601         MUX_CFG(DA850, UART1_RXD,       4,      24,     15,     2,      false)
 602         MUX_CFG(DA850, UART1_TXD,       4,      28,     15,     2,      false)
 603         /* UART2 function */
 604         MUX_CFG(DA850, UART2_RXD,       4,      16,     15,     2,      false)
 605         MUX_CFG(DA850, UART2_TXD,       4,      20,     15,     2,      false)
 606         /* I2C1 function */
 607         MUX_CFG(DA850, I2C1_SCL,        4,      16,     15,     4,      false)
 608         MUX_CFG(DA850, I2C1_SDA,        4,      20,     15,     4,      false)
 609         /* I2C0 function */
 610         MUX_CFG(DA850, I2C0_SDA,        4,      12,     15,     2,      false)
 611         MUX_CFG(DA850, I2C0_SCL,        4,      8,      15,     2,      false)
 612         /* EMAC function */
 613         MUX_CFG(DA850, MII_TXEN,        2,      4,      15,     8,      false)
 614         MUX_CFG(DA850, MII_TXCLK,       2,      8,      15,     8,      false)
 615         MUX_CFG(DA850, MII_COL,         2,      12,     15,     8,      false)
 616         MUX_CFG(DA850, MII_TXD_3,       2,      16,     15,     8,      false)
 617         MUX_CFG(DA850, MII_TXD_2,       2,      20,     15,     8,      false)
 618         MUX_CFG(DA850, MII_TXD_1,       2,      24,     15,     8,      false)
 619         MUX_CFG(DA850, MII_TXD_0,       2,      28,     15,     8,      false)
 620         MUX_CFG(DA850, MII_RXCLK,       3,      0,      15,     8,      false)
 621         MUX_CFG(DA850, MII_RXDV,        3,      4,      15,     8,      false)
 622         MUX_CFG(DA850, MII_RXER,        3,      8,      15,     8,      false)
 623         MUX_CFG(DA850, MII_CRS,         3,      12,     15,     8,      false)
 624         MUX_CFG(DA850, MII_RXD_3,       3,      16,     15,     8,      false)
 625         MUX_CFG(DA850, MII_RXD_2,       3,      20,     15,     8,      false)
 626         MUX_CFG(DA850, MII_RXD_1,       3,      24,     15,     8,      false)
 627         MUX_CFG(DA850, MII_RXD_0,       3,      28,     15,     8,      false)
 628         MUX_CFG(DA850, MDIO_CLK,        4,      0,      15,     8,      false)
 629         MUX_CFG(DA850, MDIO_D,          4,      4,      15,     8,      false)
 630         MUX_CFG(DA850, RMII_TXD_0,      14,     12,     15,     8,      false)
 631         MUX_CFG(DA850, RMII_TXD_1,      14,     8,      15,     8,      false)
 632         MUX_CFG(DA850, RMII_TXEN,       14,     16,     15,     8,      false)
 633         MUX_CFG(DA850, RMII_CRS_DV,     15,     4,      15,     8,      false)
 634         MUX_CFG(DA850, RMII_RXD_0,      14,     24,     15,     8,      false)
 635         MUX_CFG(DA850, RMII_RXD_1,      14,     20,     15,     8,      false)
 636         MUX_CFG(DA850, RMII_RXER,       14,     28,     15,     8,      false)
 637         MUX_CFG(DA850, RMII_MHZ_50_CLK, 15,     0,      15,     0,      false)
 638         /* McASP function */
 639         MUX_CFG(DA850,  ACLKR,          0,      0,      15,     1,      false)
 640         MUX_CFG(DA850,  ACLKX,          0,      4,      15,     1,      false)
 641         MUX_CFG(DA850,  AFSR,           0,      8,      15,     1,      false)
 642         MUX_CFG(DA850,  AFSX,           0,      12,     15,     1,      false)
 643         MUX_CFG(DA850,  AHCLKR,         0,      16,     15,     1,      false)
 644         MUX_CFG(DA850,  AHCLKX,         0,      20,     15,     1,      false)
 645         MUX_CFG(DA850,  AMUTE,          0,      24,     15,     1,      false)
 646         MUX_CFG(DA850,  AXR_15,         1,      0,      15,     1,      false)
 647         MUX_CFG(DA850,  AXR_14,         1,      4,      15,     1,      false)
 648         MUX_CFG(DA850,  AXR_13,         1,      8,      15,     1,      false)
 649         MUX_CFG(DA850,  AXR_12,         1,      12,     15,     1,      false)
 650         MUX_CFG(DA850,  AXR_11,         1,      16,     15,     1,      false)
 651         MUX_CFG(DA850,  AXR_10,         1,      20,     15,     1,      false)
 652         MUX_CFG(DA850,  AXR_9,          1,      24,     15,     1,      false)
 653         MUX_CFG(DA850,  AXR_8,          1,      28,     15,     1,      false)
 654         MUX_CFG(DA850,  AXR_7,          2,      0,      15,     1,      false)
 655         MUX_CFG(DA850,  AXR_6,          2,      4,      15,     1,      false)
 656         MUX_CFG(DA850,  AXR_5,          2,      8,      15,     1,      false)
 657         MUX_CFG(DA850,  AXR_4,          2,      12,     15,     1,      false)
 658         MUX_CFG(DA850,  AXR_3,          2,      16,     15,     1,      false)
 659         MUX_CFG(DA850,  AXR_2,          2,      20,     15,     1,      false)
 660         MUX_CFG(DA850,  AXR_1,          2,      24,     15,     1,      false)
 661         MUX_CFG(DA850,  AXR_0,          2,      28,     15,     1,      false)
 662         /* LCD function */
 663         MUX_CFG(DA850, LCD_D_7,         16,     8,      15,     2,      false)
 664         MUX_CFG(DA850, LCD_D_6,         16,     12,     15,     2,      false)
 665         MUX_CFG(DA850, LCD_D_5,         16,     16,     15,     2,      false)
 666         MUX_CFG(DA850, LCD_D_4,         16,     20,     15,     2,      false)
 667         MUX_CFG(DA850, LCD_D_3,         16,     24,     15,     2,      false)
 668         MUX_CFG(DA850, LCD_D_2,         16,     28,     15,     2,      false)
 669         MUX_CFG(DA850, LCD_D_1,         17,     0,      15,     2,      false)
 670         MUX_CFG(DA850, LCD_D_0,         17,     4,      15,     2,      false)
 671         MUX_CFG(DA850, LCD_D_15,        17,     8,      15,     2,      false)
 672         MUX_CFG(DA850, LCD_D_14,        17,     12,     15,     2,      false)
 673         MUX_CFG(DA850, LCD_D_13,        17,     16,     15,     2,      false)
 674         MUX_CFG(DA850, LCD_D_12,        17,     20,     15,     2,      false)
 675         MUX_CFG(DA850, LCD_D_11,        17,     24,     15,     2,      false)
 676         MUX_CFG(DA850, LCD_D_10,        17,     28,     15,     2,      false)
 677         MUX_CFG(DA850, LCD_D_9,         18,     0,      15,     2,      false)
 678         MUX_CFG(DA850, LCD_D_8,         18,     4,      15,     2,      false)
 679         MUX_CFG(DA850, LCD_PCLK,        18,     24,     15,     2,      false)
 680         MUX_CFG(DA850, LCD_HSYNC,       19,     0,      15,     2,      false)
 681         MUX_CFG(DA850, LCD_VSYNC,       19,     4,      15,     2,      false)
 682         MUX_CFG(DA850, NLCD_AC_ENB_CS,  19,     24,     15,     2,      false)
 683         /* MMC/SD0 function */
 684         MUX_CFG(DA850, MMCSD0_DAT_0,    10,     8,      15,     2,      false)
 685         MUX_CFG(DA850, MMCSD0_DAT_1,    10,     12,     15,     2,      false)
 686         MUX_CFG(DA850, MMCSD0_DAT_2,    10,     16,     15,     2,      false)
 687         MUX_CFG(DA850, MMCSD0_DAT_3,    10,     20,     15,     2,      false)
 688         MUX_CFG(DA850, MMCSD0_CLK,      10,     0,      15,     2,      false)
 689         MUX_CFG(DA850, MMCSD0_CMD,      10,     4,      15,     2,      false)
 690         /* MMC/SD1 function */
 691         MUX_CFG(DA850, MMCSD1_DAT_0,    18,     8,      15,     2,      false)
 692         MUX_CFG(DA850, MMCSD1_DAT_1,    19,     16,     15,     2,      false)
 693         MUX_CFG(DA850, MMCSD1_DAT_2,    19,     12,     15,     2,      false)
 694         MUX_CFG(DA850, MMCSD1_DAT_3,    19,     8,      15,     2,      false)
 695         MUX_CFG(DA850, MMCSD1_CLK,      18,     12,     15,     2,      false)
 696         MUX_CFG(DA850, MMCSD1_CMD,      18,     16,     15,     2,      false)
 697         /* EMIF2.5/EMIFA function */
 698         MUX_CFG(DA850, EMA_D_7,         9,      0,      15,     1,      false)
 699         MUX_CFG(DA850, EMA_D_6,         9,      4,      15,     1,      false)
 700         MUX_CFG(DA850, EMA_D_5,         9,      8,      15,     1,      false)
 701         MUX_CFG(DA850, EMA_D_4,         9,      12,     15,     1,      false)
 702         MUX_CFG(DA850, EMA_D_3,         9,      16,     15,     1,      false)
 703         MUX_CFG(DA850, EMA_D_2,         9,      20,     15,     1,      false)
 704         MUX_CFG(DA850, EMA_D_1,         9,      24,     15,     1,      false)
 705         MUX_CFG(DA850, EMA_D_0,         9,      28,     15,     1,      false)
 706         MUX_CFG(DA850, EMA_A_1,         12,     24,     15,     1,      false)
 707         MUX_CFG(DA850, EMA_A_2,         12,     20,     15,     1,      false)
 708         MUX_CFG(DA850, NEMA_CS_3,       7,      4,      15,     1,      false)
 709         MUX_CFG(DA850, NEMA_CS_4,       7,      8,      15,     1,      false)
 710         MUX_CFG(DA850, NEMA_WE,         7,      16,     15,     1,      false)
 711         MUX_CFG(DA850, NEMA_OE,         7,      20,     15,     1,      false)
 712         MUX_CFG(DA850, EMA_A_0,         12,     28,     15,     1,      false)
 713         MUX_CFG(DA850, EMA_A_3,         12,     16,     15,     1,      false)
 714         MUX_CFG(DA850, EMA_A_4,         12,     12,     15,     1,      false)
 715         MUX_CFG(DA850, EMA_A_5,         12,     8,      15,     1,      false)
 716         MUX_CFG(DA850, EMA_A_6,         12,     4,      15,     1,      false)
 717         MUX_CFG(DA850, EMA_A_7,         12,     0,      15,     1,      false)
 718         MUX_CFG(DA850, EMA_A_8,         11,     28,     15,     1,      false)
 719         MUX_CFG(DA850, EMA_A_9,         11,     24,     15,     1,      false)
 720         MUX_CFG(DA850, EMA_A_10,        11,     20,     15,     1,      false)
 721         MUX_CFG(DA850, EMA_A_11,        11,     16,     15,     1,      false)
 722         MUX_CFG(DA850, EMA_A_12,        11,     12,     15,     1,      false)
 723         MUX_CFG(DA850, EMA_A_13,        11,     8,      15,     1,      false)
 724         MUX_CFG(DA850, EMA_A_14,        11,     4,      15,     1,      false)
 725         MUX_CFG(DA850, EMA_A_15,        11,     0,      15,     1,      false)
 726         MUX_CFG(DA850, EMA_A_16,        10,     28,     15,     1,      false)
 727         MUX_CFG(DA850, EMA_A_17,        10,     24,     15,     1,      false)
 728         MUX_CFG(DA850, EMA_A_18,        10,     20,     15,     1,      false)
 729         MUX_CFG(DA850, EMA_A_19,        10,     16,     15,     1,      false)
 730         MUX_CFG(DA850, EMA_A_20,        10,     12,     15,     1,      false)
 731         MUX_CFG(DA850, EMA_A_21,        10,     8,      15,     1,      false)
 732         MUX_CFG(DA850, EMA_A_22,        10,     4,      15,     1,      false)
 733         MUX_CFG(DA850, EMA_A_23,        10,     0,      15,     1,      false)
 734         MUX_CFG(DA850, EMA_D_8,         8,      28,     15,     1,      false)
 735         MUX_CFG(DA850, EMA_D_9,         8,      24,     15,     1,      false)
 736         MUX_CFG(DA850, EMA_D_10,        8,      20,     15,     1,      false)
 737         MUX_CFG(DA850, EMA_D_11,        8,      16,     15,     1,      false)
 738         MUX_CFG(DA850, EMA_D_12,        8,      12,     15,     1,      false)
 739         MUX_CFG(DA850, EMA_D_13,        8,      8,      15,     1,      false)
 740         MUX_CFG(DA850, EMA_D_14,        8,      4,      15,     1,      false)
 741         MUX_CFG(DA850, EMA_D_15,        8,      0,      15,     1,      false)
 742         MUX_CFG(DA850, EMA_BA_1,        5,      24,     15,     1,      false)
 743         MUX_CFG(DA850, EMA_CLK,         6,      0,      15,     1,      false)
 744         MUX_CFG(DA850, EMA_WAIT_1,      6,      24,     15,     1,      false)
 745         MUX_CFG(DA850, NEMA_CS_2,       7,      0,      15,     1,      false)
 746         /* GPIO function */
 747         MUX_CFG(DA850, GPIO2_4,         6,      12,     15,     8,      false)
 748         MUX_CFG(DA850, GPIO2_6,         6,      4,      15,     8,      false)
 749         MUX_CFG(DA850, GPIO2_8,         5,      28,     15,     8,      false)
 750         MUX_CFG(DA850, GPIO2_15,        5,      0,      15,     8,      false)
 751         MUX_CFG(DA850, GPIO3_12,        7,      12,     15,     8,      false)
 752         MUX_CFG(DA850, GPIO3_13,        7,      8,      15,     8,      false)
 753         MUX_CFG(DA850, GPIO4_0,         10,     28,     15,     8,      false)
 754         MUX_CFG(DA850, GPIO4_1,         10,     24,     15,     8,      false)
 755         MUX_CFG(DA850, GPIO6_9,         13,     24,     15,     8,      false)
 756         MUX_CFG(DA850, GPIO6_10,        13,     20,     15,     8,      false)
 757         MUX_CFG(DA850, GPIO6_13,        13,     8,      15,     8,      false)
 758         MUX_CFG(DA850, RTC_ALARM,       0,      28,     15,     2,      false)
 759         /* VPIF Capture */
 760         MUX_CFG(DA850, VPIF_DIN0,       15,     4,      15,     1,      false)
 761         MUX_CFG(DA850, VPIF_DIN1,       15,     0,      15,     1,      false)
 762         MUX_CFG(DA850, VPIF_DIN2,       14,     28,     15,     1,      false)
 763         MUX_CFG(DA850, VPIF_DIN3,       14,     24,     15,     1,      false)
 764         MUX_CFG(DA850, VPIF_DIN4,       14,     20,     15,     1,      false)
 765         MUX_CFG(DA850, VPIF_DIN5,       14,     16,     15,     1,      false)
 766         MUX_CFG(DA850, VPIF_DIN6,       14,     12,     15,     1,      false)
 767         MUX_CFG(DA850, VPIF_DIN7,       14,     8,      15,     1,      false)
 768         MUX_CFG(DA850, VPIF_DIN8,       16,     4,      15,     1,      false)
 769         MUX_CFG(DA850, VPIF_DIN9,       16,     0,      15,     1,      false)
 770         MUX_CFG(DA850, VPIF_DIN10,      15,     28,     15,     1,      false)
 771         MUX_CFG(DA850, VPIF_DIN11,      15,     24,     15,     1,      false)
 772         MUX_CFG(DA850, VPIF_DIN12,      15,     20,     15,     1,      false)
 773         MUX_CFG(DA850, VPIF_DIN13,      15,     16,     15,     1,      false)
 774         MUX_CFG(DA850, VPIF_DIN14,      15,     12,     15,     1,      false)
 775         MUX_CFG(DA850, VPIF_DIN15,      15,     8,      15,     1,      false)
 776         MUX_CFG(DA850, VPIF_CLKIN0,     14,     0,      15,     1,      false)
 777         MUX_CFG(DA850, VPIF_CLKIN1,     14,     4,      15,     1,      false)
 778         MUX_CFG(DA850, VPIF_CLKIN2,     19,     8,      15,     1,      false)
 779         MUX_CFG(DA850, VPIF_CLKIN3,     19,     16,     15,     1,      false)
 780         /* VPIF Display */
 781         MUX_CFG(DA850, VPIF_DOUT0,      17,     4,      15,     1,      false)
 782         MUX_CFG(DA850, VPIF_DOUT1,      17,     0,      15,     1,      false)
 783         MUX_CFG(DA850, VPIF_DOUT2,      16,     28,     15,     1,      false)
 784         MUX_CFG(DA850, VPIF_DOUT3,      16,     24,     15,     1,      false)
 785         MUX_CFG(DA850, VPIF_DOUT4,      16,     20,     15,     1,      false)
 786         MUX_CFG(DA850, VPIF_DOUT5,      16,     16,     15,     1,      false)
 787         MUX_CFG(DA850, VPIF_DOUT6,      16,     12,     15,     1,      false)
 788         MUX_CFG(DA850, VPIF_DOUT7,      16,     8,      15,     1,      false)
 789         MUX_CFG(DA850, VPIF_DOUT8,      18,     4,      15,     1,      false)
 790         MUX_CFG(DA850, VPIF_DOUT9,      18,     0,      15,     1,      false)
 791         MUX_CFG(DA850, VPIF_DOUT10,     17,     28,     15,     1,      false)
 792         MUX_CFG(DA850, VPIF_DOUT11,     17,     24,     15,     1,      false)
 793         MUX_CFG(DA850, VPIF_DOUT12,     17,     20,     15,     1,      false)
 794         MUX_CFG(DA850, VPIF_DOUT13,     17,     16,     15,     1,      false)
 795         MUX_CFG(DA850, VPIF_DOUT14,     17,     12,     15,     1,      false)
 796         MUX_CFG(DA850, VPIF_DOUT15,     17,     8,      15,     1,      false)
 797         MUX_CFG(DA850, VPIF_CLKO2,      19,     12,     15,     1,      false)
 798         MUX_CFG(DA850, VPIF_CLKO3,      19,     20,     15,     1,      false)
 799 #endif
 800 };
 801
 802 const short da850_i2c0_pins[] __initconst = {
 803         DA850_I2C0_SDA, DA850_I2C0_SCL,
 804         -1
 805 };
 806
 807 const short da850_i2c1_pins[] __initconst = {
 808         DA850_I2C1_SCL, DA850_I2C1_SDA,
 809         -1
 810 };
 811
 812 const short da850_lcdcntl_pins[] __initconst = {
 813         DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
 814         DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
 815         DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
 816         DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
 817         DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
 818         -1
 819 };
 820
 821 const short da850_vpif_capture_pins[] __initconst = {
 822         DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3,
 823         DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7,
 824         DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11,
 825         DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15,
 826         DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2,
 827         DA850_VPIF_CLKIN3,
 828         -1
 829 };
 830
 831 const short da850_vpif_display_pins[] __initconst = {
 832         DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3,
 833         DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7,
 834         DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10,
 835         DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13,
 836         DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2,
 837         DA850_VPIF_CLKO3,
 838         -1
 839 };
 840
 841 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 842 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
 843         [IRQ_DA8XX_COMMTX]              = 7,
 844         [IRQ_DA8XX_COMMRX]              = 7,
 845         [IRQ_DA8XX_NINT]                = 7,
 846         [IRQ_DA8XX_EVTOUT0]             = 7,
 847         [IRQ_DA8XX_EVTOUT1]             = 7,
 848         [IRQ_DA8XX_EVTOUT2]             = 7,
 849         [IRQ_DA8XX_EVTOUT3]             = 7,
 850         [IRQ_DA8XX_EVTOUT4]             = 7,
 851         [IRQ_DA8XX_EVTOUT5]             = 7,
 852         [IRQ_DA8XX_EVTOUT6]             = 7,
 853         [IRQ_DA8XX_EVTOUT7]             = 7,
 854         [IRQ_DA8XX_CCINT0]              = 7,
 855         [IRQ_DA8XX_CCERRINT]            = 7,
 856         [IRQ_DA8XX_TCERRINT0]           = 7,
 857         [IRQ_DA8XX_AEMIFINT]            = 7,
 858         [IRQ_DA8XX_I2CINT0]             = 7,
 859         [IRQ_DA8XX_MMCSDINT0]           = 7,
 860         [IRQ_DA8XX_MMCSDINT1]           = 7,
 861         [IRQ_DA8XX_ALLINT0]             = 7,
 862         [IRQ_DA8XX_RTC]                 = 7,
 863         [IRQ_DA8XX_SPINT0]              = 7,
 864         [IRQ_DA8XX_TINT12_0]            = 7,
 865         [IRQ_DA8XX_TINT34_0]            = 7,
 866         [IRQ_DA8XX_TINT12_1]            = 7,
 867         [IRQ_DA8XX_TINT34_1]            = 7,
 868         [IRQ_DA8XX_UARTINT0]            = 7,
 869         [IRQ_DA8XX_KEYMGRINT]           = 7,
 870         [IRQ_DA850_MPUADDRERR0]         = 7,
 871         [IRQ_DA8XX_CHIPINT0]            = 7,
 872         [IRQ_DA8XX_CHIPINT1]            = 7,
 873         [IRQ_DA8XX_CHIPINT2]            = 7,
 874         [IRQ_DA8XX_CHIPINT3]            = 7,
 875         [IRQ_DA8XX_TCERRINT1]           = 7,
 876         [IRQ_DA8XX_C0_RX_THRESH_PULSE]  = 7,
 877         [IRQ_DA8XX_C0_RX_PULSE]         = 7,
 878         [IRQ_DA8XX_C0_TX_PULSE]         = 7,
 879         [IRQ_DA8XX_C0_MISC_PULSE]       = 7,
 880         [IRQ_DA8XX_C1_RX_THRESH_PULSE]  = 7,
 881         [IRQ_DA8XX_C1_RX_PULSE]         = 7,
 882         [IRQ_DA8XX_C1_TX_PULSE]         = 7,
 883         [IRQ_DA8XX_C1_MISC_PULSE]       = 7,
 884         [IRQ_DA8XX_MEMERR]              = 7,
 885         [IRQ_DA8XX_GPIO0]               = 7,
 886         [IRQ_DA8XX_GPIO1]               = 7,
 887         [IRQ_DA8XX_GPIO2]               = 7,
 888         [IRQ_DA8XX_GPIO3]               = 7,
 889         [IRQ_DA8XX_GPIO4]               = 7,
 890         [IRQ_DA8XX_GPIO5]               = 7,
 891         [IRQ_DA8XX_GPIO6]               = 7,
 892         [IRQ_DA8XX_GPIO7]               = 7,
 893         [IRQ_DA8XX_GPIO8]               = 7,
 894         [IRQ_DA8XX_I2CINT1]             = 7,
 895         [IRQ_DA8XX_LCDINT]              = 7,
 896         [IRQ_DA8XX_UARTINT1]            = 7,
 897         [IRQ_DA8XX_MCASPINT]            = 7,
 898         [IRQ_DA8XX_ALLINT1]             = 7,
 899         [IRQ_DA8XX_SPINT1]              = 7,
 900         [IRQ_DA8XX_UHPI_INT1]           = 7,
 901         [IRQ_DA8XX_USB_INT]             = 7,
 902         [IRQ_DA8XX_IRQN]                = 7,
 903         [IRQ_DA8XX_RWAKEUP]             = 7,
 904         [IRQ_DA8XX_UARTINT2]            = 7,
 905         [IRQ_DA8XX_DFTSSINT]            = 7,
 906         [IRQ_DA8XX_EHRPWM0]             = 7,
 907         [IRQ_DA8XX_EHRPWM0TZ]           = 7,
 908         [IRQ_DA8XX_EHRPWM1]             = 7,
 909         [IRQ_DA8XX_EHRPWM1TZ]           = 7,
 910         [IRQ_DA850_SATAINT]             = 7,
 911         [IRQ_DA850_TINTALL_2]           = 7,
 912         [IRQ_DA8XX_ECAP0]               = 7,
 913         [IRQ_DA8XX_ECAP1]               = 7,
 914         [IRQ_DA8XX_ECAP2]               = 7,
 915         [IRQ_DA850_MMCSDINT0_1]         = 7,
 916         [IRQ_DA850_MMCSDINT1_1]         = 7,
 917         [IRQ_DA850_T12CMPINT0_2]        = 7,
 918         [IRQ_DA850_T12CMPINT1_2]        = 7,
 919         [IRQ_DA850_T12CMPINT2_2]        = 7,
 920         [IRQ_DA850_T12CMPINT3_2]        = 7,
 921         [IRQ_DA850_T12CMPINT4_2]        = 7,
 922         [IRQ_DA850_T12CMPINT5_2]        = 7,
 923         [IRQ_DA850_T12CMPINT6_2]        = 7,
 924         [IRQ_DA850_T12CMPINT7_2]        = 7,
 925         [IRQ_DA850_T12CMPINT0_3]        = 7,
 926         [IRQ_DA850_T12CMPINT1_3]        = 7,
 927         [IRQ_DA850_T12CMPINT2_3]        = 7,
 928         [IRQ_DA850_T12CMPINT3_3]        = 7,
 929         [IRQ_DA850_T12CMPINT4_3]        = 7,
 930         [IRQ_DA850_T12CMPINT5_3]        = 7,
 931         [IRQ_DA850_T12CMPINT6_3]        = 7,
 932         [IRQ_DA850_T12CMPINT7_3]        = 7,
 933         [IRQ_DA850_RPIINT]              = 7,
 934         [IRQ_DA850_VPIFINT]             = 7,
 935         [IRQ_DA850_CCINT1]              = 7,
 936         [IRQ_DA850_CCERRINT1]           = 7,
 937         [IRQ_DA850_TCERRINT2]           = 7,
 938         [IRQ_DA850_TINTALL_3]           = 7,
 939         [IRQ_DA850_MCBSP0RINT]          = 7,
 940         [IRQ_DA850_MCBSP0XINT]          = 7,
 941         [IRQ_DA850_MCBSP1RINT]          = 7,
 942         [IRQ_DA850_MCBSP1XINT]          = 7,
 943         [IRQ_DA8XX_ARMCLKSTOPREQ]       = 7,
 944 };
 945
 946 static struct map_desc da850_io_desc[] = {
 947         {
 948                 .virtual        = IO_VIRT,
 949                 .pfn            = __phys_to_pfn(IO_PHYS),
 950                 .length         = IO_SIZE,
 951                 .type           = MT_DEVICE
 952         },
 953         {
 954                 .virtual        = DA8XX_CP_INTC_VIRT,
 955                 .pfn            = __phys_to_pfn(DA8XX_CP_INTC_BASE),
 956                 .length         = DA8XX_CP_INTC_SIZE,
 957                 .type           = MT_DEVICE
 958         },
 959 };
 960
 961 static u32 da850_psc_bases[] = { DA8XX_PSC0_BASE, DA8XX_PSC1_BASE };
 962
 963 /* Contents of JTAG ID register used to identify exact cpu type */
 964 static struct davinci_id da850_ids[] = {
 965         {
 966                 .variant        = 0x0,
 967                 .part_no        = 0xb7d1,
 968                 .manufacturer   = 0x017,        /* 0x02f >> 1 */
 969                 .cpu_id         = DAVINCI_CPU_ID_DA850,
 970                 .name           = "da850/omap-l138",
 971         },
 972         {
 973                 .variant        = 0x1,
 974                 .part_no        = 0xb7d1,
 975                 .manufacturer   = 0x017,        /* 0x02f >> 1 */
 976                 .cpu_id         = DAVINCI_CPU_ID_DA850,
 977                 .name           = "da850/omap-l138/am18x",
 978         },
 979 };
 980
 981 static struct davinci_timer_instance da850_timer_instance[4] = {
 982         {
 983                 .base           = DA8XX_TIMER64P0_BASE,
 984                 .bottom_irq     = IRQ_DA8XX_TINT12_0,
 985                 .top_irq        = IRQ_DA8XX_TINT34_0,
 986         },
 987         {
 988                 .base           = DA8XX_TIMER64P1_BASE,
 989                 .bottom_irq     = IRQ_DA8XX_TINT12_1,
 990                 .top_irq        = IRQ_DA8XX_TINT34_1,
 991         },
 992         {
 993                 .base           = DA850_TIMER64P2_BASE,
 994                 .bottom_irq     = IRQ_DA850_TINT12_2,
 995                 .top_irq        = IRQ_DA850_TINT34_2,
 996         },
 997         {
 998                 .base           = DA850_TIMER64P3_BASE,
 999                 .bottom_irq     = IRQ_DA850_TINT12_3,
1000                 .top_irq        = IRQ_DA850_TINT34_3,
1001         },
1002 };
1003
1004 /*
1005  * T0_BOT: Timer 0, bottom              : Used for clock_event
1006  * T0_TOP: Timer 0, top                 : Used for clocksource
1007  * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
1008  */
1009 static struct davinci_timer_info da850_timer_info = {
1010         .timers         = da850_timer_instance,
1011         .clockevent_id  = T0_BOT,
1012         .clocksource_id = T0_TOP,
1013 };
1014
1015 #ifdef CONFIG_CPU_FREQ
1016 /*
1017  * Notes:
1018  * According to the TRM, minimum PLLM results in maximum power savings.
1019  * The OPP definitions below should keep the PLLM as low as possible.
1020  *
1021  * The output of the PLLM must be between 300 to 600 MHz.
1022  */
1023 struct da850_opp {
1024         unsigned int    freq;   /* in KHz */
1025         unsigned int    prediv;
1026         unsigned int    mult;
1027         unsigned int    postdiv;
1028         unsigned int    cvdd_min; /* in uV */
1029         unsigned int    cvdd_max; /* in uV */
1030 };
1031
1032 static const struct da850_opp da850_opp_456 = {
1033         .freq           = 456000,
1034         .prediv         = 1,
1035         .mult           = 19,
1036         .postdiv        = 1,
1037         .cvdd_min       = 1300000,
1038         .cvdd_max       = 1350000,
1039 };
1040
1041 static const struct da850_opp da850_opp_408 = {
1042         .freq           = 408000,
1043         .prediv         = 1,
1044         .mult           = 17,
1045         .postdiv        = 1,
1046         .cvdd_min       = 1300000,
1047         .cvdd_max       = 1350000,
1048 };
1049
1050 static const struct da850_opp da850_opp_372 = {
1051         .freq           = 372000,
1052         .prediv         = 2,
1053         .mult           = 31,
1054         .postdiv        = 1,
1055         .cvdd_min       = 1200000,
1056         .cvdd_max       = 1320000,
1057 };
1058
1059 static const struct da850_opp da850_opp_300 = {
1060         .freq           = 300000,
1061         .prediv         = 1,
1062         .mult           = 25,
1063         .postdiv        = 2,
1064         .cvdd_min       = 1200000,
1065         .cvdd_max       = 1320000,
1066 };
1067
1068 static const struct da850_opp da850_opp_200 = {
1069         .freq           = 200000,
1070         .prediv         = 1,
1071         .mult           = 25,
1072         .postdiv        = 3,
1073         .cvdd_min       = 1100000,
1074         .cvdd_max       = 1160000,
1075 };
1076
1077 static const struct da850_opp da850_opp_96 = {
1078         .freq           = 96000,
1079         .prediv         = 1,
1080         .mult           = 20,
1081         .postdiv        = 5,
1082         .cvdd_min       = 1000000,
1083         .cvdd_max       = 1050000,
1084 };
1085
1086 #define OPP(freq)               \
1087         {                               \
1088                 .driver_data = (unsigned int) &da850_opp_##freq,        \
1089                 .frequency = freq * 1000, \
1090         }
1091
1092 static struct cpufreq_frequency_table da850_freq_table[] = {
1093         OPP(456),
1094         OPP(408),
1095         OPP(372),
1096         OPP(300),
1097         OPP(200),
1098         OPP(96),
1099         {
1100                 .driver_data            = 0,
1101                 .frequency      = CPUFREQ_TABLE_END,
1102         },
1103 };
1104
1105 #ifdef CONFIG_REGULATOR
1106 static int da850_set_voltage(unsigned int index);
1107 static int da850_regulator_init(void);
1108 #endif
1109
1110 static struct davinci_cpufreq_config cpufreq_info = {
1111         .freq_table = da850_freq_table,
1112 #ifdef CONFIG_REGULATOR
1113         .init = da850_regulator_init,
1114         .set_voltage = da850_set_voltage,
1115 #endif
1116 };
1117
1118 #ifdef CONFIG_REGULATOR
1119 static struct regulator *cvdd;
1120
1121 static int da850_set_voltage(unsigned int index)
1122 {
1123         struct da850_opp *opp;
1124
1125         if (!cvdd)
1126                 return -ENODEV;
1127
1128         opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
1129
1130         return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
1131 }
1132
1133 static int da850_regulator_init(void)
1134 {
1135         cvdd = regulator_get(NULL, "cvdd");
1136         if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
1137                                         " voltage scaling unsupported\n")) {
1138                 return PTR_ERR(cvdd);
1139         }
1140
1141         return 0;
1142 }
1143 #endif
1144
1145 static struct platform_device da850_cpufreq_device = {
1146         .name                   = "cpufreq-davinci",
1147         .dev = {
1148                 .platform_data  = &cpufreq_info,
1149         },
1150         .id = -1,
1151 };
1152
1153 unsigned int da850_max_speed = 300000;
1154
1155 int da850_register_cpufreq(char *async_clk)
1156 {
1157         int i;
1158
1159         /* cpufreq driver can help keep an "async" clock constant */
1160         if (async_clk)
1161                 clk_add_alias("async", da850_cpufreq_device.name,
1162                                                         async_clk, NULL);
1163         for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
1164                 if (da850_freq_table[i].frequency <= da850_max_speed) {
1165                         cpufreq_info.freq_table = &da850_freq_table[i];
1166                         break;
1167                 }
1168         }
1169
1170         return platform_device_register(&da850_cpufreq_device);
1171 }
1172
1173 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1174 {
1175         int ret = 0, diff;
1176         unsigned int best = (unsigned int) -1;
1177         struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
1178         struct cpufreq_frequency_table *pos;
1179
1180         rate /= 1000; /* convert to kHz */
1181
1182         cpufreq_for_each_entry(pos, table) {
1183                 diff = pos->frequency - rate;
1184                 if (diff < 0)
1185                         diff = -diff;
1186
1187                 if (diff < best) {
1188                         best = diff;
1189                         ret = pos->frequency;
1190                 }
1191         }
1192
1193         return ret * 1000;
1194 }
1195
1196 static int da850_set_armrate(struct clk *clk, unsigned long index)
1197 {
1198         struct clk *pllclk = &pll0_clk;
1199
1200         return clk_set_rate(pllclk, index);
1201 }
1202
1203 static int da850_set_pll0rate(struct clk *clk, unsigned long rate)
1204 {
1205         struct pll_data *pll = clk->pll_data;
1206         struct cpufreq_frequency_table *freq;
1207         unsigned int prediv, mult, postdiv;
1208         struct da850_opp *opp = NULL;
1209         int ret;
1210
1211         rate /= 1000;
1212
1213         for (freq = da850_freq_table;
1214              freq->frequency != CPUFREQ_TABLE_END; freq++) {
1215                 /* rate is in Hz, freq->frequency is in KHz */
1216                 if (freq->frequency == rate) {
1217                         opp = (struct da850_opp *)freq->driver_data;
1218                         break;
1219                 }
1220         }
1221
1222         if (!opp)
1223                 return -EINVAL;
1224
1225         prediv = opp->prediv;
1226         mult = opp->mult;
1227         postdiv = opp->postdiv;
1228
1229         ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1230         if (WARN_ON(ret))
1231                 return ret;
1232
1233         return 0;
1234 }
1235 #else
1236 int __init da850_register_cpufreq(char *async_clk)
1237 {
1238         return 0;
1239 }
1240
1241 static int da850_set_armrate(struct clk *clk, unsigned long rate)
1242 {
1243         return -EINVAL;
1244 }
1245
1246 static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1247 {
1248         return -EINVAL;
1249 }
1250
1251 static int da850_round_armrate(struct clk *clk, unsigned long rate)
1252 {
1253         return clk->rate;
1254 }
1255 #endif
1256
1257 /* VPIF resource, platform data */
1258 static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32);
1259
1260 static struct resource da850_vpif_resource[] = {
1261         {
1262                 .start = DA8XX_VPIF_BASE,
1263                 .end   = DA8XX_VPIF_BASE + 0xfff,
1264                 .flags = IORESOURCE_MEM,
1265         }
1266 };
1267
1268 static struct platform_device da850_vpif_dev = {
1269         .name           = "vpif",
1270         .id             = -1,
1271         .dev            = {
1272                 .dma_mask               = &da850_vpif_dma_mask,
1273                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1274         },
1275         .resource       = da850_vpif_resource,
1276         .num_resources  = ARRAY_SIZE(da850_vpif_resource),
1277 };
1278
1279 static struct resource da850_vpif_display_resource[] = {
1280         {
1281                 .start = IRQ_DA850_VPIFINT,
1282                 .end   = IRQ_DA850_VPIFINT,
1283                 .flags = IORESOURCE_IRQ,
1284         },
1285 };
1286
1287 static struct platform_device da850_vpif_display_dev = {
1288         .name           = "vpif_display",
1289         .id             = -1,
1290         .dev            = {
1291                 .dma_mask               = &da850_vpif_dma_mask,
1292                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1293         },
1294         .resource       = da850_vpif_display_resource,
1295         .num_resources  = ARRAY_SIZE(da850_vpif_display_resource),
1296 };
1297
1298 static struct resource da850_vpif_capture_resource[] = {
1299         {
1300                 .start = IRQ_DA850_VPIFINT,
1301                 .end   = IRQ_DA850_VPIFINT,
1302                 .flags = IORESOURCE_IRQ,
1303         },
1304         {
1305                 .start = IRQ_DA850_VPIFINT,
1306                 .end   = IRQ_DA850_VPIFINT,
1307                 .flags = IORESOURCE_IRQ,
1308         },
1309 };
1310
1311 static struct platform_device da850_vpif_capture_dev = {
1312         .name           = "vpif_capture",
1313         .id             = -1,
1314         .dev            = {
1315                 .dma_mask               = &da850_vpif_dma_mask,
1316                 .coherent_dma_mask      = DMA_BIT_MASK(32),
1317         },
1318         .resource       = da850_vpif_capture_resource,
1319         .num_resources  = ARRAY_SIZE(da850_vpif_capture_resource),
1320 };
1321
1322 int __init da850_register_vpif(void)
1323 {
1324         return platform_device_register(&da850_vpif_dev);
1325 }
1326
1327 int __init da850_register_vpif_display(struct vpif_display_config
1328                                                 *display_config)
1329 {
1330         da850_vpif_display_dev.dev.platform_data = display_config;
1331         return platform_device_register(&da850_vpif_display_dev);
1332 }
1333
1334 int __init da850_register_vpif_capture(struct vpif_capture_config
1335                                                         *capture_config)
1336 {
1337         da850_vpif_capture_dev.dev.platform_data = capture_config;
1338         return platform_device_register(&da850_vpif_capture_dev);
1339 }
1340
1341 static struct davinci_gpio_platform_data da850_gpio_platform_data = {
1342         .ngpio = 144,
1343 };
1344
1345 int __init da850_register_gpio(void)
1346 {
1347         return da8xx_register_gpio(&da850_gpio_platform_data);
1348 }
1349
1350 static struct davinci_soc_info davinci_soc_info_da850 = {
1351         .io_desc                = da850_io_desc,
1352         .io_desc_num            = ARRAY_SIZE(da850_io_desc),
1353         .jtag_id_reg            = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
1354         .ids                    = da850_ids,
1355         .ids_num                = ARRAY_SIZE(da850_ids),
1356         .cpu_clks               = da850_clks,
1357         .psc_bases              = da850_psc_bases,
1358         .psc_bases_num          = ARRAY_SIZE(da850_psc_bases),
1359         .pinmux_base            = DA8XX_SYSCFG0_BASE + 0x120,
1360         .pinmux_pins            = da850_pins,
1361         .pinmux_pins_num        = ARRAY_SIZE(da850_pins),
1362         .intc_base              = DA8XX_CP_INTC_BASE,
1363         .intc_type              = DAVINCI_INTC_TYPE_CP_INTC,
1364         .intc_irq_prios         = da850_default_priorities,
1365         .intc_irq_num           = DA850_N_CP_INTC_IRQ,
1366         .timer_info             = &da850_timer_info,
1367         .emac_pdata             = &da8xx_emac_pdata,
1368         .sram_dma               = DA8XX_SHARED_RAM_BASE,
1369         .sram_len               = SZ_128K,
1370 };
1371
1372 void __init da850_init(void)
1373 {
1374         unsigned int v;
1375
1376         davinci_common_init(&davinci_soc_info_da850);
1377
1378         da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1379         if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1380                 return;
1381
1382         da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1383         if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
1384                 return;
1385
1386         /* Unlock writing to PLL0 registers */
1387         v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1388         v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1389         __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1390
1391         /* Unlock writing to PLL1 registers */
1392         v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1393         v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1394         __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1395
1396         davinci_clk_init(davinci_soc_info_da850.cpu_clks);
1397 }