arch/arm/mach-davinci/board-mityomapl138.c

   1 /*
   2  * Critical Link MityOMAP-L138 SoM
   3  *
   4  * Copyright (C) 2010 Critical Link LLC - http://www.criticallink.com
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2. This program is licensed "as is" without any warranty of
   8  * any kind, whether express or implied.
   9  */
  10
  11 #define pr_fmt(fmt) "MityOMAPL138: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/console.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/property.h>
  18 #include <linux/mtd/partitions.h>
  19 #include <linux/notifier.h>
  20 #include <linux/nvmem-consumer.h>
  21 #include <linux/nvmem-provider.h>
  22 #include <linux/regulator/machine.h>
  23 #include <linux/i2c.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/spi/flash.h>
  27
  28 #include <asm/io.h>
  29 #include <asm/mach-types.h>
  30 #include <asm/mach/arch.h>
  31 #include <mach/common.h>
  32 #include <mach/da8xx.h>
  33 #include <linux/platform_data/mtd-davinci.h>
  34 #include <linux/platform_data/mtd-davinci-aemif.h>
  35 #include <linux/platform_data/ti-aemif.h>
  36 #include <mach/mux.h>
  37 #include <linux/platform_data/spi-davinci.h>
  38
  39 #define MITYOMAPL138_PHY_ID             ""
  40
  41 #define FACTORY_CONFIG_MAGIC    0x012C0138
  42 #define FACTORY_CONFIG_VERSION  0x00010001
  43
  44 /* Data Held in On-Board I2C device */
  45 struct factory_config {
  46         u32     magic;
  47         u32     version;
  48         u8      mac[6];
  49         u32     fpga_type;
  50         u32     spare;
  51         u32     serialnumber;
  52         char    partnum[32];
  53 };
  54
  55 static struct factory_config factory_config;
  56
  57 #ifdef CONFIG_CPU_FREQ
  58 struct part_no_info {
  59         const char      *part_no;       /* part number string of interest */
  60         int             max_freq;       /* khz */
  61 };
  62
  63 static struct part_no_info mityomapl138_pn_info[] = {
  64         {
  65                 .part_no        = "L138-C",
  66                 .max_freq       = 300000,
  67         },
  68         {
  69                 .part_no        = "L138-D",
  70                 .max_freq       = 375000,
  71         },
  72         {
  73                 .part_no        = "L138-F",
  74                 .max_freq       = 456000,
  75         },
  76         {
  77                 .part_no        = "1808-C",
  78                 .max_freq       = 300000,
  79         },
  80         {
  81                 .part_no        = "1808-D",
  82                 .max_freq       = 375000,
  83         },
  84         {
  85                 .part_no        = "1808-F",
  86                 .max_freq       = 456000,
  87         },
  88         {
  89                 .part_no        = "1810-D",
  90                 .max_freq       = 375000,
  91         },
  92 };
  93
  94 static void mityomapl138_cpufreq_init(const char *partnum)
  95 {
  96         int i, ret;
  97
  98         for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
  99                 /*
 100                  * the part number has additional characters beyond what is
 101                  * stored in the table.  This information is not needed for
 102                  * determining the speed grade, and would require several
 103                  * more table entries.  Only check the first N characters
 104                  * for a match.
 105                  */
 106                 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
 107                              strlen(mityomapl138_pn_info[i].part_no))) {
 108                         da850_max_speed = mityomapl138_pn_info[i].max_freq;
 109                         break;
 110                 }
 111         }
 112
 113         ret = da850_register_cpufreq("pll0_sysclk3");
 114         if (ret)
 115                 pr_warn("cpufreq registration failed: %d\n", ret);
 116 }
 117 #else
 118 static void mityomapl138_cpufreq_init(const char *partnum) { }
 119 #endif
 120
 121 static int read_factory_config(struct notifier_block *nb,
 122                                unsigned long event, void *data)
 123 {
 124         int ret;
 125         const char *partnum = NULL;
 126         struct nvmem_device *nvmem = data;
 127
 128         if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0)
 129                 return NOTIFY_DONE;
 130
 131         if (!IS_BUILTIN(CONFIG_NVMEM)) {
 132                 pr_warn("Factory Config not available without CONFIG_NVMEM\n");
 133                 goto bad_config;
 134         }
 135
 136         ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
 137                                 &factory_config);
 138         if (ret != sizeof(struct factory_config)) {
 139                 pr_warn("Read Factory Config Failed: %d\n", ret);
 140                 goto bad_config;
 141         }
 142
 143         if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
 144                 pr_warn("Factory Config Magic Wrong (%X)\n",
 145                         factory_config.magic);
 146                 goto bad_config;
 147         }
 148
 149         if (factory_config.version != FACTORY_CONFIG_VERSION) {
 150                 pr_warn("Factory Config Version Wrong (%X)\n",
 151                         factory_config.version);
 152                 goto bad_config;
 153         }
 154
 155         partnum = factory_config.partnum;
 156         pr_info("Part Number = %s\n", partnum);
 157
 158 bad_config:
 159         /* default maximum speed is valid for all platforms */
 160         mityomapl138_cpufreq_init(partnum);
 161
 162         return NOTIFY_STOP;
 163 }
 164
 165 static struct notifier_block mityomapl138_nvmem_notifier = {
 166         .notifier_call = read_factory_config,
 167 };
 168
 169 /*
 170  * We don't define a cell for factory config as it will be accessed from the
 171  * board file using the nvmem notifier chain.
 172  */
 173 static struct nvmem_cell_info mityomapl138_nvmem_cells[] = {
 174         {
 175                 .name           = "macaddr",
 176                 .offset         = 0x64,
 177                 .bytes          = ETH_ALEN,
 178         }
 179 };
 180
 181 static struct nvmem_cell_table mityomapl138_nvmem_cell_table = {
 182         .nvmem_name     = "1-00500",
 183         .cells          = mityomapl138_nvmem_cells,
 184         .ncells         = ARRAY_SIZE(mityomapl138_nvmem_cells),
 185 };
 186
 187 static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = {
 188         .nvmem_name     = "1-00500",
 189         .cell_name      = "macaddr",
 190         .dev_id         = "davinci_emac.1",
 191         .con_id         = "mac-address",
 192 };
 193
 194 static const struct property_entry mityomapl138_fd_chip_properties[] = {
 195         PROPERTY_ENTRY_U32("pagesize", 8),
 196         PROPERTY_ENTRY_BOOL("read-only"),
 197         { }
 198 };
 199
 200 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
 201         .bus_freq       = 100,  /* kHz */
 202         .bus_delay      = 0,    /* usec */
 203 };
 204
 205 /* TPS65023 voltage regulator support */
 206 /* 1.2V Core */
 207 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
 208         {
 209                 .supply = "cvdd",
 210         },
 211 };
 212
 213 /* 1.8V */
 214 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
 215         {
 216                 .supply = "usb0_vdda18",
 217         },
 218         {
 219                 .supply = "usb1_vdda18",
 220         },
 221         {
 222                 .supply = "ddr_dvdd18",
 223         },
 224         {
 225                 .supply = "sata_vddr",
 226         },
 227 };
 228
 229 /* 1.2V */
 230 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
 231         {
 232                 .supply = "sata_vdd",
 233         },
 234         {
 235                 .supply = "usb_cvdd",
 236         },
 237         {
 238                 .supply = "pll0_vdda",
 239         },
 240         {
 241                 .supply = "pll1_vdda",
 242         },
 243 };
 244
 245 /* 1.8V Aux LDO, not used */
 246 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
 247         {
 248                 .supply = "1.8v_aux",
 249         },
 250 };
 251
 252 /* FPGA VCC Aux (2.5 or 3.3) LDO */
 253 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
 254         {
 255                 .supply = "vccaux",
 256         },
 257 };
 258
 259 static struct regulator_init_data tps65023_regulator_data[] = {
 260         /* dcdc1 */
 261         {
 262                 .constraints = {
 263                         .min_uV = 1150000,
 264                         .max_uV = 1350000,
 265                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 266                                           REGULATOR_CHANGE_STATUS,
 267                         .boot_on = 1,
 268                 },
 269                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
 270                 .consumer_supplies = tps65023_dcdc1_consumers,
 271         },
 272         /* dcdc2 */
 273         {
 274                 .constraints = {
 275                         .min_uV = 1800000,
 276                         .max_uV = 1800000,
 277                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 278                         .boot_on = 1,
 279                 },
 280                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
 281                 .consumer_supplies = tps65023_dcdc2_consumers,
 282         },
 283         /* dcdc3 */
 284         {
 285                 .constraints = {
 286                         .min_uV = 1200000,
 287                         .max_uV = 1200000,
 288                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 289                         .boot_on = 1,
 290                 },
 291                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
 292                 .consumer_supplies = tps65023_dcdc3_consumers,
 293         },
 294         /* ldo1 */
 295         {
 296                 .constraints = {
 297                         .min_uV = 1800000,
 298                         .max_uV = 1800000,
 299                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 300                         .boot_on = 1,
 301                 },
 302                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
 303                 .consumer_supplies = tps65023_ldo1_consumers,
 304         },
 305         /* ldo2 */
 306         {
 307                 .constraints = {
 308                         .min_uV = 2500000,
 309                         .max_uV = 3300000,
 310                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 311                                           REGULATOR_CHANGE_STATUS,
 312                         .boot_on = 1,
 313                 },
 314                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
 315                 .consumer_supplies = tps65023_ldo2_consumers,
 316         },
 317 };
 318
 319 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
 320         {
 321                 I2C_BOARD_INFO("tps65023", 0x48),
 322                 .platform_data = &tps65023_regulator_data[0],
 323         },
 324         {
 325                 I2C_BOARD_INFO("24c02", 0x50),
 326                 .properties = mityomapl138_fd_chip_properties,
 327         },
 328 };
 329
 330 static int __init pmic_tps65023_init(void)
 331 {
 332         return i2c_register_board_info(1, mityomap_tps65023_info,
 333                                         ARRAY_SIZE(mityomap_tps65023_info));
 334 }
 335
 336 /*
 337  * SPI Devices:
 338  *      SPI1_CS0: 8M Flash ST-M25P64-VME6G
 339  */
 340 static struct mtd_partition spi_flash_partitions[] = {
 341         [0] = {
 342                 .name           = "ubl",
 343                 .offset         = 0,
 344                 .size           = SZ_64K,
 345                 .mask_flags     = MTD_WRITEABLE,
 346         },
 347         [1] = {
 348                 .name           = "u-boot",
 349                 .offset         = MTDPART_OFS_APPEND,
 350                 .size           = SZ_512K,
 351                 .mask_flags     = MTD_WRITEABLE,
 352         },
 353         [2] = {
 354                 .name           = "u-boot-env",
 355                 .offset         = MTDPART_OFS_APPEND,
 356                 .size           = SZ_64K,
 357                 .mask_flags     = MTD_WRITEABLE,
 358         },
 359         [3] = {
 360                 .name           = "periph-config",
 361                 .offset         = MTDPART_OFS_APPEND,
 362                 .size           = SZ_64K,
 363                 .mask_flags     = MTD_WRITEABLE,
 364         },
 365         [4] = {
 366                 .name           = "reserved",
 367                 .offset         = MTDPART_OFS_APPEND,
 368                 .size           = SZ_256K + SZ_64K,
 369         },
 370         [5] = {
 371                 .name           = "kernel",
 372                 .offset         = MTDPART_OFS_APPEND,
 373                 .size           = SZ_2M + SZ_1M,
 374         },
 375         [6] = {
 376                 .name           = "fpga",
 377                 .offset         = MTDPART_OFS_APPEND,
 378                 .size           = SZ_2M,
 379         },
 380         [7] = {
 381                 .name           = "spare",
 382                 .offset         = MTDPART_OFS_APPEND,
 383                 .size           = MTDPART_SIZ_FULL,
 384         },
 385 };
 386
 387 static struct flash_platform_data mityomapl138_spi_flash_data = {
 388         .name           = "m25p80",
 389         .parts          = spi_flash_partitions,
 390         .nr_parts       = ARRAY_SIZE(spi_flash_partitions),
 391         .type           = "m24p64",
 392 };
 393
 394 static struct davinci_spi_config spi_eprom_config = {
 395         .io_type        = SPI_IO_TYPE_DMA,
 396         .c2tdelay       = 8,
 397         .t2cdelay       = 8,
 398 };
 399
 400 static struct spi_board_info mityomapl138_spi_flash_info[] = {
 401         {
 402                 .modalias               = "m25p80",
 403                 .platform_data          = &mityomapl138_spi_flash_data,
 404                 .controller_data        = &spi_eprom_config,
 405                 .mode                   = SPI_MODE_0,
 406                 .max_speed_hz           = 30000000,
 407                 .bus_num                = 1,
 408                 .chip_select            = 0,
 409         },
 410 };
 411
 412 /*
 413  * MityDSP-L138 includes a 256 MByte large-page NAND flash
 414  * (128K blocks).
 415  */
 416 static struct mtd_partition mityomapl138_nandflash_partition[] = {
 417         {
 418                 .name           = "rootfs",
 419                 .offset         = 0,
 420                 .size           = SZ_128M,
 421                 .mask_flags     = 0, /* MTD_WRITEABLE, */
 422         },
 423         {
 424                 .name           = "homefs",
 425                 .offset         = MTDPART_OFS_APPEND,
 426                 .size           = MTDPART_SIZ_FULL,
 427                 .mask_flags     = 0,
 428         },
 429 };
 430
 431 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
 432         .core_chipsel   = 1,
 433         .parts          = mityomapl138_nandflash_partition,
 434         .nr_parts       = ARRAY_SIZE(mityomapl138_nandflash_partition),
 435         .ecc_mode       = NAND_ECC_HW,
 436         .bbt_options    = NAND_BBT_USE_FLASH,
 437         .options        = NAND_BUSWIDTH_16,
 438         .ecc_bits       = 1, /* 4 bit mode is not supported with 16 bit NAND */
 439 };
 440
 441 static struct resource mityomapl138_nandflash_resource[] = {
 442         {
 443                 .start  = DA8XX_AEMIF_CS3_BASE,
 444                 .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
 445                 .flags  = IORESOURCE_MEM,
 446         },
 447         {
 448                 .start  = DA8XX_AEMIF_CTL_BASE,
 449                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
 450                 .flags  = IORESOURCE_MEM,
 451         },
 452 };
 453
 454 static struct platform_device mityomapl138_aemif_devices[] = {
 455         {
 456                 .name           = "davinci_nand",
 457                 .id             = 1,
 458                 .dev            = {
 459                         .platform_data  = &mityomapl138_nandflash_data,
 460                 },
 461                 .num_resources  = ARRAY_SIZE(mityomapl138_nandflash_resource),
 462                 .resource       = mityomapl138_nandflash_resource,
 463         },
 464 };
 465
 466 static struct resource mityomapl138_aemif_resources[] = {
 467         {
 468                 .start  = DA8XX_AEMIF_CTL_BASE,
 469                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
 470                 .flags  = IORESOURCE_MEM,
 471         },
 472 };
 473
 474 static struct aemif_abus_data mityomapl138_aemif_abus_data[] = {
 475         {
 476                 .cs     = 1,
 477         },
 478 };
 479
 480 static struct aemif_platform_data mityomapl138_aemif_pdata = {
 481         .abus_data              = mityomapl138_aemif_abus_data,
 482         .num_abus_data          = ARRAY_SIZE(mityomapl138_aemif_abus_data),
 483         .sub_devices            = mityomapl138_aemif_devices,
 484         .num_sub_devices        = ARRAY_SIZE(mityomapl138_aemif_devices),
 485 };
 486
 487 static struct platform_device mityomapl138_aemif_device = {
 488         .name           = "ti-aemif",
 489         .id             = -1,
 490         .dev = {
 491                 .platform_data  = &mityomapl138_aemif_pdata,
 492         },
 493         .resource       = mityomapl138_aemif_resources,
 494         .num_resources  = ARRAY_SIZE(mityomapl138_aemif_resources),
 495 };
 496
 497 static void __init mityomapl138_setup_nand(void)
 498 {
 499         if (platform_device_register(&mityomapl138_aemif_device))
 500                 pr_warn("%s: Cannot register AEMIF device\n", __func__);
 501 }
 502
 503 static const short mityomap_mii_pins[] = {
 504         DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
 505         DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
 506         DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
 507         DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
 508         DA850_MDIO_D,
 509         -1
 510 };
 511
 512 static const short mityomap_rmii_pins[] = {
 513         DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
 514         DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
 515         DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
 516         DA850_MDIO_D,
 517         -1
 518 };
 519
 520 static void __init mityomapl138_config_emac(void)
 521 {
 522         void __iomem *cfg_chip3_base;
 523         int ret;
 524         u32 val;
 525         struct davinci_soc_info *soc_info = &davinci_soc_info;
 526
 527         soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
 528
 529         cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
 530         val = __raw_readl(cfg_chip3_base);
 531
 532         if (soc_info->emac_pdata->rmii_en) {
 533                 val |= BIT(8);
 534                 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
 535                 pr_info("RMII PHY configured\n");
 536         } else {
 537                 val &= ~BIT(8);
 538                 ret = davinci_cfg_reg_list(mityomap_mii_pins);
 539                 pr_info("MII PHY configured\n");
 540         }
 541
 542         if (ret) {
 543                 pr_warn("mii/rmii mux setup failed: %d\n", ret);
 544                 return;
 545         }
 546
 547         /* configure the CFGCHIP3 register for RMII or MII */
 548         __raw_writel(val, cfg_chip3_base);
 549
 550         soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
 551
 552         ret = da8xx_register_emac();
 553         if (ret)
 554                 pr_warn("emac registration failed: %d\n", ret);
 555 }
 556
 557 static void __init mityomapl138_init(void)
 558 {
 559         int ret;
 560
 561         da850_register_clocks();
 562
 563         /* for now, no special EDMA channels are reserved */
 564         ret = da850_register_edma(NULL);
 565         if (ret)
 566                 pr_warn("edma registration failed: %d\n", ret);
 567
 568         ret = da8xx_register_watchdog();
 569         if (ret)
 570                 pr_warn("watchdog registration failed: %d\n", ret);
 571
 572         davinci_serial_init(da8xx_serial_device);
 573
 574         nvmem_register_notifier(&mityomapl138_nvmem_notifier);
 575         nvmem_add_cell_table(&mityomapl138_nvmem_cell_table);
 576         nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1);
 577
 578         ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
 579         if (ret)
 580                 pr_warn("i2c0 registration failed: %d\n", ret);
 581
 582         ret = pmic_tps65023_init();
 583         if (ret)
 584                 pr_warn("TPS65023 PMIC init failed: %d\n", ret);
 585
 586         mityomapl138_setup_nand();
 587
 588         ret = spi_register_board_info(mityomapl138_spi_flash_info,
 589                                       ARRAY_SIZE(mityomapl138_spi_flash_info));
 590         if (ret)
 591                 pr_warn("spi info registration failed: %d\n", ret);
 592
 593         ret = da8xx_register_spi_bus(1,
 594                                      ARRAY_SIZE(mityomapl138_spi_flash_info));
 595         if (ret)
 596                 pr_warn("spi 1 registration failed: %d\n", ret);
 597
 598         mityomapl138_config_emac();
 599
 600         ret = da8xx_register_rtc();
 601         if (ret)
 602                 pr_warn("rtc setup failed: %d\n", ret);
 603
 604         ret = da8xx_register_cpuidle();
 605         if (ret)
 606                 pr_warn("cpuidle registration failed: %d\n", ret);
 607
 608         davinci_pm_init();
 609 }
 610
 611 #ifdef CONFIG_SERIAL_8250_CONSOLE
 612 static int __init mityomapl138_console_init(void)
 613 {
 614         if (!machine_is_mityomapl138())
 615                 return 0;
 616
 617         return add_preferred_console("ttyS", 1, "115200");
 618 }
 619 console_initcall(mityomapl138_console_init);
 620 #endif
 621
 622 static void __init mityomapl138_map_io(void)
 623 {
 624         da850_init();
 625 }
 626
 627 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
 628         .atag_offset    = 0x100,
 629         .map_io         = mityomapl138_map_io,
 630         .init_irq       = da850_init_irq,
 631         .init_time      = da850_init_time,
 632         .init_machine   = mityomapl138_init,
 633         .init_late      = davinci_init_late,
 634         .dma_zone_size  = SZ_128M,
 635 MACHINE_END