1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/include/asm/assembler.h
5 * Copyright (C) 1996-2000 Russell King
7 * This file contains arm architecture specific defines
8 * for the different processors.
10 * Do not include any C declarations in this file - it is included by
13 #ifndef __ASM_ASSEMBLER_H__
14 #define __ASM_ASSEMBLER_H__
17 #error "Only include this from assembly code"
20 #include <asm/ptrace.h>
21 #include <asm/opcodes-virt.h>
22 #include <asm/asm-offsets.h>
24 #include <asm/thread_info.h>
25 #include <asm/uaccess-asm.h>
30 * Endian independent macros for shifting bytes within registers.
35 #define get_byte_0 lsl #0
36 #define get_byte_1 lsr #8
37 #define get_byte_2 lsr #16
38 #define get_byte_3 lsr #24
39 #define put_byte_0 lsl #0
40 #define put_byte_1 lsl #8
41 #define put_byte_2 lsl #16
42 #define put_byte_3 lsl #24
46 #define get_byte_0 lsr #24
47 #define get_byte_1 lsr #16
48 #define get_byte_2 lsr #8
49 #define get_byte_3 lsl #0
50 #define put_byte_0 lsl #24
51 #define put_byte_1 lsl #16
52 #define put_byte_2 lsl #8
53 #define put_byte_3 lsl #0
56 /* Select code for any configuration running in BE8 mode */
57 #ifdef CONFIG_CPU_ENDIAN_BE8
58 #define ARM_BE8(code...) code
60 #define ARM_BE8(code...)
64 * Data preload for architectures that support it
66 #if __LINUX_ARM_ARCH__ >= 5
67 #define PLD(code...) code
73 * This can be used to enable code to cacheline align the destination
74 * pointer when bulk writing to memory. Experiments on StrongARM and
75 * XScale didn't show this a worthwhile thing to do when the cache is not
76 * set to write-allocate (this would need further testing on XScale when WA
79 * On Feroceon there is much to gain however, regardless of cache mode.
81 #ifdef CONFIG_CPU_FEROCEON
82 #define CALGN(code...) code
84 #define CALGN(code...)
87 #define IMM12_MASK 0xfff
90 * Enable and disable interrupts
92 #if __LINUX_ARM_ARCH__ >= 6
93 .macro disable_irq_notrace
97 .macro enable_irq_notrace
101 .macro disable_irq_notrace
102 msr cpsr_c, #PSR_I_BIT | SVC_MODE
105 .macro enable_irq_notrace
106 msr cpsr_c, #SVC_MODE
110 .macro asm_trace_hardirqs_off, save=1
111 #if defined(CONFIG_TRACE_IRQFLAGS)
113 stmdb sp!, {r0-r3, ip, lr}
115 bl trace_hardirqs_off
117 ldmia sp!, {r0-r3, ip, lr}
122 .macro asm_trace_hardirqs_on, cond=al, save=1
123 #if defined(CONFIG_TRACE_IRQFLAGS)
125 * actually the registers should be pushed and pop'd conditionally, but
126 * after bl the flags are certainly clobbered
129 stmdb sp!, {r0-r3, ip, lr}
131 bl\cond trace_hardirqs_on
133 ldmia sp!, {r0-r3, ip, lr}
138 .macro disable_irq, save=1
140 asm_trace_hardirqs_off \save
144 asm_trace_hardirqs_on
148 * Save the current IRQ state and disable IRQs. Note that this macro
149 * assumes FIQs are enabled, and that the processor is in SVC mode.
151 .macro save_and_disable_irqs, oldcpsr
152 #ifdef CONFIG_CPU_V7M
153 mrs \oldcpsr, primask
160 .macro save_and_disable_irqs_notrace, oldcpsr
161 #ifdef CONFIG_CPU_V7M
162 mrs \oldcpsr, primask
170 * Restore interrupt state previously stored in a register. We don't
171 * guarantee that this will preserve the flags.
173 .macro restore_irqs_notrace, oldcpsr
174 #ifdef CONFIG_CPU_V7M
175 msr primask, \oldcpsr
181 .macro restore_irqs, oldcpsr
182 tst \oldcpsr, #PSR_I_BIT
183 asm_trace_hardirqs_on cond=eq
184 restore_irqs_notrace \oldcpsr
188 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
189 * reference local symbols in the same assembly file which are to be
190 * resolved by the assembler. Other usage is undefined.
192 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
193 .macro badr\c, rd, sym
194 #ifdef CONFIG_THUMB2_KERNEL
203 * Get current thread_info.
205 .macro get_thread_info, rd
206 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT )
208 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT )
209 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
213 * Increment/decrement the preempt count.
215 #ifdef CONFIG_PREEMPT_COUNT
216 .macro inc_preempt_count, ti, tmp
217 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
218 add \tmp, \tmp, #1 @ increment it
219 str \tmp, [\ti, #TI_PREEMPT]
222 .macro dec_preempt_count, ti, tmp
223 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
224 sub \tmp, \tmp, #1 @ decrement it
225 str \tmp, [\ti, #TI_PREEMPT]
228 .macro dec_preempt_count_ti, ti, tmp
230 dec_preempt_count \ti, \tmp
233 .macro inc_preempt_count, ti, tmp
236 .macro dec_preempt_count, ti, tmp
239 .macro dec_preempt_count_ti, ti, tmp
243 #define USERL(l, x...) \
245 .pushsection __ex_table,"a"; \
250 #define USER(x...) USERL(9001f, x)
253 #define ALT_SMP(instr...) \
256 * Note: if you get assembler errors from ALT_UP() when building with
257 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
258 * ALT_SMP( W(instr) ... )
260 #define ALT_UP(instr...) \
261 .pushsection ".alt.smp.init", "a" ;\
264 .if . - 9997b == 2 ;\
267 .if . - 9997b != 4 ;\
268 .error "ALT_UP() content must assemble to exactly 4 bytes";\
271 #define ALT_UP_B(label) \
272 .equ up_b_offset, label - 9998b ;\
273 .pushsection ".alt.smp.init", "a" ;\
275 W(b) . + up_b_offset ;\
278 #define ALT_SMP(instr...)
279 #define ALT_UP(instr...) instr
280 #define ALT_UP_B(label) b label
284 * Instruction barrier
287 #if __LINUX_ARM_ARCH__ >= 7
289 #elif __LINUX_ARM_ARCH__ == 6
290 mcr p15, 0, r0, c7, c5, 4
295 * SMP data memory barrier
299 #if __LINUX_ARM_ARCH__ >= 7
305 #elif __LINUX_ARM_ARCH__ == 6
306 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
308 #error Incompatible SMP platform
318 #if defined(CONFIG_CPU_V7M)
320 * setmode is used to assert to be in svc mode during boot. For v7-M
321 * this is done in __v7m_setup, so setmode can be empty here.
323 .macro setmode, mode, reg
325 #elif defined(CONFIG_THUMB2_KERNEL)
326 .macro setmode, mode, reg
331 .macro setmode, mode, reg
337 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
338 * a scratch register for the macro to overwrite.
340 * This macro is intended for forcing the CPU into SVC mode at boot time.
341 * you cannot return to the original mode.
343 .macro safe_svcmode_maskall reg:req
344 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
346 eor \reg, \reg, #HYP_MODE
348 bic \reg , \reg , #MODE_MASK
349 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
350 THUMB( orr \reg , \reg , #PSR_T_BIT )
352 orr \reg, \reg, #PSR_A_BIT
361 * workaround for possibly broken pre-v6 hardware
362 * (akita, Sharp Zaurus C-1000, PXA270-based)
364 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
369 * STRT/LDRT access macros with ARM and Thumb-2 variants
371 #ifdef CONFIG_THUMB2_KERNEL
373 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
376 \instr\()b\t\cond\().w \reg, [\ptr, #\off]
378 \instr\t\cond\().w \reg, [\ptr, #\off]
380 .error "Unsupported inc macro argument"
383 .pushsection __ex_table,"a"
389 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
390 @ explicit IT instruction needed because of the label
391 @ introduced by the USER macro
398 .error "Unsupported rept macro argument"
402 @ Slightly optimised to avoid incrementing the pointer twice
403 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
405 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
408 add\cond \ptr, #\rept * \inc
411 #else /* !CONFIG_THUMB2_KERNEL */
413 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
417 \instr\()b\t\cond \reg, [\ptr], #\inc
419 \instr\t\cond \reg, [\ptr], #\inc
421 .error "Unsupported inc macro argument"
424 .pushsection __ex_table,"a"
431 #endif /* CONFIG_THUMB2_KERNEL */
433 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
434 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
437 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
438 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
441 /* Utility macro for declaring string literals */
442 .macro string name:req, string
443 .type \name , #object
446 .size \name , . - \name
449 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
451 #if __LINUX_ARM_ARCH__ < 6
465 #ifdef CONFIG_THUMB2_KERNEL
470 .macro bug, msg, line
471 #ifdef CONFIG_THUMB2_KERNEL
476 #ifdef CONFIG_DEBUG_BUGVERBOSE
477 .pushsection .rodata.str, "aMS", %progbits, 1
480 .pushsection __bug_table, "aw"
488 #ifdef CONFIG_KPROBES
489 #define _ASM_NOKPROBE(entry) \
490 .pushsection "_kprobe_blacklist", "aw" ; \
495 #define _ASM_NOKPROBE(entry)
498 #endif /* __ASM_ASSEMBLER_H__ */