arch/arm/boot/dts/vf610-twr.dts

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 /dts-v1/;
  43 #include "vf610.dtsi"
  44
  45 / {
  46         model = "VF610 Tower Board";
  47         compatible = "fsl,vf610-twr", "fsl,vf610";
  48
  49         chosen {
  50                 bootargs = "console=ttyLP1,115200";
  51         };
  52
  53         memory {
  54                 reg = <0x80000000 0x8000000>;
  55         };
  56
  57         audio_ext: mclk_osc {
  58                 compatible = "fixed-clock";
  59                 #clock-cells = <0>;
  60                 clock-frequency = <24576000>;
  61         };
  62
  63         enet_ext: eth_osc {
  64                 compatible = "fixed-clock";
  65                 #clock-cells = <0>;
  66                 clock-frequency = <50000000>;
  67         };
  68
  69         regulators {
  70                 compatible = "simple-bus";
  71                 #address-cells = <1>;
  72                 #size-cells = <0>;
  73
  74                 reg_3p3v: regulator@0 {
  75                         compatible = "regulator-fixed";
  76                         reg = <0>;
  77                         regulator-name = "3P3V";
  78                         regulator-min-microvolt = <3300000>;
  79                         regulator-max-microvolt = <3300000>;
  80                         regulator-always-on;
  81                 };
  82
  83                 reg_vcc_3v3_mcu: regulator@1 {
  84                         compatible = "regulator-fixed";
  85                         reg = <1>;
  86                         regulator-name = "vcc_3v3_mcu";
  87                         regulator-min-microvolt = <3300000>;
  88                         regulator-max-microvolt = <3300000>;
  89                 };
  90         };
  91
  92         sound {
  93                 compatible = "simple-audio-card";
  94                 simple-audio-card,format = "i2s";
  95                 simple-audio-card,widgets =
  96                         "Microphone", "Microphone Jack",
  97                         "Headphone", "Headphone Jack",
  98                         "Speaker", "Speaker Ext",
  99                         "Line", "Line In Jack";
 100                 simple-audio-card,routing =
 101                         "MIC_IN", "Microphone Jack",
 102                         "Microphone Jack", "Mic Bias",
 103                         "LINE_IN", "Line In Jack",
 104                         "Headphone Jack", "HP_OUT",
 105                         "Speaker Ext", "LINE_OUT";
 106
 107                 simple-audio-card,cpu {
 108                         sound-dai = <&sai2>;
 109                         frame-master;
 110                         bitclock-master;
 111                 };
 112
 113                 simple-audio-card,codec {
 114                         sound-dai = <&codec>;
 115                         frame-master;
 116                         bitclock-master;
 117                 };
 118         };
 119 };
 120
 121 &adc0 {
 122         pinctrl-names = "default";
 123         pinctrl-0 = <&pinctrl_adc0_ad5>;
 124         vref-supply = <&reg_vcc_3v3_mcu>;
 125         status = "okay";
 126 };
 127
 128 &clks {
 129         clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>;
 130         clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
 131         assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
 132                           <&clks VF610_CLK_ENET_TS_SEL>;
 133         assigned-clock-parents = <&clks VF610_CLK_ENET_EXT>,
 134                                  <&clks VF610_CLK_ENET_EXT>;
 135 };
 136
 137 &dspi0 {
 138         bus-num = <0>;
 139         pinctrl-names = "default";
 140         pinctrl-0 = <&pinctrl_dspi0>;
 141         status = "okay";
 142
 143         sflash: at26df081a@0 {
 144                 #address-cells = <1>;
 145                 #size-cells = <1>;
 146                 compatible = "atmel,at26df081a";
 147                 spi-max-frequency = <16000000>;
 148                 spi-cpol;
 149                 spi-cpha;
 150                 reg = <0>;
 151         };
 152 };
 153
 154 &edma0 {
 155         status = "okay";
 156 };
 157
 158 &esdhc1 {
 159         pinctrl-names = "default";
 160         pinctrl-0 = <&pinctrl_esdhc1>;
 161         bus-width = <4>;
 162         cd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
 163         status = "okay";
 164 };
 165
 166 &fec0 {
 167         phy-mode = "rmii";
 168         phy-handle = <&ethphy0>;
 169         pinctrl-names = "default";
 170         pinctrl-0 = <&pinctrl_fec0>;
 171         status = "okay";
 172
 173         mdio {
 174                 #address-cells = <1>;
 175                 #size-cells = <0>;
 176
 177                 ethphy0: ethernet-phy@0 {
 178                         reg = <0>;
 179                 };
 180
 181                 ethphy1: ethernet-phy@1 {
 182                         reg = <1>;
 183                 };
 184         };
 185 };
 186
 187 &fec1 {
 188         phy-mode = "rmii";
 189         phy-handle = <&ethphy1>;
 190         pinctrl-names = "default";
 191         pinctrl-0 = <&pinctrl_fec1>;
 192         status = "okay";
 193 };
 194
 195 &i2c0 {
 196         clock-frequency = <100000>;
 197         pinctrl-names = "default";
 198         pinctrl-0 = <&pinctrl_i2c0>;
 199         status = "okay";
 200
 201         codec: sgtl5000@0a {
 202                #sound-dai-cells = <0>;
 203                compatible = "fsl,sgtl5000";
 204                reg = <0x0a>;
 205                VDDA-supply = <&reg_3p3v>;
 206                VDDIO-supply = <&reg_3p3v>;
 207                clocks = <&clks VF610_CLK_SAI2>;
 208        };
 209 };
 210
 211 &iomuxc {
 212         vf610-twr {
 213                 pinctrl_adc0_ad5: adc0ad5grp {
 214                         fsl,pins = <
 215                                 VF610_PAD_PTC30__ADC0_SE5               0xa1
 216                         >;
 217                 };
 218
 219                 pinctrl_dspi0: dspi0grp {
 220                         fsl,pins = <
 221                                 VF610_PAD_PTB19__DSPI0_CS0              0x1182
 222                                 VF610_PAD_PTB20__DSPI0_SIN              0x1181
 223                                 VF610_PAD_PTB21__DSPI0_SOUT             0x1182
 224                                 VF610_PAD_PTB22__DSPI0_SCK              0x1182
 225                         >;
 226                 };
 227
 228                 pinctrl_esdhc1: esdhc1grp {
 229                         fsl,pins = <
 230                                 VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
 231                                 VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
 232                                 VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
 233                                 VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
 234                                 VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
 235                                 VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
 236                                 VF610_PAD_PTA7__GPIO_134        0x219d
 237                         >;
 238                 };
 239
 240                 pinctrl_fec0: fec0grp {
 241                         fsl,pins = <
 242                                 VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 243                                 VF610_PAD_PTC0__ENET_RMII0_MDC          0x30d3
 244                                 VF610_PAD_PTC1__ENET_RMII0_MDIO         0x30d1
 245                                 VF610_PAD_PTC2__ENET_RMII0_CRS          0x30d1
 246                                 VF610_PAD_PTC3__ENET_RMII0_RXD1         0x30d1
 247                                 VF610_PAD_PTC4__ENET_RMII0_RXD0         0x30d1
 248                                 VF610_PAD_PTC5__ENET_RMII0_RXER         0x30d1
 249                                 VF610_PAD_PTC6__ENET_RMII0_TXD1         0x30d2
 250                                 VF610_PAD_PTC7__ENET_RMII0_TXD0         0x30d2
 251                                 VF610_PAD_PTC8__ENET_RMII0_TXEN         0x30d2
 252                         >;
 253                 };
 254
 255                 pinctrl_fec1: fec1grp {
 256                         fsl,pins = <
 257                                 VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 258                                 VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 259                                 VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 260                                 VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 261                                 VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 262                                 VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 263                                 VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 264                                 VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 265                                 VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 266                         >;
 267                 };
 268
 269                 pinctrl_i2c0: i2c0grp {
 270                         fsl,pins = <
 271                                 VF610_PAD_PTB14__I2C0_SCL               0x30d3
 272                                 VF610_PAD_PTB15__I2C0_SDA               0x30d3
 273                         >;
 274                 };
 275
 276                 pinctrl_nfc: nfcgrp {
 277                         fsl,pins = <
 278                                 VF610_PAD_PTD31__NF_IO15        0x28df
 279                                 VF610_PAD_PTD30__NF_IO14        0x28df
 280                                 VF610_PAD_PTD29__NF_IO13        0x28df
 281                                 VF610_PAD_PTD28__NF_IO12        0x28df
 282                                 VF610_PAD_PTD27__NF_IO11        0x28df
 283                                 VF610_PAD_PTD26__NF_IO10        0x28df
 284                                 VF610_PAD_PTD25__NF_IO9         0x28df
 285                                 VF610_PAD_PTD24__NF_IO8         0x28df
 286                                 VF610_PAD_PTD23__NF_IO7         0x28df
 287                                 VF610_PAD_PTD22__NF_IO6         0x28df
 288                                 VF610_PAD_PTD21__NF_IO5         0x28df
 289                                 VF610_PAD_PTD20__NF_IO4         0x28df
 290                                 VF610_PAD_PTD19__NF_IO3         0x28df
 291                                 VF610_PAD_PTD18__NF_IO2         0x28df
 292                                 VF610_PAD_PTD17__NF_IO1         0x28df
 293                                 VF610_PAD_PTD16__NF_IO0         0x28df
 294                                 VF610_PAD_PTB24__NF_WE_B        0x28c2
 295                                 VF610_PAD_PTB25__NF_CE0_B       0x28c2
 296                                 VF610_PAD_PTB27__NF_RE_B        0x28c2
 297                                 VF610_PAD_PTC26__NF_RB_B        0x283d
 298                                 VF610_PAD_PTC27__NF_ALE         0x28c2
 299                                 VF610_PAD_PTC28__NF_CLE         0x28c2
 300                         >;
 301                 };
 302
 303                 pinctrl_pwm0: pwm0grp {
 304                         fsl,pins = <
 305                                 VF610_PAD_PTB0__FTM0_CH0                0x1582
 306                                 VF610_PAD_PTB1__FTM0_CH1                0x1582
 307                                 VF610_PAD_PTB2__FTM0_CH2                0x1582
 308                                 VF610_PAD_PTB3__FTM0_CH3                0x1582
 309                         >;
 310                 };
 311
 312                 pinctrl_sai2: sai2grp {
 313                         fsl,pins = <
 314                                 VF610_PAD_PTA16__SAI2_TX_BCLK           0x02ed
 315                                 VF610_PAD_PTA18__SAI2_TX_DATA           0x02ee
 316                                 VF610_PAD_PTA19__SAI2_TX_SYNC           0x02ed
 317                                 VF610_PAD_PTA21__SAI2_RX_BCLK           0x02ed
 318                                 VF610_PAD_PTA22__SAI2_RX_DATA           0x02ed
 319                                 VF610_PAD_PTA23__SAI2_RX_SYNC           0x02ed
 320                                 VF610_PAD_PTB18__EXT_AUDIO_MCLK         0x02ed
 321                         >;
 322                 };
 323
 324                 pinctrl_uart1: uart1grp {
 325                         fsl,pins = <
 326                                 VF610_PAD_PTB4__UART1_TX                0x21a2
 327                                 VF610_PAD_PTB5__UART1_RX                0x21a1
 328                         >;
 329                 };
 330
 331                 pinctrl_uart2: uart2grp {
 332                         fsl,pins = <
 333                                 VF610_PAD_PTB6__UART2_TX                0x21a2
 334                                 VF610_PAD_PTB7__UART2_RX                0x21a1
 335                         >;
 336                 };
 337         };
 338 };
 339
 340 &nfc {
 341         assigned-clocks = <&clks VF610_CLK_NFC>;
 342         assigned-clock-rates = <33000000>;
 343         pinctrl-names = "default";
 344         pinctrl-0 = <&pinctrl_nfc>;
 345         status = "okay";
 346
 347         nand@0 {
 348                 compatible = "fsl,vf610-nfc-nandcs";
 349                 reg = <0>;
 350                 #address-cells = <1>;
 351                 #size-cells = <1>;
 352                 nand-bus-width = <16>;
 353                 nand-ecc-mode = "hw";
 354                 nand-ecc-strength = <24>;
 355                 nand-ecc-step-size = <2048>;
 356                 nand-on-flash-bbt;
 357         };
 358 };
 359
 360 &pwm0 {
 361         pinctrl-names = "default";
 362         pinctrl-0 = <&pinctrl_pwm0>;
 363         status = "okay";
 364 };
 365
 366 &sai2 {
 367         #sound-dai-cells = <0>;
 368         pinctrl-names = "default";
 369         pinctrl-0 = <&pinctrl_sai2>;
 370         status = "okay";
 371 };
 372
 373 &uart1 {
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&pinctrl_uart1>;
 376         status = "okay";
 377 };
 378
 379 &uart2 {
 380         pinctrl-names = "default";
 381         pinctrl-0 = <&pinctrl_uart2>;
 382         status = "okay";
 383 };
 384
 385 &usbdev0 {
 386         disable-over-current;
 387         status = "okay";
 388 };
 389
 390 &usbh1 {
 391         disable-over-current;
 392         status = "okay";
 393 };
 394
 395 &usbmisc0 {
 396         status = "okay";
 397 };
 398
 399 &usbmisc1 {
 400         status = "okay";
 401 };
 402
 403 &usbphy0 {
 404         status = "okay";
 405 };
 406
 407 &usbphy1 {
 408         status = "okay";
 409 };