arch/arm/boot/dts/rk3288-veyron-sdmmc.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Veyron (and derivatives) fragment for sdmmc cards
   4  *
   5  * Copyright 2015 Google, Inc
   6  */
   7
   8 &io_domains {
   9         sdcard-supply = <&vccio_sd>;
  10 };
  11
  12 &pinctrl {
  13         sdmmc {
  14                 /*
  15                  * We run sdmmc at max speed; bump up drive strength.
  16                  * We also have external pulls, so disable the internal ones.
  17                  */
  18                 sdmmc_bus4: sdmmc-bus4 {
  19                         rockchip,pins = <6 RK_PC0 1 &pcfg_pull_none_drv_8ma>,
  20                                         <6 RK_PC1 1 &pcfg_pull_none_drv_8ma>,
  21                                         <6 RK_PC2 1 &pcfg_pull_none_drv_8ma>,
  22                                         <6 RK_PC3 1 &pcfg_pull_none_drv_8ma>;
  23                 };
  24
  25                 sdmmc_clk: sdmmc-clk {
  26                         rockchip,pins = <6 RK_PC4 1 &pcfg_pull_none_drv_8ma>;
  27                 };
  28
  29                 sdmmc_cmd: sdmmc-cmd {
  30                         rockchip,pins = <6 RK_PC5 1 &pcfg_pull_none_drv_8ma>;
  31                 };
  32
  33                 /*
  34                  * Builtin CD line is hooked to ground to prevent JTAG at boot
  35                  * (and also to get the voltage rail correct).
  36                  * Configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
  37                  * think there's a card inserted
  38                  */
  39                 sdmmc_cd_disabled: sdmmc-cd-disabled {
  40                         rockchip,pins = <6 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
  41                 };
  42
  43                 /* This is where we actually hook up CD */
  44                 sdmmc_cd_gpio: sdmmc-cd-gpio {
  45                         rockchip,pins = <7 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
  46                 };
  47         };
  48 };
  49
  50 &rk808 {
  51         vcc9-supply = <&vcc_5v>;
  52
  53         regulators {
  54                 vccio_sd: LDO_REG4 {
  55                         regulator-name = "vccio_sd";
  56                         regulator-min-microvolt = <1800000>;
  57                         regulator-max-microvolt = <3300000>;
  58                         regulator-state-mem {
  59                                 regulator-off-in-suspend;
  60                         };
  61                 };
  62
  63                 vcc33_sd: LDO_REG5 {
  64                         regulator-name = "vcc33_sd";
  65                         regulator-min-microvolt = <3300000>;
  66                         regulator-max-microvolt = <3300000>;
  67                         regulator-state-mem {
  68                                 regulator-off-in-suspend;
  69                         };
  70                 };
  71         };
  72 };
  73
  74 &sdmmc {
  75         status = "okay";
  76
  77         bus-width = <4>;
  78         cap-mmc-highspeed;
  79         cap-sd-highspeed;
  80         card-detect-delay = <200>;
  81         cd-gpios = <&gpio7 RK_PA5 GPIO_ACTIVE_LOW>;
  82         rockchip,default-sample-phase = <90>;
  83         sd-uhs-sdr12;
  84         sd-uhs-sdr25;
  85         sd-uhs-sdr50;
  86         sd-uhs-sdr104;
  87         vmmc-supply = <&vcc33_sd>;
  88         vqmmc-supply = <&vccio_sd>;
  89 };