arch/arm/boot/dts/imx6qdl-var-dart.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Support for Variscite DART-MX6 Module
   4  *
   5  * Copyright 2017 BayLibre, SAS
   6  * Author: Neil Armstrong <narmstrong@baylibre.com>
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/sound/fsl-imx-audmux.h>
  11
  12 / {
  13         memory@10000000 {
  14                 device_type = "memory";
  15                 reg = <0x10000000 0x40000000>;
  16         };
  17
  18         reg_3p3v: regulator-3p3v {
  19                 compatible = "regulator-fixed";
  20                 regulator-name = "3P3V";
  21                 regulator-min-microvolt = <3300000>;
  22                 regulator-max-microvolt = <3300000>;
  23                 regulator-always-on;
  24         };
  25
  26         reg_wl18xx_vmmc: regulator-wl18xx {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "vwl1807";
  29                 regulator-min-microvolt = <1800000>;
  30                 regulator-max-microvolt = <1800000>;
  31                 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
  32                 enable-active-high;
  33                 startup-delay-us = <70000>;
  34         };
  35 };
  36
  37 &audmux {
  38         pinctrl-names = "default";
  39         pinctrl-0 = <&pinctrl_audmux>;
  40         status = "okay";
  41
  42         ssi2 {
  43                 fsl,audmux-port = <1>;
  44                 fsl,port-config = <
  45                         (IMX_AUDMUX_V2_PTCR_SYN |
  46                         IMX_AUDMUX_V2_PTCR_TFSDIR |
  47                         IMX_AUDMUX_V2_PTCR_TFSEL(2) |
  48                         IMX_AUDMUX_V2_PTCR_TCLKDIR |
  49                         IMX_AUDMUX_V2_PTCR_TCSEL(2))
  50                         IMX_AUDMUX_V2_PDCR_RXDSEL(2)
  51                 >;
  52         };
  53
  54         aud3 {
  55                 fsl,audmux-port = <2>;
  56                 fsl,port-config = <
  57                         IMX_AUDMUX_V2_PTCR_SYN
  58                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)
  59                 >;
  60         };
  61 };
  62
  63 &can1 {
  64         pinctrl-names = "default";
  65         pinctrl-0 = <&pinctrl_flexcan1>;
  66         status = "disabled";
  67 };
  68
  69 &can2 {
  70         pinctrl-names = "default";
  71         pinctrl-0 = <&pinctrl_flexcan2>;
  72         status = "disabled";
  73 };
  74
  75 &ecspi1 {
  76         pinctrl-names = "default";
  77         pinctrl-0 = <&pinctrl_ecspi1>;
  78         status = "disabled";
  79 };
  80
  81 &fec {
  82         pinctrl-names = "default";
  83         pinctrl-0 = <&pinctrl_enet>;
  84         phy-mode = "rgmii";
  85         status = "disabled";
  86 };
  87
  88 &hdmi {
  89         pinctrl-names = "default";
  90         pinctrl-0 = <&pinctrl_hdmicec>;
  91         ddc-i2c-bus = <&i2c1>;
  92         status = "disabled";
  93 };
  94
  95 &i2c1 {
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&pinctrl_i2c1>;
  98         status = "disabled";
  99 };
 100
 101 &i2c2 {
 102         clock-frequency = <100000>;
 103         pinctrl-names = "default";
 104         pinctrl-0 = <&pinctrl_i2c2>;
 105         status = "okay";
 106
 107         pmic@8 {
 108                 pinctrl-names = "default";
 109                 pinctrl-0 = <&pinctrl_pmic>;
 110                 compatible = "fsl,pfuze100";
 111                 reg = <0x08>;
 112
 113                 regulators {
 114                         sw1a_reg: sw1ab {
 115                                 regulator-min-microvolt = <300000>;
 116                                 regulator-max-microvolt = <1875000>;
 117                                 regulator-boot-on;
 118                                 regulator-always-on;
 119                                 regulator-ramp-delay = <6250>;
 120                         };
 121
 122                         sw1c_reg: sw1c {
 123                                 regulator-min-microvolt = <300000>;
 124                                 regulator-max-microvolt = <1875000>;
 125                                 regulator-boot-on;
 126                                 regulator-always-on;
 127                                 regulator-ramp-delay = <6250>;
 128                         };
 129
 130                         sw2_reg: sw2 {
 131                                 regulator-min-microvolt = <800000>;
 132                                 regulator-max-microvolt = <3300000>;
 133                                 regulator-boot-on;
 134                                 regulator-always-on;
 135                         };
 136
 137                         sw3a_reg: sw3a {
 138                                 regulator-min-microvolt = <800000>;
 139                                 regulator-max-microvolt = <3950000>;
 140                                 regulator-boot-on;
 141                                 regulator-always-on;
 142                         };
 143
 144                         sw3b_reg: sw3b {
 145                                 regulator-min-microvolt = <800000>;
 146                                 regulator-max-microvolt = <3950000>;
 147                                 regulator-boot-on;
 148                                 regulator-always-on;
 149                         };
 150
 151                         sw4_reg: sw4 {
 152                                 regulator-min-microvolt = <800000>;
 153                                 regulator-max-microvolt = <3950000>;
 154                         };
 155
 156                         snvs_reg: vsnvs {
 157                                 regulator-min-microvolt = <1200000>;
 158                                 regulator-max-microvolt = <3000000>;
 159                                 regulator-boot-on;
 160                                 regulator-always-on;
 161                         };
 162
 163                         vref_reg: vrefddr {
 164                                 regulator-boot-on;
 165                                 regulator-always-on;
 166                         };
 167
 168                         vgen6_reg: vgen6 {
 169                                 regulator-min-microvolt = <2800000>;
 170                                 regulator-max-microvolt = <2800000>;
 171                                 regulator-always-on;
 172                                 regulator-boot-on;
 173                         };
 174                 };
 175         };
 176
 177         tlv320aic3106: codec@1b {
 178                 compatible = "ti,tlv320aic3106";
 179                 reg = <0x1b>;
 180                 #sound-dai-cells = <0>;
 181                 DRVDD-supply = <&reg_3p3v>;
 182                 AVDD-supply = <&reg_3p3v>;
 183                 IOVDD-supply = <&reg_3p3v>;
 184                 DVDD-supply = <&reg_3p3v>;
 185                 ai3x-ocmv = <0>;
 186                 reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
 187         };
 188 };
 189
 190 &i2c3 {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_i2c3>;
 193         status = "disabled";
 194 };
 195
 196 &iomuxc {
 197         pinctrl_audmux: audmux {
 198                 fsl,pins = <
 199                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
 200                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 201                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
 202                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 203                         /* Audio Clock */
 204                         MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0
 205                 >;
 206         };
 207
 208         pinctrl_bt: bt {
 209                 fsl,pins = <
 210                         /* Bluetooth enable */
 211                         MX6QDL_PAD_SD3_DAT6__GPIO6_IO18         0x1b0b1
 212                         /* Bluetooth Slow Clock */
 213                         MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT    0x000b0
 214                 >;
 215         };
 216
 217         pinctrl_ecspi1: ecspi1grp {
 218                 fsl,pins = <
 219                         MX6QDL_PAD_KEY_COL1__ECSPI1_MISO        0x100b1
 220                         MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI        0x100b1
 221                         MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK        0x100b1
 222                         /* SPI1 CS0 */
 223                         MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x1b0b0
 224                         /* SPI1 CS1 */
 225                         MX6QDL_PAD_KEY_COL2__GPIO4_IO10         0x1b0b0
 226                 >;
 227         };
 228
 229         pinctrl_enet: enetgrp {
 230                 fsl,pins = <
 231                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
 232                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
 233                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x10030
 234                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x10030
 235                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x10030
 236                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x10030
 237                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x10030
 238                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x10030
 239                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
 240                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 241                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 242                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 243                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 244                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 245                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 246                 >;
 247         };
 248
 249         pinctrl_flexcan1: flexcan1grp {
 250                 fsl,pins = <
 251                         MX6QDL_PAD_GPIO_7__FLEXCAN1_TX  0x1b0b0
 252                         MX6QDL_PAD_GPIO_8__FLEXCAN1_RX  0x1b0b0
 253                 >;
 254         };
 255
 256         pinctrl_flexcan2: flexcan2grp {
 257                 fsl,pins = <
 258                         MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX        0x1b0b0
 259                         MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX        0x1b0b0
 260                 >;
 261         };
 262
 263         pinctrl_hdmicec: hdmicecgrp {
 264                 fsl,pins = <
 265                         MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE   0x1f8b0
 266                 >;
 267         };
 268
 269         pinctrl_i2c1: i2c1grp {
 270                 fsl,pins = <
 271                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA  0x4001b8b1
 272                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL  0x4001b8b1
 273                 >;
 274         };
 275
 276         pinctrl_i2c2: i2c2grp {
 277                 fsl,pins = <
 278                         MX6QDL_PAD_KEY_COL3__I2C2_SCL   0x4001b8b1
 279                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA   0x4001b8b1
 280                 >;
 281         };
 282
 283         pinctrl_i2c3: i2c3grp {
 284                 fsl,pins = <
 285                         MX6QDL_PAD_GPIO_5__I2C3_SCL     0x4001b8b1
 286                         MX6QDL_PAD_GPIO_16__I2C3_SDA    0x4001b8b1
 287                 >;
 288         };
 289
 290         pinctrl_pmic: pmicgrp {
 291                 fsl,pins = <
 292                         /* PMIC INT */
 293                         MX6QDL_PAD_GPIO_17__GPIO7_IO12  0x1b0b1
 294                 >;
 295         };
 296
 297         pinctrl_pwm2: pwm2grp {
 298                 fsl,pins = <
 299                         MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
 300                 >;
 301         };
 302
 303         pinctrl_uart1: uart1grp {
 304                 fsl,pins = <
 305                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
 306                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
 307                 >;
 308         };
 309
 310         pinctrl_uart2: uart2grp {
 311                 fsl,pins = <
 312                         MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA      0x1b0b1
 313                         MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA      0x1b0b1
 314                         MX6QDL_PAD_SD4_DAT6__UART2_CTS_B        0x1b0b1
 315                         MX6QDL_PAD_SD4_DAT5__UART2_RTS_B        0x1b0b1
 316                 >;
 317         };
 318
 319         pinctrl_uart3: uart3grp {
 320                 fsl,pins = <
 321                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
 322                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
 323                         MX6QDL_PAD_EIM_D23__UART3_CTS_B   0x1b0b1
 324                         MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
 325                 >;
 326         };
 327
 328         pinctrl_usbotg: usbotggrp {
 329                 fsl,pins = <
 330                         MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
 331                 >;
 332         };
 333
 334         pinctrl_usdhc1: usdhc1grp {
 335                 fsl,pins = <
 336                         MX6QDL_PAD_SD1_CMD__SD1_CMD     0x17059
 337                         MX6QDL_PAD_SD1_CLK__SD1_CLK     0x10059
 338                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0  0x17059
 339                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1  0x17059
 340                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2  0x17059
 341                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3  0x17059
 342                         /* WL_EN */
 343                         MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x17071
 344                         /* WL_IRQ */
 345                         MX6QDL_PAD_SD3_RST__GPIO7_IO08  0x17071
 346                 >;
 347         };
 348
 349         pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
 350                 fsl,pins = <
 351                         MX6QDL_PAD_SD1_CMD__SD1_CMD     0x170B9
 352                         MX6QDL_PAD_SD1_CLK__SD1_CLK     0x100B9
 353                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0  0x170B9
 354                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1  0x170B9
 355                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2  0x170B9
 356                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3  0x170B9
 357                 >;
 358         };
 359
 360         pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
 361                 fsl,pins = <
 362                         MX6QDL_PAD_SD1_CMD__SD1_CMD     0x170F9
 363                         MX6QDL_PAD_SD1_CLK__SD1_CLK     0x100F9
 364                         MX6QDL_PAD_SD1_DAT0__SD1_DATA0  0x170F9
 365                         MX6QDL_PAD_SD1_DAT1__SD1_DATA1  0x170F9
 366                         MX6QDL_PAD_SD1_DAT2__SD1_DATA2  0x170F9
 367                         MX6QDL_PAD_SD1_DAT3__SD1_DATA3  0x170F9
 368                 >;
 369         };
 370
 371         pinctrl_usdhc2: usdhc2grp {
 372                 fsl,pins = <
 373                         MX6QDL_PAD_SD2_CMD__SD2_CMD     0x17059
 374                         MX6QDL_PAD_SD2_CLK__SD2_CLK     0x10059
 375                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0  0x17059
 376                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1  0x17059
 377                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2  0x17059
 378                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3  0x17059
 379                 >;
 380         };
 381
 382         pinctrl_usdhc3: usdhc3grp {
 383                 fsl,pins = <
 384                         MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
 385                         MX6QDL_PAD_SD3_CLK__SD3_CLK     0x10059
 386                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x17059
 387                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x17059
 388                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x17059
 389                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x17059
 390                 >;
 391         };
 392 };
 393
 394 &pcie {
 395         fsl,tx-swing-full = <103>;
 396         fsl,tx-swing-low = <103>;
 397         reset-gpio = <&gpio4 11 GPIO_ACTIVE_LOW>;
 398         status = "disabled";
 399 };
 400
 401 &pwm2 {
 402         pinctrl-names = "default";
 403         pinctrl-0 = <&pinctrl_pwm2>;
 404         status = "disabled";
 405 };
 406
 407 &reg_arm {
 408         vin-supply = <&sw1a_reg>;
 409 };
 410
 411 &reg_pu {
 412         vin-supply = <&sw1c_reg>;
 413 };
 414
 415 &reg_soc {
 416         vin-supply = <&sw1c_reg>;
 417 };
 418
 419 &snvs_poweroff {
 420         status = "okay";
 421 };
 422
 423 &ssi2 {
 424         status = "okay";
 425 };
 426
 427 &uart1 {
 428         pinctrl-names = "default";
 429         pinctrl-0 = <&pinctrl_uart1>;
 430         status = "disabled";
 431 };
 432
 433 &uart2 {
 434         pinctrl-names = "default";
 435         pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt>;
 436         uart-has-rtscts;
 437         status = "okay";
 438
 439         bluetooth {
 440                 compatible = "ti,wl1835-st";
 441                 enable-gpios = <&gpio6 18 GPIO_ACTIVE_HIGH>;
 442         };
 443 };
 444
 445 &uart3 {
 446         pinctrl-names = "default";
 447         pinctrl-0 = <&pinctrl_uart3>;
 448         uart-has-rtscts;
 449         status = "disabled";
 450 };
 451
 452 &usbh1 {
 453         status = "disabled";
 454 };
 455
 456 &usbotg {
 457         vbus-supply = <&reg_usb_otg_vbus>;
 458         pinctrl-names = "default";
 459         pinctrl-0 = <&pinctrl_usbotg>;
 460         disable-over-current;
 461         status = "disabled";
 462 };
 463
 464 &usdhc1 {
 465         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 466         pinctrl-0 = <&pinctrl_usdhc1>;
 467         pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
 468         pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 469         bus-width = <4>;
 470         vmmc-supply = <&reg_wl18xx_vmmc>;
 471         non-removable;
 472         wakeup-source;
 473         keep-power-in-suspend;
 474         cap-power-off-card;
 475         #address-cells = <1>;
 476         #size-cells = <0>;
 477         status = "okay";
 478
 479         wlcore: wlcore@2 {
 480                 compatible = "ti,wl1835";
 481                 reg = <2>;
 482                 interrupt-parent = <&gpio6>;
 483                 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
 484                 ref-clock-frequency = <38400000>;
 485         };
 486 };
 487
 488 &usdhc2 {
 489         pinctrl-names = "default";
 490         pinctrl-0 = <&pinctrl_usdhc2>;
 491         no-1-8-v;
 492         keep-power-in-suspend;
 493         wakeup-source;
 494         status = "disabled";
 495 };
 496
 497 &usdhc3 {
 498         pinctrl-names = "default";
 499         pinctrl-0 = <&pinctrl_usdhc3>;
 500         non-removable;
 501         keep-power-in-suspend;
 502         wakeup-source;
 503         status = "okay";
 504 };