arch/arm/boot/dts/exynos4.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung's Exynos4 SoC series common device tree source
   4  *
   5  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  * Copyright (c) 2010-2011 Linaro Ltd.
   8  *              www.linaro.org
   9  *
  10  * Samsung's Exynos4 SoC series device nodes are listed in this file.  Particular
  11  * SoCs from Exynos4 series can include this file and provide values for SoCs
  12  * specfic bindings.
  13  *
  14  * Note: This file does not include device nodes for all the controllers in
  15  * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
  16  * nodes can be added to this file.
  17  */
  18
  19 #include <dt-bindings/clock/exynos4.h>
  20 #include <dt-bindings/clock/exynos-audss-clk.h>
  21 #include <dt-bindings/interrupt-controller/arm-gic.h>
  22 #include <dt-bindings/interrupt-controller/irq.h>
  23
  24 / {
  25         interrupt-parent = <&gic>;
  26         #address-cells = <1>;
  27         #size-cells = <1>;
  28
  29         aliases {
  30                 spi0 = &spi_0;
  31                 spi1 = &spi_1;
  32                 spi2 = &spi_2;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 i2c4 = &i2c_4;
  38                 i2c5 = &i2c_5;
  39                 i2c6 = &i2c_6;
  40                 i2c7 = &i2c_7;
  41                 i2c8 = &i2c_8;
  42                 csis0 = &csis_0;
  43                 csis1 = &csis_1;
  44                 fimc0 = &fimc_0;
  45                 fimc1 = &fimc_1;
  46                 fimc2 = &fimc_2;
  47                 fimc3 = &fimc_3;
  48                 serial0 = &serial_0;
  49                 serial1 = &serial_1;
  50                 serial2 = &serial_2;
  51                 serial3 = &serial_3;
  52         };
  53
  54         pmu: pmu {
  55                 compatible = "arm,cortex-a9-pmu";
  56                 interrupt-parent = <&combiner>;
  57                 status = "disabled";
  58         };
  59
  60         soc: soc {
  61                 compatible = "simple-bus";
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 ranges;
  65
  66                 clock_audss: clock-controller@3810000 {
  67                         compatible = "samsung,exynos4210-audss-clock";
  68                         reg = <0x03810000 0x0C>;
  69                         #clock-cells = <1>;
  70                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
  71                                  <&clock CLK_SCLK_AUDIO0>,
  72                                  <&clock CLK_SCLK_AUDIO0>;
  73                         clock-names = "pll_ref", "pll_in", "sclk_audio",
  74                                       "sclk_pcm_in";
  75                 };
  76
  77                 i2s0: i2s@3830000 {
  78                         compatible = "samsung,s5pv210-i2s";
  79                         reg = <0x03830000 0x100>;
  80                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
  81                                  <&clock_audss EXYNOS_DOUT_AUD_BUS>,
  82                                  <&clock_audss EXYNOS_SCLK_I2S>;
  83                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
  84                         #clock-cells = <1>;
  85                         clock-output-names = "i2s_cdclk0";
  86                         dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
  87                         dma-names = "tx", "rx", "tx-sec";
  88                         samsung,idma-addr = <0x03000000>;
  89                         #sound-dai-cells = <1>;
  90                         status = "disabled";
  91                 };
  92
  93                 chipid@10000000 {
  94                         compatible = "samsung,exynos4210-chipid";
  95                         reg = <0x10000000 0x100>;
  96                 };
  97
  98                 scu: snoop-control-unit@10500000 {
  99                         compatible = "arm,cortex-a9-scu";
 100                         reg = <0x10500000 0x2000>;
 101                 };
 102
 103                 memory-controller@12570000 {
 104                         compatible = "samsung,exynos4210-srom";
 105                         reg = <0x12570000 0x14>;
 106                 };
 107
 108                 mipi_phy: video-phy {
 109                         compatible = "samsung,s5pv210-mipi-video-phy";
 110                         #phy-cells = <1>;
 111                         syscon = <&pmu_system_controller>;
 112                 };
 113
 114                 pd_mfc: mfc-power-domain@10023c40 {
 115                         compatible = "samsung,exynos4210-pd";
 116                         reg = <0x10023C40 0x20>;
 117                         #power-domain-cells = <0>;
 118                         label = "MFC";
 119                 };
 120
 121                 pd_g3d: g3d-power-domain@10023c60 {
 122                         compatible = "samsung,exynos4210-pd";
 123                         reg = <0x10023C60 0x20>;
 124                         #power-domain-cells = <0>;
 125                         label = "G3D";
 126                 };
 127
 128                 pd_lcd0: lcd0-power-domain@10023c80 {
 129                         compatible = "samsung,exynos4210-pd";
 130                         reg = <0x10023C80 0x20>;
 131                         #power-domain-cells = <0>;
 132                         label = "LCD0";
 133                 };
 134
 135                 pd_tv: tv-power-domain@10023c20 {
 136                         compatible = "samsung,exynos4210-pd";
 137                         reg = <0x10023C20 0x20>;
 138                         #power-domain-cells = <0>;
 139                         power-domains = <&pd_lcd0>;
 140                         label = "TV";
 141                 };
 142
 143                 pd_cam: cam-power-domain@10023c00 {
 144                         compatible = "samsung,exynos4210-pd";
 145                         reg = <0x10023C00 0x20>;
 146                         #power-domain-cells = <0>;
 147                         label = "CAM";
 148                 };
 149
 150                 pd_gps: gps-power-domain@10023ce0 {
 151                         compatible = "samsung,exynos4210-pd";
 152                         reg = <0x10023CE0 0x20>;
 153                         #power-domain-cells = <0>;
 154                         label = "GPS";
 155                 };
 156
 157                 pd_gps_alive: gps-alive-power-domain@10023d00 {
 158                         compatible = "samsung,exynos4210-pd";
 159                         reg = <0x10023D00 0x20>;
 160                         #power-domain-cells = <0>;
 161                         label = "GPS alive";
 162                 };
 163
 164                 gic: interrupt-controller@10490000 {
 165                         compatible = "arm,cortex-a9-gic";
 166                         #interrupt-cells = <3>;
 167                         interrupt-controller;
 168                         reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
 169                 };
 170
 171                 combiner: interrupt-controller@10440000 {
 172                         compatible = "samsung,exynos4210-combiner";
 173                         #interrupt-cells = <2>;
 174                         interrupt-controller;
 175                         reg = <0x10440000 0x1000>;
 176                 };
 177
 178                 sys_reg: syscon@10010000 {
 179                         compatible = "samsung,exynos4-sysreg", "syscon";
 180                         reg = <0x10010000 0x400>;
 181                 };
 182
 183                 pmu_system_controller: system-controller@10020000 {
 184                         compatible = "samsung,exynos4210-pmu", "syscon";
 185                         reg = <0x10020000 0x4000>;
 186                         interrupt-controller;
 187                         #interrupt-cells = <3>;
 188                         interrupt-parent = <&gic>;
 189                 };
 190
 191                 dsi_0: dsi@11c80000 {
 192                         compatible = "samsung,exynos4210-mipi-dsi";
 193                         reg = <0x11C80000 0x10000>;
 194                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 195                         power-domains = <&pd_lcd0>;
 196                         phys = <&mipi_phy 1>;
 197                         phy-names = "dsim";
 198                         clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
 199                         clock-names = "bus_clk", "sclk_mipi";
 200                         status = "disabled";
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                 };
 204
 205                 camera: camera {
 206                         compatible = "samsung,fimc", "simple-bus";
 207                         status = "disabled";
 208                         #address-cells = <1>;
 209                         #size-cells = <1>;
 210                         #clock-cells = <1>;
 211                         clock-output-names = "cam_a_clkout", "cam_b_clkout";
 212                         ranges;
 213
 214                         fimc_0: fimc@11800000 {
 215                                 compatible = "samsung,exynos4210-fimc";
 216                                 reg = <0x11800000 0x1000>;
 217                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 218                                 clocks = <&clock CLK_FIMC0>,
 219                                          <&clock CLK_SCLK_FIMC0>;
 220                                 clock-names = "fimc", "sclk_fimc";
 221                                 power-domains = <&pd_cam>;
 222                                 samsung,sysreg = <&sys_reg>;
 223                                 iommus = <&sysmmu_fimc0>;
 224                                 status = "disabled";
 225                         };
 226
 227                         fimc_1: fimc@11810000 {
 228                                 compatible = "samsung,exynos4210-fimc";
 229                                 reg = <0x11810000 0x1000>;
 230                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 231                                 clocks = <&clock CLK_FIMC1>,
 232                                          <&clock CLK_SCLK_FIMC1>;
 233                                 clock-names = "fimc", "sclk_fimc";
 234                                 power-domains = <&pd_cam>;
 235                                 samsung,sysreg = <&sys_reg>;
 236                                 iommus = <&sysmmu_fimc1>;
 237                                 status = "disabled";
 238                         };
 239
 240                         fimc_2: fimc@11820000 {
 241                                 compatible = "samsung,exynos4210-fimc";
 242                                 reg = <0x11820000 0x1000>;
 243                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 244                                 clocks = <&clock CLK_FIMC2>,
 245                                          <&clock CLK_SCLK_FIMC2>;
 246                                 clock-names = "fimc", "sclk_fimc";
 247                                 power-domains = <&pd_cam>;
 248                                 samsung,sysreg = <&sys_reg>;
 249                                 iommus = <&sysmmu_fimc2>;
 250                                 status = "disabled";
 251                         };
 252
 253                         fimc_3: fimc@11830000 {
 254                                 compatible = "samsung,exynos4210-fimc";
 255                                 reg = <0x11830000 0x1000>;
 256                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 257                                 clocks = <&clock CLK_FIMC3>,
 258                                          <&clock CLK_SCLK_FIMC3>;
 259                                 clock-names = "fimc", "sclk_fimc";
 260                                 power-domains = <&pd_cam>;
 261                                 samsung,sysreg = <&sys_reg>;
 262                                 iommus = <&sysmmu_fimc3>;
 263                                 status = "disabled";
 264                         };
 265
 266                         csis_0: csis@11880000 {
 267                                 compatible = "samsung,exynos4210-csis";
 268                                 reg = <0x11880000 0x4000>;
 269                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 270                                 clocks = <&clock CLK_CSIS0>,
 271                                          <&clock CLK_SCLK_CSIS0>;
 272                                 clock-names = "csis", "sclk_csis";
 273                                 bus-width = <4>;
 274                                 power-domains = <&pd_cam>;
 275                                 phys = <&mipi_phy 0>;
 276                                 phy-names = "csis";
 277                                 status = "disabled";
 278                                 #address-cells = <1>;
 279                                 #size-cells = <0>;
 280                         };
 281
 282                         csis_1: csis@11890000 {
 283                                 compatible = "samsung,exynos4210-csis";
 284                                 reg = <0x11890000 0x4000>;
 285                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 286                                 clocks = <&clock CLK_CSIS1>,
 287                                          <&clock CLK_SCLK_CSIS1>;
 288                                 clock-names = "csis", "sclk_csis";
 289                                 bus-width = <2>;
 290                                 power-domains = <&pd_cam>;
 291                                 phys = <&mipi_phy 2>;
 292                                 phy-names = "csis";
 293                                 status = "disabled";
 294                                 #address-cells = <1>;
 295                                 #size-cells = <0>;
 296                         };
 297                 };
 298
 299                 rtc: rtc@10070000 {
 300                         compatible = "samsung,s3c6410-rtc";
 301                         reg = <0x10070000 0x100>;
 302                         interrupt-parent = <&pmu_system_controller>;
 303                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 304                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 305                         clocks = <&clock CLK_RTC>;
 306                         clock-names = "rtc";
 307                         status = "disabled";
 308                 };
 309
 310                 keypad: keypad@100a0000 {
 311                         compatible = "samsung,s5pv210-keypad";
 312                         reg = <0x100A0000 0x100>;
 313                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 314                         clocks = <&clock CLK_KEYIF>;
 315                         clock-names = "keypad";
 316                         status = "disabled";
 317                 };
 318
 319                 sdhci_0: sdhci@12510000 {
 320                         compatible = "samsung,exynos4210-sdhci";
 321                         reg = <0x12510000 0x100>;
 322                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 323                         clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 324                         clock-names = "hsmmc", "mmc_busclk.2";
 325                         status = "disabled";
 326                 };
 327
 328                 sdhci_1: sdhci@12520000 {
 329                         compatible = "samsung,exynos4210-sdhci";
 330                         reg = <0x12520000 0x100>;
 331                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 332                         clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 333                         clock-names = "hsmmc", "mmc_busclk.2";
 334                         status = "disabled";
 335                 };
 336
 337                 sdhci_2: sdhci@12530000 {
 338                         compatible = "samsung,exynos4210-sdhci";
 339                         reg = <0x12530000 0x100>;
 340                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 341                         clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 342                         clock-names = "hsmmc", "mmc_busclk.2";
 343                         status = "disabled";
 344                 };
 345
 346                 sdhci_3: sdhci@12540000 {
 347                         compatible = "samsung,exynos4210-sdhci";
 348                         reg = <0x12540000 0x100>;
 349                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 350                         clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 351                         clock-names = "hsmmc", "mmc_busclk.2";
 352                         status = "disabled";
 353                 };
 354
 355                 exynos_usbphy: exynos-usbphy@125b0000 {
 356                         compatible = "samsung,exynos4210-usb2-phy";
 357                         reg = <0x125B0000 0x100>;
 358                         samsung,pmureg-phandle = <&pmu_system_controller>;
 359                         clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
 360                         clock-names = "phy", "ref";
 361                         #phy-cells = <1>;
 362                         status = "disabled";
 363                 };
 364
 365                 hsotg: hsotg@12480000 {
 366                         compatible = "samsung,s3c6400-hsotg";
 367                         reg = <0x12480000 0x20000>;
 368                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 369                         clocks = <&clock CLK_USB_DEVICE>;
 370                         clock-names = "otg";
 371                         phys = <&exynos_usbphy 0>;
 372                         phy-names = "usb2-phy";
 373                         status = "disabled";
 374                 };
 375
 376                 ehci: ehci@12580000 {
 377                         compatible = "samsung,exynos4210-ehci";
 378                         reg = <0x12580000 0x100>;
 379                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 380                         clocks = <&clock CLK_USB_HOST>;
 381                         clock-names = "usbhost";
 382                         status = "disabled";
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         port@0 {
 386                                 reg = <0>;
 387                                 phys = <&exynos_usbphy 1>;
 388                                 status = "disabled";
 389                         };
 390                         port@1 {
 391                                 reg = <1>;
 392                                 phys = <&exynos_usbphy 2>;
 393                                 status = "disabled";
 394                         };
 395                         port@2 {
 396                                 reg = <2>;
 397                                 phys = <&exynos_usbphy 3>;
 398                                 status = "disabled";
 399                         };
 400                 };
 401
 402                 ohci: ohci@12590000 {
 403                         compatible = "samsung,exynos4210-ohci";
 404                         reg = <0x12590000 0x100>;
 405                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 406                         clocks = <&clock CLK_USB_HOST>;
 407                         clock-names = "usbhost";
 408                         status = "disabled";
 409                         #address-cells = <1>;
 410                         #size-cells = <0>;
 411                         port@0 {
 412                                 reg = <0>;
 413                                 phys = <&exynos_usbphy 1>;
 414                                 status = "disabled";
 415                         };
 416                 };
 417
 418                 gpu: gpu@13000000 {
 419                         compatible = "samsung,exynos4210-mali", "arm,mali-400";
 420                         reg = <0x13000000 0x10000>;
 421                         /*
 422                          * CLK_G3D is not actually bus clock but a IP-level clock.
 423                          * The bus clock is not described in hardware manual.
 424                          */
 425                         clocks = <&clock CLK_G3D>,
 426                                  <&clock CLK_SCLK_G3D>;
 427                         clock-names = "bus", "core";
 428                         power-domains = <&pd_g3d>;
 429                         status = "disabled";
 430                 };
 431
 432                 i2s1: i2s@13960000 {
 433                         compatible = "samsung,s3c6410-i2s";
 434                         reg = <0x13960000 0x100>;
 435                         clocks = <&clock CLK_I2S1>;
 436                         clock-names = "iis";
 437                         #clock-cells = <1>;
 438                         clock-output-names = "i2s_cdclk1";
 439                         dmas = <&pdma1 12>, <&pdma1 11>;
 440                         dma-names = "tx", "rx";
 441                         #sound-dai-cells = <1>;
 442                         status = "disabled";
 443                 };
 444
 445                 i2s2: i2s@13970000 {
 446                         compatible = "samsung,s3c6410-i2s";
 447                         reg = <0x13970000 0x100>;
 448                         clocks = <&clock CLK_I2S2>;
 449                         clock-names = "iis";
 450                         #clock-cells = <1>;
 451                         clock-output-names = "i2s_cdclk2";
 452                         dmas = <&pdma0 14>, <&pdma0 13>;
 453                         dma-names = "tx", "rx";
 454                         #sound-dai-cells = <1>;
 455                         status = "disabled";
 456                 };
 457
 458                 mfc: codec@13400000 {
 459                         compatible = "samsung,mfc-v5";
 460                         reg = <0x13400000 0x10000>;
 461                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 462                         power-domains = <&pd_mfc>;
 463                         clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
 464                         clock-names = "mfc", "sclk_mfc";
 465                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 466                         iommu-names = "left", "right";
 467                 };
 468
 469                 serial_0: serial@13800000 {
 470                         compatible = "samsung,exynos4210-uart";
 471                         reg = <0x13800000 0x100>;
 472                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 473                         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 474                         clock-names = "uart", "clk_uart_baud0";
 475                         dmas = <&pdma0 15>, <&pdma0 16>;
 476                         dma-names = "rx", "tx";
 477                         status = "disabled";
 478                 };
 479
 480                 serial_1: serial@13810000 {
 481                         compatible = "samsung,exynos4210-uart";
 482                         reg = <0x13810000 0x100>;
 483                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 484                         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 485                         clock-names = "uart", "clk_uart_baud0";
 486                         dmas = <&pdma1 15>, <&pdma1 16>;
 487                         dma-names = "rx", "tx";
 488                         status = "disabled";
 489                 };
 490
 491                 serial_2: serial@13820000 {
 492                         compatible = "samsung,exynos4210-uart";
 493                         reg = <0x13820000 0x100>;
 494                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 495                         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 496                         clock-names = "uart", "clk_uart_baud0";
 497                         dmas = <&pdma0 17>, <&pdma0 18>;
 498                         dma-names = "rx", "tx";
 499                         status = "disabled";
 500                 };
 501
 502                 serial_3: serial@13830000 {
 503                         compatible = "samsung,exynos4210-uart";
 504                         reg = <0x13830000 0x100>;
 505                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 506                         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 507                         clock-names = "uart", "clk_uart_baud0";
 508                         dmas = <&pdma1 17>, <&pdma1 18>;
 509                         dma-names = "rx", "tx";
 510                         status = "disabled";
 511                 };
 512
 513                 i2c_0: i2c@13860000 {
 514                         #address-cells = <1>;
 515                         #size-cells = <0>;
 516                         compatible = "samsung,s3c2440-i2c";
 517                         reg = <0x13860000 0x100>;
 518                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 519                         clocks = <&clock CLK_I2C0>;
 520                         clock-names = "i2c";
 521                         pinctrl-names = "default";
 522                         pinctrl-0 = <&i2c0_bus>;
 523                         status = "disabled";
 524                 };
 525
 526                 i2c_1: i2c@13870000 {
 527                         #address-cells = <1>;
 528                         #size-cells = <0>;
 529                         compatible = "samsung,s3c2440-i2c";
 530                         reg = <0x13870000 0x100>;
 531                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 532                         clocks = <&clock CLK_I2C1>;
 533                         clock-names = "i2c";
 534                         pinctrl-names = "default";
 535                         pinctrl-0 = <&i2c1_bus>;
 536                         status = "disabled";
 537                 };
 538
 539                 i2c_2: i2c@13880000 {
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                         compatible = "samsung,s3c2440-i2c";
 543                         reg = <0x13880000 0x100>;
 544                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 545                         clocks = <&clock CLK_I2C2>;
 546                         clock-names = "i2c";
 547                         pinctrl-names = "default";
 548                         pinctrl-0 = <&i2c2_bus>;
 549                         status = "disabled";
 550                 };
 551
 552                 i2c_3: i2c@13890000 {
 553                         #address-cells = <1>;
 554                         #size-cells = <0>;
 555                         compatible = "samsung,s3c2440-i2c";
 556                         reg = <0x13890000 0x100>;
 557                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 558                         clocks = <&clock CLK_I2C3>;
 559                         clock-names = "i2c";
 560                         pinctrl-names = "default";
 561                         pinctrl-0 = <&i2c3_bus>;
 562                         status = "disabled";
 563                 };
 564
 565                 i2c_4: i2c@138a0000 {
 566                         #address-cells = <1>;
 567                         #size-cells = <0>;
 568                         compatible = "samsung,s3c2440-i2c";
 569                         reg = <0x138A0000 0x100>;
 570                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 571                         clocks = <&clock CLK_I2C4>;
 572                         clock-names = "i2c";
 573                         pinctrl-names = "default";
 574                         pinctrl-0 = <&i2c4_bus>;
 575                         status = "disabled";
 576                 };
 577
 578                 i2c_5: i2c@138b0000 {
 579                         #address-cells = <1>;
 580                         #size-cells = <0>;
 581                         compatible = "samsung,s3c2440-i2c";
 582                         reg = <0x138B0000 0x100>;
 583                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 584                         clocks = <&clock CLK_I2C5>;
 585                         clock-names = "i2c";
 586                         pinctrl-names = "default";
 587                         pinctrl-0 = <&i2c5_bus>;
 588                         status = "disabled";
 589                 };
 590
 591                 i2c_6: i2c@138c0000 {
 592                         #address-cells = <1>;
 593                         #size-cells = <0>;
 594                         compatible = "samsung,s3c2440-i2c";
 595                         reg = <0x138C0000 0x100>;
 596                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 597                         clocks = <&clock CLK_I2C6>;
 598                         clock-names = "i2c";
 599                         pinctrl-names = "default";
 600                         pinctrl-0 = <&i2c6_bus>;
 601                         status = "disabled";
 602                 };
 603
 604                 i2c_7: i2c@138d0000 {
 605                         #address-cells = <1>;
 606                         #size-cells = <0>;
 607                         compatible = "samsung,s3c2440-i2c";
 608                         reg = <0x138D0000 0x100>;
 609                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 610                         clocks = <&clock CLK_I2C7>;
 611                         clock-names = "i2c";
 612                         pinctrl-names = "default";
 613                         pinctrl-0 = <&i2c7_bus>;
 614                         status = "disabled";
 615                 };
 616
 617                 i2c_8: i2c@138e0000 {
 618                         #address-cells = <1>;
 619                         #size-cells = <0>;
 620                         compatible = "samsung,s3c2440-hdmiphy-i2c";
 621                         reg = <0x138E0000 0x100>;
 622                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 623                         clocks = <&clock CLK_I2C_HDMI>;
 624                         clock-names = "i2c";
 625                         status = "disabled";
 626
 627                         hdmi_i2c_phy: hdmiphy@38 {
 628                                 compatible = "exynos4210-hdmiphy";
 629                                 reg = <0x38>;
 630                         };
 631                 };
 632
 633                 spi_0: spi@13920000 {
 634                         compatible = "samsung,exynos4210-spi";
 635                         reg = <0x13920000 0x100>;
 636                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 637                         dmas = <&pdma0 7>, <&pdma0 6>;
 638                         dma-names = "tx", "rx";
 639                         #address-cells = <1>;
 640                         #size-cells = <0>;
 641                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 642                         clock-names = "spi", "spi_busclk0";
 643                         pinctrl-names = "default";
 644                         pinctrl-0 = <&spi0_bus>;
 645                         status = "disabled";
 646                 };
 647
 648                 spi_1: spi@13930000 {
 649                         compatible = "samsung,exynos4210-spi";
 650                         reg = <0x13930000 0x100>;
 651                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 652                         dmas = <&pdma1 7>, <&pdma1 6>;
 653                         dma-names = "tx", "rx";
 654                         #address-cells = <1>;
 655                         #size-cells = <0>;
 656                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 657                         clock-names = "spi", "spi_busclk0";
 658                         pinctrl-names = "default";
 659                         pinctrl-0 = <&spi1_bus>;
 660                         status = "disabled";
 661                 };
 662
 663                 spi_2: spi@13940000 {
 664                         compatible = "samsung,exynos4210-spi";
 665                         reg = <0x13940000 0x100>;
 666                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 667                         dmas = <&pdma0 9>, <&pdma0 8>;
 668                         dma-names = "tx", "rx";
 669                         #address-cells = <1>;
 670                         #size-cells = <0>;
 671                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 672                         clock-names = "spi", "spi_busclk0";
 673                         pinctrl-names = "default";
 674                         pinctrl-0 = <&spi2_bus>;
 675                         status = "disabled";
 676                 };
 677
 678                 pwm: pwm@139d0000 {
 679                         compatible = "samsung,exynos4210-pwm";
 680                         reg = <0x139D0000 0x1000>;
 681                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 682                                      <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
 683                                      <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 684                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 685                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 686                         clocks = <&clock CLK_PWM>;
 687                         clock-names = "timers";
 688                         #pwm-cells = <3>;
 689                         status = "disabled";
 690                 };
 691
 692                 amba: amba {
 693                         #address-cells = <1>;
 694                         #size-cells = <1>;
 695                         compatible = "simple-bus";
 696                         interrupt-parent = <&gic>;
 697                         ranges;
 698
 699                         pdma0: pdma@12680000 {
 700                                 compatible = "arm,pl330", "arm,primecell";
 701                                 reg = <0x12680000 0x1000>;
 702                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 703                                 clocks = <&clock CLK_PDMA0>;
 704                                 clock-names = "apb_pclk";
 705                                 #dma-cells = <1>;
 706                                 #dma-channels = <8>;
 707                                 #dma-requests = <32>;
 708                         };
 709
 710                         pdma1: pdma@12690000 {
 711                                 compatible = "arm,pl330", "arm,primecell";
 712                                 reg = <0x12690000 0x1000>;
 713                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 714                                 clocks = <&clock CLK_PDMA1>;
 715                                 clock-names = "apb_pclk";
 716                                 #dma-cells = <1>;
 717                                 #dma-channels = <8>;
 718                                 #dma-requests = <32>;
 719                         };
 720
 721                         mdma1: mdma@12850000 {
 722                                 compatible = "arm,pl330", "arm,primecell";
 723                                 reg = <0x12850000 0x1000>;
 724                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 725                                 clocks = <&clock CLK_MDMA>;
 726                                 clock-names = "apb_pclk";
 727                                 #dma-cells = <1>;
 728                                 #dma-channels = <8>;
 729                                 #dma-requests = <1>;
 730                         };
 731                 };
 732
 733                 fimd: fimd@11c00000 {
 734                         compatible = "samsung,exynos4210-fimd";
 735                         interrupt-parent = <&combiner>;
 736                         reg = <0x11c00000 0x20000>;
 737                         interrupt-names = "fifo", "vsync", "lcd_sys";
 738                         interrupts = <11 0>, <11 1>, <11 2>;
 739                         clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
 740                         clock-names = "sclk_fimd", "fimd";
 741                         power-domains = <&pd_lcd0>;
 742                         iommus = <&sysmmu_fimd0>;
 743                         samsung,sysreg = <&sys_reg>;
 744                         status = "disabled";
 745                 };
 746
 747                 tmu: tmu@100c0000 {
 748                         interrupt-parent = <&combiner>;
 749                         reg = <0x100C0000 0x100>;
 750                         interrupts = <2 4>;
 751                         status = "disabled";
 752                         #thermal-sensor-cells = <0>;
 753                 };
 754
 755                 jpeg_codec: jpeg-codec@11840000 {
 756                         compatible = "samsung,exynos4210-jpeg";
 757                         reg = <0x11840000 0x1000>;
 758                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 759                         clocks = <&clock CLK_JPEG>;
 760                         clock-names = "jpeg";
 761                         power-domains = <&pd_cam>;
 762                         iommus = <&sysmmu_jpeg>;
 763                 };
 764
 765                 rotator: rotator@12810000 {
 766                         compatible = "samsung,exynos4210-rotator";
 767                         reg = <0x12810000 0x64>;
 768                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 769                         clocks = <&clock CLK_ROTATOR>;
 770                         clock-names = "rotator";
 771                         iommus = <&sysmmu_rotator>;
 772                 };
 773
 774                 hdmi: hdmi@12d00000 {
 775                         compatible = "samsung,exynos4210-hdmi";
 776                         reg = <0x12D00000 0x70000>;
 777                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 778                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 779                                       "sclk_hdmiphy", "mout_hdmi";
 780                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 781                                  <&clock CLK_SCLK_PIXEL>,
 782                                  <&clock CLK_SCLK_HDMIPHY>,
 783                                  <&clock CLK_MOUT_HDMI>;
 784                         phy = <&hdmi_i2c_phy>;
 785                         power-domains = <&pd_tv>;
 786                         samsung,syscon-phandle = <&pmu_system_controller>;
 787                         #sound-dai-cells = <0>;
 788                         status = "disabled";
 789                 };
 790
 791                 hdmicec: cec@100b0000 {
 792                         compatible = "samsung,s5p-cec";
 793                         reg = <0x100B0000 0x200>;
 794                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 795                         clocks = <&clock CLK_HDMI_CEC>;
 796                         clock-names = "hdmicec";
 797                         samsung,syscon-phandle = <&pmu_system_controller>;
 798                         hdmi-phandle = <&hdmi>;
 799                         pinctrl-names = "default";
 800                         pinctrl-0 = <&hdmi_cec>;
 801                         status = "disabled";
 802                 };
 803
 804                 mixer: mixer@12c10000 {
 805                         compatible = "samsung,exynos4210-mixer";
 806                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 807                         reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
 808                         power-domains = <&pd_tv>;
 809                         iommus = <&sysmmu_tv>;
 810                         status = "disabled";
 811                 };
 812
 813                 ppmu_dmc0: ppmu_dmc0@106a0000 {
 814                         compatible = "samsung,exynos-ppmu";
 815                         reg = <0x106a0000 0x2000>;
 816                         clocks = <&clock CLK_PPMUDMC0>;
 817                         clock-names = "ppmu";
 818                         status = "disabled";
 819                 };
 820
 821                 ppmu_dmc1: ppmu_dmc1@106b0000 {
 822                         compatible = "samsung,exynos-ppmu";
 823                         reg = <0x106b0000 0x2000>;
 824                         clocks = <&clock CLK_PPMUDMC1>;
 825                         clock-names = "ppmu";
 826                         status = "disabled";
 827                 };
 828
 829                 ppmu_cpu: ppmu_cpu@106c0000 {
 830                         compatible = "samsung,exynos-ppmu";
 831                         reg = <0x106c0000 0x2000>;
 832                         clocks = <&clock CLK_PPMUCPU>;
 833                         clock-names = "ppmu";
 834                         status = "disabled";
 835                 };
 836
 837                 ppmu_rightbus: ppmu_rightbus@112a0000 {
 838                         compatible = "samsung,exynos-ppmu";
 839                         reg = <0x112a0000 0x2000>;
 840                         clocks = <&clock CLK_PPMURIGHT>;
 841                         clock-names = "ppmu";
 842                         status = "disabled";
 843                 };
 844
 845                 ppmu_leftbus: ppmu_leftbus0@116a0000 {
 846                         compatible = "samsung,exynos-ppmu";
 847                         reg = <0x116a0000 0x2000>;
 848                         clocks = <&clock CLK_PPMULEFT>;
 849                         clock-names = "ppmu";
 850                         status = "disabled";
 851                 };
 852
 853                 ppmu_camif: ppmu_camif@11ac0000 {
 854                         compatible = "samsung,exynos-ppmu";
 855                         reg = <0x11ac0000 0x2000>;
 856                         clocks = <&clock CLK_PPMUCAMIF>;
 857                         clock-names = "ppmu";
 858                         status = "disabled";
 859                 };
 860
 861                 ppmu_lcd0: ppmu_lcd0@11e40000 {
 862                         compatible = "samsung,exynos-ppmu";
 863                         reg = <0x11e40000 0x2000>;
 864                         clocks = <&clock CLK_PPMULCD0>;
 865                         clock-names = "ppmu";
 866                         status = "disabled";
 867                 };
 868
 869                 ppmu_fsys: ppmu_g3d@12630000 {
 870                         compatible = "samsung,exynos-ppmu";
 871                         reg = <0x12630000 0x2000>;
 872                         status = "disabled";
 873                 };
 874
 875                 ppmu_image: ppmu_image@12aa0000 {
 876                         compatible = "samsung,exynos-ppmu";
 877                         reg = <0x12aa0000 0x2000>;
 878                         clocks = <&clock CLK_PPMUIMAGE>;
 879                         clock-names = "ppmu";
 880                         status = "disabled";
 881                 };
 882
 883                 ppmu_tv: ppmu_tv@12e40000 {
 884                         compatible = "samsung,exynos-ppmu";
 885                         reg = <0x12e40000 0x2000>;
 886                         clocks = <&clock CLK_PPMUTV>;
 887                         clock-names = "ppmu";
 888                         status = "disabled";
 889                 };
 890
 891                 ppmu_g3d: ppmu_g3d@13220000 {
 892                         compatible = "samsung,exynos-ppmu";
 893                         reg = <0x13220000 0x2000>;
 894                         clocks = <&clock CLK_PPMUG3D>;
 895                         clock-names = "ppmu";
 896                         status = "disabled";
 897                 };
 898
 899                 ppmu_mfc_left: ppmu_mfc_left@13660000 {
 900                         compatible = "samsung,exynos-ppmu";
 901                         reg = <0x13660000 0x2000>;
 902                         clocks = <&clock CLK_PPMUMFC_L>;
 903                         clock-names = "ppmu";
 904                         status = "disabled";
 905                 };
 906
 907                 ppmu_mfc_right: ppmu_mfc_right@13670000 {
 908                         compatible = "samsung,exynos-ppmu";
 909                         reg = <0x13670000 0x2000>;
 910                         clocks = <&clock CLK_PPMUMFC_R>;
 911                         clock-names = "ppmu";
 912                         status = "disabled";
 913                 };
 914
 915                 sysmmu_mfc_l: sysmmu@13620000 {
 916                         compatible = "samsung,exynos-sysmmu";
 917                         reg = <0x13620000 0x1000>;
 918                         interrupt-parent = <&combiner>;
 919                         interrupts = <5 5>;
 920                         clock-names = "sysmmu", "master";
 921                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 922                         power-domains = <&pd_mfc>;
 923                         #iommu-cells = <0>;
 924                 };
 925
 926                 sysmmu_mfc_r: sysmmu@13630000 {
 927                         compatible = "samsung,exynos-sysmmu";
 928                         reg = <0x13630000 0x1000>;
 929                         interrupt-parent = <&combiner>;
 930                         interrupts = <5 6>;
 931                         clock-names = "sysmmu", "master";
 932                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 933                         power-domains = <&pd_mfc>;
 934                         #iommu-cells = <0>;
 935                 };
 936
 937                 sysmmu_tv: sysmmu@12e20000 {
 938                         compatible = "samsung,exynos-sysmmu";
 939                         reg = <0x12E20000 0x1000>;
 940                         interrupt-parent = <&combiner>;
 941                         interrupts = <5 4>;
 942                         clock-names = "sysmmu", "master";
 943                         clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
 944                         power-domains = <&pd_tv>;
 945                         #iommu-cells = <0>;
 946                 };
 947
 948                 sysmmu_fimc0: sysmmu@11a20000 {
 949                         compatible = "samsung,exynos-sysmmu";
 950                         reg = <0x11A20000 0x1000>;
 951                         interrupt-parent = <&combiner>;
 952                         interrupts = <4 2>;
 953                         clock-names = "sysmmu", "master";
 954                         clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
 955                         power-domains = <&pd_cam>;
 956                         #iommu-cells = <0>;
 957                 };
 958
 959                 sysmmu_fimc1: sysmmu@11a30000 {
 960                         compatible = "samsung,exynos-sysmmu";
 961                         reg = <0x11A30000 0x1000>;
 962                         interrupt-parent = <&combiner>;
 963                         interrupts = <4 3>;
 964                         clock-names = "sysmmu", "master";
 965                         clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
 966                         power-domains = <&pd_cam>;
 967                         #iommu-cells = <0>;
 968                 };
 969
 970                 sysmmu_fimc2: sysmmu@11a40000 {
 971                         compatible = "samsung,exynos-sysmmu";
 972                         reg = <0x11A40000 0x1000>;
 973                         interrupt-parent = <&combiner>;
 974                         interrupts = <4 4>;
 975                         clock-names = "sysmmu", "master";
 976                         clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
 977                         power-domains = <&pd_cam>;
 978                         #iommu-cells = <0>;
 979                 };
 980
 981                 sysmmu_fimc3: sysmmu@11a50000 {
 982                         compatible = "samsung,exynos-sysmmu";
 983                         reg = <0x11A50000 0x1000>;
 984                         interrupt-parent = <&combiner>;
 985                         interrupts = <4 5>;
 986                         clock-names = "sysmmu", "master";
 987                         clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
 988                         power-domains = <&pd_cam>;
 989                         #iommu-cells = <0>;
 990                 };
 991
 992                 sysmmu_jpeg: sysmmu@11a60000 {
 993                         compatible = "samsung,exynos-sysmmu";
 994                         reg = <0x11A60000 0x1000>;
 995                         interrupt-parent = <&combiner>;
 996                         interrupts = <4 6>;
 997                         clock-names = "sysmmu", "master";
 998                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 999                         power-domains = <&pd_cam>;
1000                         #iommu-cells = <0>;
1001                 };
1002
1003                 sysmmu_rotator: sysmmu@12a30000 {
1004                         compatible = "samsung,exynos-sysmmu";
1005                         reg = <0x12A30000 0x1000>;
1006                         interrupt-parent = <&combiner>;
1007                         interrupts = <5 0>;
1008                         clock-names = "sysmmu", "master";
1009                         clocks = <&clock CLK_SMMU_ROTATOR>,
1010                                  <&clock CLK_ROTATOR>;
1011                         #iommu-cells = <0>;
1012                 };
1013
1014                 sysmmu_fimd0: sysmmu@11e20000 {
1015                         compatible = "samsung,exynos-sysmmu";
1016                         reg = <0x11E20000 0x1000>;
1017                         interrupt-parent = <&combiner>;
1018                         interrupts = <5 2>;
1019                         clock-names = "sysmmu", "master";
1020                         clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
1021                         power-domains = <&pd_lcd0>;
1022                         #iommu-cells = <0>;
1023                 };
1024
1025                 sss: sss@10830000 {
1026                         compatible = "samsung,exynos4210-secss";
1027                         reg = <0x10830000 0x300>;
1028                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1029                         clocks = <&clock CLK_SSS>;
1030                         clock-names = "secss";
1031                 };
1032
1033                 prng: rng@10830400 {
1034                         compatible = "samsung,exynos4-rng";
1035                         reg = <0x10830400 0x200>;
1036                         clocks = <&clock CLK_SSS>;
1037                         clock-names = "secss";
1038                 };
1039         };
1040 };
1041
1042 #include "exynos-syscon-restart.dtsi"