arch/arm/boot/dts/dra7xx-clocks.dtsi

   1 /*
   2  * Device Tree Source for DRA7xx clock data
   3  *
   4  * Copyright (C) 2013 Texas Instruments, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 &cm_core_aon_clocks {
  11         atl_clkin0_ck: atl_clkin0_ck {
  12                 #clock-cells = <0>;
  13                 compatible = "fixed-clock";
  14                 clock-frequency = <0>;
  15         };
  16
  17         atl_clkin1_ck: atl_clkin1_ck {
  18                 #clock-cells = <0>;
  19                 compatible = "fixed-clock";
  20                 clock-frequency = <0>;
  21         };
  22
  23         atl_clkin2_ck: atl_clkin2_ck {
  24                 #clock-cells = <0>;
  25                 compatible = "fixed-clock";
  26                 clock-frequency = <0>;
  27         };
  28
  29         atlclkin3_ck: atlclkin3_ck {
  30                 #clock-cells = <0>;
  31                 compatible = "fixed-clock";
  32                 clock-frequency = <0>;
  33         };
  34
  35         hdmi_clkin_ck: hdmi_clkin_ck {
  36                 #clock-cells = <0>;
  37                 compatible = "fixed-clock";
  38                 clock-frequency = <0>;
  39         };
  40
  41         mlb_clkin_ck: mlb_clkin_ck {
  42                 #clock-cells = <0>;
  43                 compatible = "fixed-clock";
  44                 clock-frequency = <0>;
  45         };
  46
  47         mlbp_clkin_ck: mlbp_clkin_ck {
  48                 #clock-cells = <0>;
  49                 compatible = "fixed-clock";
  50                 clock-frequency = <0>;
  51         };
  52
  53         pciesref_acs_clk_ck: pciesref_acs_clk_ck {
  54                 #clock-cells = <0>;
  55                 compatible = "fixed-clock";
  56                 clock-frequency = <100000000>;
  57         };
  58
  59         ref_clkin0_ck: ref_clkin0_ck {
  60                 #clock-cells = <0>;
  61                 compatible = "fixed-clock";
  62                 clock-frequency = <0>;
  63         };
  64
  65         ref_clkin1_ck: ref_clkin1_ck {
  66                 #clock-cells = <0>;
  67                 compatible = "fixed-clock";
  68                 clock-frequency = <0>;
  69         };
  70
  71         ref_clkin2_ck: ref_clkin2_ck {
  72                 #clock-cells = <0>;
  73                 compatible = "fixed-clock";
  74                 clock-frequency = <0>;
  75         };
  76
  77         ref_clkin3_ck: ref_clkin3_ck {
  78                 #clock-cells = <0>;
  79                 compatible = "fixed-clock";
  80                 clock-frequency = <0>;
  81         };
  82
  83         rmii_clk_ck: rmii_clk_ck {
  84                 #clock-cells = <0>;
  85                 compatible = "fixed-clock";
  86                 clock-frequency = <0>;
  87         };
  88
  89         sdvenc_clkin_ck: sdvenc_clkin_ck {
  90                 #clock-cells = <0>;
  91                 compatible = "fixed-clock";
  92                 clock-frequency = <0>;
  93         };
  94
  95         secure_32k_clk_src_ck: secure_32k_clk_src_ck {
  96                 #clock-cells = <0>;
  97                 compatible = "fixed-clock";
  98                 clock-frequency = <32768>;
  99         };
 100
 101         sys_32k_ck: sys_32k_ck {
 102                 #clock-cells = <0>;
 103                 compatible = "fixed-clock";
 104                 clock-frequency = <32768>;
 105         };
 106
 107         virt_12000000_ck: virt_12000000_ck {
 108                 #clock-cells = <0>;
 109                 compatible = "fixed-clock";
 110                 clock-frequency = <12000000>;
 111         };
 112
 113         virt_13000000_ck: virt_13000000_ck {
 114                 #clock-cells = <0>;
 115                 compatible = "fixed-clock";
 116                 clock-frequency = <13000000>;
 117         };
 118
 119         virt_16800000_ck: virt_16800000_ck {
 120                 #clock-cells = <0>;
 121                 compatible = "fixed-clock";
 122                 clock-frequency = <16800000>;
 123         };
 124
 125         virt_19200000_ck: virt_19200000_ck {
 126                 #clock-cells = <0>;
 127                 compatible = "fixed-clock";
 128                 clock-frequency = <19200000>;
 129         };
 130
 131         virt_20000000_ck: virt_20000000_ck {
 132                 #clock-cells = <0>;
 133                 compatible = "fixed-clock";
 134                 clock-frequency = <20000000>;
 135         };
 136
 137         virt_26000000_ck: virt_26000000_ck {
 138                 #clock-cells = <0>;
 139                 compatible = "fixed-clock";
 140                 clock-frequency = <26000000>;
 141         };
 142
 143         virt_27000000_ck: virt_27000000_ck {
 144                 #clock-cells = <0>;
 145                 compatible = "fixed-clock";
 146                 clock-frequency = <27000000>;
 147         };
 148
 149         virt_38400000_ck: virt_38400000_ck {
 150                 #clock-cells = <0>;
 151                 compatible = "fixed-clock";
 152                 clock-frequency = <38400000>;
 153         };
 154
 155         sys_clkin2: sys_clkin2 {
 156                 #clock-cells = <0>;
 157                 compatible = "fixed-clock";
 158                 clock-frequency = <22579200>;
 159         };
 160
 161         usb_otg_clkin_ck: usb_otg_clkin_ck {
 162                 #clock-cells = <0>;
 163                 compatible = "fixed-clock";
 164                 clock-frequency = <0>;
 165         };
 166
 167         video1_clkin_ck: video1_clkin_ck {
 168                 #clock-cells = <0>;
 169                 compatible = "fixed-clock";
 170                 clock-frequency = <0>;
 171         };
 172
 173         video1_m2_clkin_ck: video1_m2_clkin_ck {
 174                 #clock-cells = <0>;
 175                 compatible = "fixed-clock";
 176                 clock-frequency = <0>;
 177         };
 178
 179         video2_clkin_ck: video2_clkin_ck {
 180                 #clock-cells = <0>;
 181                 compatible = "fixed-clock";
 182                 clock-frequency = <0>;
 183         };
 184
 185         video2_m2_clkin_ck: video2_m2_clkin_ck {
 186                 #clock-cells = <0>;
 187                 compatible = "fixed-clock";
 188                 clock-frequency = <0>;
 189         };
 190
 191         dpll_abe_ck: dpll_abe_ck {
 192                 #clock-cells = <0>;
 193                 compatible = "ti,omap4-dpll-m4xen-clock";
 194                 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
 195                 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
 196         };
 197
 198         dpll_abe_x2_ck: dpll_abe_x2_ck {
 199                 #clock-cells = <0>;
 200                 compatible = "ti,omap4-dpll-x2-clock";
 201                 clocks = <&dpll_abe_ck>;
 202         };
 203
 204         dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
 205                 #clock-cells = <0>;
 206                 compatible = "ti,divider-clock";
 207                 clocks = <&dpll_abe_x2_ck>;
 208                 ti,max-div = <31>;
 209                 ti,autoidle-shift = <8>;
 210                 reg = <0x01f0>;
 211                 ti,index-starts-at-one;
 212                 ti,invert-autoidle-bit;
 213         };
 214
 215         abe_clk: abe_clk {
 216                 #clock-cells = <0>;
 217                 compatible = "ti,divider-clock";
 218                 clocks = <&dpll_abe_m2x2_ck>;
 219                 ti,max-div = <4>;
 220                 reg = <0x0108>;
 221                 ti,index-power-of-two;
 222         };
 223
 224         dpll_abe_m2_ck: dpll_abe_m2_ck {
 225                 #clock-cells = <0>;
 226                 compatible = "ti,divider-clock";
 227                 clocks = <&dpll_abe_ck>;
 228                 ti,max-div = <31>;
 229                 ti,autoidle-shift = <8>;
 230                 reg = <0x01f0>;
 231                 ti,index-starts-at-one;
 232                 ti,invert-autoidle-bit;
 233         };
 234
 235         dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
 236                 #clock-cells = <0>;
 237                 compatible = "ti,divider-clock";
 238                 clocks = <&dpll_abe_x2_ck>;
 239                 ti,max-div = <31>;
 240                 ti,autoidle-shift = <8>;
 241                 reg = <0x01f4>;
 242                 ti,index-starts-at-one;
 243                 ti,invert-autoidle-bit;
 244         };
 245
 246         dpll_core_byp_mux: dpll_core_byp_mux {
 247                 #clock-cells = <0>;
 248                 compatible = "ti,mux-clock";
 249                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 250                 ti,bit-shift = <23>;
 251                 reg = <0x012c>;
 252         };
 253
 254         dpll_core_ck: dpll_core_ck {
 255                 #clock-cells = <0>;
 256                 compatible = "ti,omap4-dpll-core-clock";
 257                 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
 258                 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 259         };
 260
 261         dpll_core_x2_ck: dpll_core_x2_ck {
 262                 #clock-cells = <0>;
 263                 compatible = "ti,omap4-dpll-x2-clock";
 264                 clocks = <&dpll_core_ck>;
 265         };
 266
 267         dpll_core_h12x2_ck: dpll_core_h12x2_ck {
 268                 #clock-cells = <0>;
 269                 compatible = "ti,divider-clock";
 270                 clocks = <&dpll_core_x2_ck>;
 271                 ti,max-div = <63>;
 272                 ti,autoidle-shift = <8>;
 273                 reg = <0x013c>;
 274                 ti,index-starts-at-one;
 275                 ti,invert-autoidle-bit;
 276         };
 277
 278         mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
 279                 #clock-cells = <0>;
 280                 compatible = "fixed-factor-clock";
 281                 clocks = <&dpll_core_h12x2_ck>;
 282                 clock-mult = <1>;
 283                 clock-div = <1>;
 284         };
 285
 286         dpll_mpu_ck: dpll_mpu_ck {
 287                 #clock-cells = <0>;
 288                 compatible = "ti,omap4-dpll-clock";
 289                 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
 290                 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 291         };
 292
 293         dpll_mpu_m2_ck: dpll_mpu_m2_ck {
 294                 #clock-cells = <0>;
 295                 compatible = "ti,divider-clock";
 296                 clocks = <&dpll_mpu_ck>;
 297                 ti,max-div = <31>;
 298                 ti,autoidle-shift = <8>;
 299                 reg = <0x0170>;
 300                 ti,index-starts-at-one;
 301                 ti,invert-autoidle-bit;
 302         };
 303
 304         mpu_dclk_div: mpu_dclk_div {
 305                 #clock-cells = <0>;
 306                 compatible = "fixed-factor-clock";
 307                 clocks = <&dpll_mpu_m2_ck>;
 308                 clock-mult = <1>;
 309                 clock-div = <1>;
 310         };
 311
 312         dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
 313                 #clock-cells = <0>;
 314                 compatible = "fixed-factor-clock";
 315                 clocks = <&dpll_core_h12x2_ck>;
 316                 clock-mult = <1>;
 317                 clock-div = <1>;
 318         };
 319
 320         dpll_dsp_byp_mux: dpll_dsp_byp_mux {
 321                 #clock-cells = <0>;
 322                 compatible = "ti,mux-clock";
 323                 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
 324                 ti,bit-shift = <23>;
 325                 reg = <0x0240>;
 326         };
 327
 328         dpll_dsp_ck: dpll_dsp_ck {
 329                 #clock-cells = <0>;
 330                 compatible = "ti,omap4-dpll-clock";
 331                 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
 332                 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
 333         };
 334
 335         dpll_dsp_m2_ck: dpll_dsp_m2_ck {
 336                 #clock-cells = <0>;
 337                 compatible = "ti,divider-clock";
 338                 clocks = <&dpll_dsp_ck>;
 339                 ti,max-div = <31>;
 340                 ti,autoidle-shift = <8>;
 341                 reg = <0x0244>;
 342                 ti,index-starts-at-one;
 343                 ti,invert-autoidle-bit;
 344         };
 345
 346         iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
 347                 #clock-cells = <0>;
 348                 compatible = "fixed-factor-clock";
 349                 clocks = <&dpll_core_h12x2_ck>;
 350                 clock-mult = <1>;
 351                 clock-div = <1>;
 352         };
 353
 354         dpll_iva_byp_mux: dpll_iva_byp_mux {
 355                 #clock-cells = <0>;
 356                 compatible = "ti,mux-clock";
 357                 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
 358                 ti,bit-shift = <23>;
 359                 reg = <0x01ac>;
 360         };
 361
 362         dpll_iva_ck: dpll_iva_ck {
 363                 #clock-cells = <0>;
 364                 compatible = "ti,omap4-dpll-clock";
 365                 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
 366                 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 367         };
 368
 369         dpll_iva_m2_ck: dpll_iva_m2_ck {
 370                 #clock-cells = <0>;
 371                 compatible = "ti,divider-clock";
 372                 clocks = <&dpll_iva_ck>;
 373                 ti,max-div = <31>;
 374                 ti,autoidle-shift = <8>;
 375                 reg = <0x01b0>;
 376                 ti,index-starts-at-one;
 377                 ti,invert-autoidle-bit;
 378         };
 379
 380         iva_dclk: iva_dclk {
 381                 #clock-cells = <0>;
 382                 compatible = "fixed-factor-clock";
 383                 clocks = <&dpll_iva_m2_ck>;
 384                 clock-mult = <1>;
 385                 clock-div = <1>;
 386         };
 387
 388         dpll_gpu_byp_mux: dpll_gpu_byp_mux {
 389                 #clock-cells = <0>;
 390                 compatible = "ti,mux-clock";
 391                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 392                 ti,bit-shift = <23>;
 393                 reg = <0x02e4>;
 394         };
 395
 396         dpll_gpu_ck: dpll_gpu_ck {
 397                 #clock-cells = <0>;
 398                 compatible = "ti,omap4-dpll-clock";
 399                 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
 400                 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
 401         };
 402
 403         dpll_gpu_m2_ck: dpll_gpu_m2_ck {
 404                 #clock-cells = <0>;
 405                 compatible = "ti,divider-clock";
 406                 clocks = <&dpll_gpu_ck>;
 407                 ti,max-div = <31>;
 408                 ti,autoidle-shift = <8>;
 409                 reg = <0x02e8>;
 410                 ti,index-starts-at-one;
 411                 ti,invert-autoidle-bit;
 412         };
 413
 414         dpll_core_m2_ck: dpll_core_m2_ck {
 415                 #clock-cells = <0>;
 416                 compatible = "ti,divider-clock";
 417                 clocks = <&dpll_core_ck>;
 418                 ti,max-div = <31>;
 419                 ti,autoidle-shift = <8>;
 420                 reg = <0x0130>;
 421                 ti,index-starts-at-one;
 422                 ti,invert-autoidle-bit;
 423         };
 424
 425         core_dpll_out_dclk_div: core_dpll_out_dclk_div {
 426                 #clock-cells = <0>;
 427                 compatible = "fixed-factor-clock";
 428                 clocks = <&dpll_core_m2_ck>;
 429                 clock-mult = <1>;
 430                 clock-div = <1>;
 431         };
 432
 433         dpll_ddr_byp_mux: dpll_ddr_byp_mux {
 434                 #clock-cells = <0>;
 435                 compatible = "ti,mux-clock";
 436                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 437                 ti,bit-shift = <23>;
 438                 reg = <0x021c>;
 439         };
 440
 441         dpll_ddr_ck: dpll_ddr_ck {
 442                 #clock-cells = <0>;
 443                 compatible = "ti,omap4-dpll-clock";
 444                 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
 445                 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
 446         };
 447
 448         dpll_ddr_m2_ck: dpll_ddr_m2_ck {
 449                 #clock-cells = <0>;
 450                 compatible = "ti,divider-clock";
 451                 clocks = <&dpll_ddr_ck>;
 452                 ti,max-div = <31>;
 453                 ti,autoidle-shift = <8>;
 454                 reg = <0x0220>;
 455                 ti,index-starts-at-one;
 456                 ti,invert-autoidle-bit;
 457         };
 458
 459         dpll_gmac_byp_mux: dpll_gmac_byp_mux {
 460                 #clock-cells = <0>;
 461                 compatible = "ti,mux-clock";
 462                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 463                 ti,bit-shift = <23>;
 464                 reg = <0x02b4>;
 465         };
 466
 467         dpll_gmac_ck: dpll_gmac_ck {
 468                 #clock-cells = <0>;
 469                 compatible = "ti,omap4-dpll-clock";
 470                 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
 471                 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
 472         };
 473
 474         dpll_gmac_m2_ck: dpll_gmac_m2_ck {
 475                 #clock-cells = <0>;
 476                 compatible = "ti,divider-clock";
 477                 clocks = <&dpll_gmac_ck>;
 478                 ti,max-div = <31>;
 479                 ti,autoidle-shift = <8>;
 480                 reg = <0x02b8>;
 481                 ti,index-starts-at-one;
 482                 ti,invert-autoidle-bit;
 483         };
 484
 485         video2_dclk_div: video2_dclk_div {
 486                 #clock-cells = <0>;
 487                 compatible = "fixed-factor-clock";
 488                 clocks = <&video2_m2_clkin_ck>;
 489                 clock-mult = <1>;
 490                 clock-div = <1>;
 491         };
 492
 493         video1_dclk_div: video1_dclk_div {
 494                 #clock-cells = <0>;
 495                 compatible = "fixed-factor-clock";
 496                 clocks = <&video1_m2_clkin_ck>;
 497                 clock-mult = <1>;
 498                 clock-div = <1>;
 499         };
 500
 501         hdmi_dclk_div: hdmi_dclk_div {
 502                 #clock-cells = <0>;
 503                 compatible = "fixed-factor-clock";
 504                 clocks = <&hdmi_clkin_ck>;
 505                 clock-mult = <1>;
 506                 clock-div = <1>;
 507         };
 508
 509         per_dpll_hs_clk_div: per_dpll_hs_clk_div {
 510                 #clock-cells = <0>;
 511                 compatible = "fixed-factor-clock";
 512                 clocks = <&dpll_abe_m3x2_ck>;
 513                 clock-mult = <1>;
 514                 clock-div = <2>;
 515         };
 516
 517         usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
 518                 #clock-cells = <0>;
 519                 compatible = "fixed-factor-clock";
 520                 clocks = <&dpll_abe_m3x2_ck>;
 521                 clock-mult = <1>;
 522                 clock-div = <3>;
 523         };
 524
 525         eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
 526                 #clock-cells = <0>;
 527                 compatible = "fixed-factor-clock";
 528                 clocks = <&dpll_core_h12x2_ck>;
 529                 clock-mult = <1>;
 530                 clock-div = <1>;
 531         };
 532
 533         dpll_eve_byp_mux: dpll_eve_byp_mux {
 534                 #clock-cells = <0>;
 535                 compatible = "ti,mux-clock";
 536                 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
 537                 ti,bit-shift = <23>;
 538                 reg = <0x0290>;
 539         };
 540
 541         dpll_eve_ck: dpll_eve_ck {
 542                 #clock-cells = <0>;
 543                 compatible = "ti,omap4-dpll-clock";
 544                 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
 545                 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
 546         };
 547
 548         dpll_eve_m2_ck: dpll_eve_m2_ck {
 549                 #clock-cells = <0>;
 550                 compatible = "ti,divider-clock";
 551                 clocks = <&dpll_eve_ck>;
 552                 ti,max-div = <31>;
 553                 ti,autoidle-shift = <8>;
 554                 reg = <0x0294>;
 555                 ti,index-starts-at-one;
 556                 ti,invert-autoidle-bit;
 557         };
 558
 559         eve_dclk_div: eve_dclk_div {
 560                 #clock-cells = <0>;
 561                 compatible = "fixed-factor-clock";
 562                 clocks = <&dpll_eve_m2_ck>;
 563                 clock-mult = <1>;
 564                 clock-div = <1>;
 565         };
 566
 567         dpll_core_h13x2_ck: dpll_core_h13x2_ck {
 568                 #clock-cells = <0>;
 569                 compatible = "ti,divider-clock";
 570                 clocks = <&dpll_core_x2_ck>;
 571                 ti,max-div = <63>;
 572                 ti,autoidle-shift = <8>;
 573                 reg = <0x0140>;
 574                 ti,index-starts-at-one;
 575                 ti,invert-autoidle-bit;
 576         };
 577
 578         dpll_core_h14x2_ck: dpll_core_h14x2_ck {
 579                 #clock-cells = <0>;
 580                 compatible = "ti,divider-clock";
 581                 clocks = <&dpll_core_x2_ck>;
 582                 ti,max-div = <63>;
 583                 ti,autoidle-shift = <8>;
 584                 reg = <0x0144>;
 585                 ti,index-starts-at-one;
 586                 ti,invert-autoidle-bit;
 587         };
 588
 589         dpll_core_h22x2_ck: dpll_core_h22x2_ck {
 590                 #clock-cells = <0>;
 591                 compatible = "ti,divider-clock";
 592                 clocks = <&dpll_core_x2_ck>;
 593                 ti,max-div = <63>;
 594                 ti,autoidle-shift = <8>;
 595                 reg = <0x0154>;
 596                 ti,index-starts-at-one;
 597                 ti,invert-autoidle-bit;
 598         };
 599
 600         dpll_core_h23x2_ck: dpll_core_h23x2_ck {
 601                 #clock-cells = <0>;
 602                 compatible = "ti,divider-clock";
 603                 clocks = <&dpll_core_x2_ck>;
 604                 ti,max-div = <63>;
 605                 ti,autoidle-shift = <8>;
 606                 reg = <0x0158>;
 607                 ti,index-starts-at-one;
 608                 ti,invert-autoidle-bit;
 609         };
 610
 611         dpll_core_h24x2_ck: dpll_core_h24x2_ck {
 612                 #clock-cells = <0>;
 613                 compatible = "ti,divider-clock";
 614                 clocks = <&dpll_core_x2_ck>;
 615                 ti,max-div = <63>;
 616                 ti,autoidle-shift = <8>;
 617                 reg = <0x015c>;
 618                 ti,index-starts-at-one;
 619                 ti,invert-autoidle-bit;
 620         };
 621
 622         dpll_ddr_x2_ck: dpll_ddr_x2_ck {
 623                 #clock-cells = <0>;
 624                 compatible = "ti,omap4-dpll-x2-clock";
 625                 clocks = <&dpll_ddr_ck>;
 626         };
 627
 628         dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
 629                 #clock-cells = <0>;
 630                 compatible = "ti,divider-clock";
 631                 clocks = <&dpll_ddr_x2_ck>;
 632                 ti,max-div = <63>;
 633                 ti,autoidle-shift = <8>;
 634                 reg = <0x0228>;
 635                 ti,index-starts-at-one;
 636                 ti,invert-autoidle-bit;
 637         };
 638
 639         dpll_dsp_x2_ck: dpll_dsp_x2_ck {
 640                 #clock-cells = <0>;
 641                 compatible = "ti,omap4-dpll-x2-clock";
 642                 clocks = <&dpll_dsp_ck>;
 643         };
 644
 645         dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
 646                 #clock-cells = <0>;
 647                 compatible = "ti,divider-clock";
 648                 clocks = <&dpll_dsp_x2_ck>;
 649                 ti,max-div = <31>;
 650                 ti,autoidle-shift = <8>;
 651                 reg = <0x0248>;
 652                 ti,index-starts-at-one;
 653                 ti,invert-autoidle-bit;
 654         };
 655
 656         dpll_gmac_x2_ck: dpll_gmac_x2_ck {
 657                 #clock-cells = <0>;
 658                 compatible = "ti,omap4-dpll-x2-clock";
 659                 clocks = <&dpll_gmac_ck>;
 660         };
 661
 662         dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
 663                 #clock-cells = <0>;
 664                 compatible = "ti,divider-clock";
 665                 clocks = <&dpll_gmac_x2_ck>;
 666                 ti,max-div = <63>;
 667                 ti,autoidle-shift = <8>;
 668                 reg = <0x02c0>;
 669                 ti,index-starts-at-one;
 670                 ti,invert-autoidle-bit;
 671         };
 672
 673         dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
 674                 #clock-cells = <0>;
 675                 compatible = "ti,divider-clock";
 676                 clocks = <&dpll_gmac_x2_ck>;
 677                 ti,max-div = <63>;
 678                 ti,autoidle-shift = <8>;
 679                 reg = <0x02c4>;
 680                 ti,index-starts-at-one;
 681                 ti,invert-autoidle-bit;
 682         };
 683
 684         dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
 685                 #clock-cells = <0>;
 686                 compatible = "ti,divider-clock";
 687                 clocks = <&dpll_gmac_x2_ck>;
 688                 ti,max-div = <63>;
 689                 ti,autoidle-shift = <8>;
 690                 reg = <0x02c8>;
 691                 ti,index-starts-at-one;
 692                 ti,invert-autoidle-bit;
 693         };
 694
 695         dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
 696                 #clock-cells = <0>;
 697                 compatible = "ti,divider-clock";
 698                 clocks = <&dpll_gmac_x2_ck>;
 699                 ti,max-div = <31>;
 700                 ti,autoidle-shift = <8>;
 701                 reg = <0x02bc>;
 702                 ti,index-starts-at-one;
 703                 ti,invert-autoidle-bit;
 704         };
 705
 706         gmii_m_clk_div: gmii_m_clk_div {
 707                 #clock-cells = <0>;
 708                 compatible = "fixed-factor-clock";
 709                 clocks = <&dpll_gmac_h11x2_ck>;
 710                 clock-mult = <1>;
 711                 clock-div = <2>;
 712         };
 713
 714         hdmi_clk2_div: hdmi_clk2_div {
 715                 #clock-cells = <0>;
 716                 compatible = "fixed-factor-clock";
 717                 clocks = <&hdmi_clkin_ck>;
 718                 clock-mult = <1>;
 719                 clock-div = <1>;
 720         };
 721
 722         hdmi_div_clk: hdmi_div_clk {
 723                 #clock-cells = <0>;
 724                 compatible = "fixed-factor-clock";
 725                 clocks = <&hdmi_clkin_ck>;
 726                 clock-mult = <1>;
 727                 clock-div = <1>;
 728         };
 729
 730         l3_iclk_div: l3_iclk_div {
 731                 #clock-cells = <0>;
 732                 compatible = "fixed-factor-clock";
 733                 clocks = <&dpll_core_h12x2_ck>;
 734                 clock-mult = <1>;
 735                 clock-div = <1>;
 736         };
 737
 738         l4_root_clk_div: l4_root_clk_div {
 739                 #clock-cells = <0>;
 740                 compatible = "fixed-factor-clock";
 741                 clocks = <&l3_iclk_div>;
 742                 clock-mult = <1>;
 743                 clock-div = <1>;
 744         };
 745
 746         video1_clk2_div: video1_clk2_div {
 747                 #clock-cells = <0>;
 748                 compatible = "fixed-factor-clock";
 749                 clocks = <&video1_clkin_ck>;
 750                 clock-mult = <1>;
 751                 clock-div = <1>;
 752         };
 753
 754         video1_div_clk: video1_div_clk {
 755                 #clock-cells = <0>;
 756                 compatible = "fixed-factor-clock";
 757                 clocks = <&video1_clkin_ck>;
 758                 clock-mult = <1>;
 759                 clock-div = <1>;
 760         };
 761
 762         video2_clk2_div: video2_clk2_div {
 763                 #clock-cells = <0>;
 764                 compatible = "fixed-factor-clock";
 765                 clocks = <&video2_clkin_ck>;
 766                 clock-mult = <1>;
 767                 clock-div = <1>;
 768         };
 769
 770         video2_div_clk: video2_div_clk {
 771                 #clock-cells = <0>;
 772                 compatible = "fixed-factor-clock";
 773                 clocks = <&video2_clkin_ck>;
 774                 clock-mult = <1>;
 775                 clock-div = <1>;
 776         };
 777
 778         ipu1_gfclk_mux: ipu1_gfclk_mux {
 779                 #clock-cells = <0>;
 780                 compatible = "ti,mux-clock";
 781                 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
 782                 ti,bit-shift = <24>;
 783                 reg = <0x0520>;
 784         };
 785
 786         mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
 787                 #clock-cells = <0>;
 788                 compatible = "ti,mux-clock";
 789                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
 790                 ti,bit-shift = <28>;
 791                 reg = <0x0550>;
 792         };
 793
 794         mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
 795                 #clock-cells = <0>;
 796                 compatible = "ti,mux-clock";
 797                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
 798                 ti,bit-shift = <24>;
 799                 reg = <0x0550>;
 800         };
 801
 802         mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
 803                 #clock-cells = <0>;
 804                 compatible = "ti,mux-clock";
 805                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
 806                 ti,bit-shift = <22>;
 807                 reg = <0x0550>;
 808         };
 809
 810         timer5_gfclk_mux: timer5_gfclk_mux {
 811                 #clock-cells = <0>;
 812                 compatible = "ti,mux-clock";
 813                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 814                 ti,bit-shift = <24>;
 815                 reg = <0x0558>;
 816         };
 817
 818         timer6_gfclk_mux: timer6_gfclk_mux {
 819                 #clock-cells = <0>;
 820                 compatible = "ti,mux-clock";
 821                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 822                 ti,bit-shift = <24>;
 823                 reg = <0x0560>;
 824         };
 825
 826         timer7_gfclk_mux: timer7_gfclk_mux {
 827                 #clock-cells = <0>;
 828                 compatible = "ti,mux-clock";
 829                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 830                 ti,bit-shift = <24>;
 831                 reg = <0x0568>;
 832         };
 833
 834         timer8_gfclk_mux: timer8_gfclk_mux {
 835                 #clock-cells = <0>;
 836                 compatible = "ti,mux-clock";
 837                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
 838                 ti,bit-shift = <24>;
 839                 reg = <0x0570>;
 840         };
 841
 842         uart6_gfclk_mux: uart6_gfclk_mux {
 843                 #clock-cells = <0>;
 844                 compatible = "ti,mux-clock";
 845                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
 846                 ti,bit-shift = <24>;
 847                 reg = <0x0580>;
 848         };
 849
 850         dummy_ck: dummy_ck {
 851                 #clock-cells = <0>;
 852                 compatible = "fixed-clock";
 853                 clock-frequency = <0>;
 854         };
 855 };
 856 &prm_clocks {
 857         sys_clkin1: sys_clkin1 {
 858                 #clock-cells = <0>;
 859                 compatible = "ti,mux-clock";
 860                 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
 861                 reg = <0x0110>;
 862                 ti,index-starts-at-one;
 863         };
 864
 865         abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
 866                 #clock-cells = <0>;
 867                 compatible = "ti,mux-clock";
 868                 clocks = <&sys_clkin1>, <&sys_clkin2>;
 869                 reg = <0x0118>;
 870         };
 871
 872         abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
 873                 #clock-cells = <0>;
 874                 compatible = "ti,mux-clock";
 875                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 876                 reg = <0x0114>;
 877         };
 878
 879         abe_dpll_clk_mux: abe_dpll_clk_mux {
 880                 #clock-cells = <0>;
 881                 compatible = "ti,mux-clock";
 882                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 883                 reg = <0x010c>;
 884         };
 885
 886         abe_24m_fclk: abe_24m_fclk {
 887                 #clock-cells = <0>;
 888                 compatible = "ti,divider-clock";
 889                 clocks = <&dpll_abe_m2x2_ck>;
 890                 reg = <0x011c>;
 891                 ti,dividers = <8>, <16>;
 892         };
 893
 894         aess_fclk: aess_fclk {
 895                 #clock-cells = <0>;
 896                 compatible = "ti,divider-clock";
 897                 clocks = <&abe_clk>;
 898                 reg = <0x0178>;
 899                 ti,max-div = <2>;
 900         };
 901
 902         abe_giclk_div: abe_giclk_div {
 903                 #clock-cells = <0>;
 904                 compatible = "ti,divider-clock";
 905                 clocks = <&aess_fclk>;
 906                 reg = <0x0174>;
 907                 ti,max-div = <2>;
 908         };
 909
 910         abe_lp_clk_div: abe_lp_clk_div {
 911                 #clock-cells = <0>;
 912                 compatible = "ti,divider-clock";
 913                 clocks = <&dpll_abe_m2x2_ck>;
 914                 reg = <0x01d8>;
 915                 ti,dividers = <16>, <32>;
 916         };
 917
 918         abe_sys_clk_div: abe_sys_clk_div {
 919                 #clock-cells = <0>;
 920                 compatible = "ti,divider-clock";
 921                 clocks = <&sys_clkin1>;
 922                 reg = <0x0120>;
 923                 ti,max-div = <2>;
 924         };
 925
 926         adc_gfclk_mux: adc_gfclk_mux {
 927                 #clock-cells = <0>;
 928                 compatible = "ti,mux-clock";
 929                 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
 930                 reg = <0x01dc>;
 931         };
 932
 933         sys_clk1_dclk_div: sys_clk1_dclk_div {
 934                 #clock-cells = <0>;
 935                 compatible = "ti,divider-clock";
 936                 clocks = <&sys_clkin1>;
 937                 ti,max-div = <64>;
 938                 reg = <0x01c8>;
 939                 ti,index-power-of-two;
 940         };
 941
 942         sys_clk2_dclk_div: sys_clk2_dclk_div {
 943                 #clock-cells = <0>;
 944                 compatible = "ti,divider-clock";
 945                 clocks = <&sys_clkin2>;
 946                 ti,max-div = <64>;
 947                 reg = <0x01cc>;
 948                 ti,index-power-of-two;
 949         };
 950
 951         per_abe_x1_dclk_div: per_abe_x1_dclk_div {
 952                 #clock-cells = <0>;
 953                 compatible = "ti,divider-clock";
 954                 clocks = <&dpll_abe_m2_ck>;
 955                 ti,max-div = <64>;
 956                 reg = <0x01bc>;
 957                 ti,index-power-of-two;
 958         };
 959
 960         dsp_gclk_div: dsp_gclk_div {
 961                 #clock-cells = <0>;
 962                 compatible = "ti,divider-clock";
 963                 clocks = <&dpll_dsp_m2_ck>;
 964                 ti,max-div = <64>;
 965                 reg = <0x018c>;
 966                 ti,index-power-of-two;
 967         };
 968
 969         gpu_dclk: gpu_dclk {
 970                 #clock-cells = <0>;
 971                 compatible = "ti,divider-clock";
 972                 clocks = <&dpll_gpu_m2_ck>;
 973                 ti,max-div = <64>;
 974                 reg = <0x01a0>;
 975                 ti,index-power-of-two;
 976         };
 977
 978         emif_phy_dclk_div: emif_phy_dclk_div {
 979                 #clock-cells = <0>;
 980                 compatible = "ti,divider-clock";
 981                 clocks = <&dpll_ddr_m2_ck>;
 982                 ti,max-div = <64>;
 983                 reg = <0x0190>;
 984                 ti,index-power-of-two;
 985         };
 986
 987         gmac_250m_dclk_div: gmac_250m_dclk_div {
 988                 #clock-cells = <0>;
 989                 compatible = "ti,divider-clock";
 990                 clocks = <&dpll_gmac_m2_ck>;
 991                 ti,max-div = <64>;
 992                 reg = <0x019c>;
 993                 ti,index-power-of-two;
 994         };
 995
 996         l3init_480m_dclk_div: l3init_480m_dclk_div {
 997                 #clock-cells = <0>;
 998                 compatible = "ti,divider-clock";
 999                 clocks = <&dpll_usb_m2_ck>;
1000                 ti,max-div = <64>;
1001                 reg = <0x01ac>;
1002                 ti,index-power-of-two;
1003         };
1004
1005         usb_otg_dclk_div: usb_otg_dclk_div {
1006                 #clock-cells = <0>;
1007                 compatible = "ti,divider-clock";
1008                 clocks = <&usb_otg_clkin_ck>;
1009                 ti,max-div = <64>;
1010                 reg = <0x0184>;
1011                 ti,index-power-of-two;
1012         };
1013
1014         sata_dclk_div: sata_dclk_div {
1015                 #clock-cells = <0>;
1016                 compatible = "ti,divider-clock";
1017                 clocks = <&sys_clkin1>;
1018                 ti,max-div = <64>;
1019                 reg = <0x01c0>;
1020                 ti,index-power-of-two;
1021         };
1022
1023         pcie2_dclk_div: pcie2_dclk_div {
1024                 #clock-cells = <0>;
1025                 compatible = "ti,divider-clock";
1026                 clocks = <&dpll_pcie_ref_m2_ck>;
1027                 ti,max-div = <64>;
1028                 reg = <0x01b8>;
1029                 ti,index-power-of-two;
1030         };
1031
1032         pcie_dclk_div: pcie_dclk_div {
1033                 #clock-cells = <0>;
1034                 compatible = "ti,divider-clock";
1035                 clocks = <&apll_pcie_m2_ck>;
1036                 ti,max-div = <64>;
1037                 reg = <0x01b4>;
1038                 ti,index-power-of-two;
1039         };
1040
1041         emu_dclk_div: emu_dclk_div {
1042                 #clock-cells = <0>;
1043                 compatible = "ti,divider-clock";
1044                 clocks = <&sys_clkin1>;
1045                 ti,max-div = <64>;
1046                 reg = <0x0194>;
1047                 ti,index-power-of-two;
1048         };
1049
1050         secure_32k_dclk_div: secure_32k_dclk_div {
1051                 #clock-cells = <0>;
1052                 compatible = "ti,divider-clock";
1053                 clocks = <&secure_32k_clk_src_ck>;
1054                 ti,max-div = <64>;
1055                 reg = <0x01c4>;
1056                 ti,index-power-of-two;
1057         };
1058
1059         clkoutmux0_clk_mux: clkoutmux0_clk_mux {
1060                 #clock-cells = <0>;
1061                 compatible = "ti,mux-clock";
1062                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1063                 reg = <0x0158>;
1064         };
1065
1066         clkoutmux1_clk_mux: clkoutmux1_clk_mux {
1067                 #clock-cells = <0>;
1068                 compatible = "ti,mux-clock";
1069                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1070                 reg = <0x015c>;
1071         };
1072
1073         clkoutmux2_clk_mux: clkoutmux2_clk_mux {
1074                 #clock-cells = <0>;
1075                 compatible = "ti,mux-clock";
1076                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1077                 reg = <0x0160>;
1078         };
1079
1080         custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1081                 #clock-cells = <0>;
1082                 compatible = "fixed-factor-clock";
1083                 clocks = <&sys_clkin1>;
1084                 clock-mult = <1>;
1085                 clock-div = <2>;
1086         };
1087
1088         eve_clk: eve_clk {
1089                 #clock-cells = <0>;
1090                 compatible = "ti,mux-clock";
1091                 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1092                 reg = <0x0180>;
1093         };
1094
1095         hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
1096                 #clock-cells = <0>;
1097                 compatible = "ti,mux-clock";
1098                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1099                 reg = <0x01a4>;
1100         };
1101
1102         mlb_clk: mlb_clk {
1103                 #clock-cells = <0>;
1104                 compatible = "ti,divider-clock";
1105                 clocks = <&mlb_clkin_ck>;
1106                 ti,max-div = <64>;
1107                 reg = <0x0134>;
1108                 ti,index-power-of-two;
1109         };
1110
1111         mlbp_clk: mlbp_clk {
1112                 #clock-cells = <0>;
1113                 compatible = "ti,divider-clock";
1114                 clocks = <&mlbp_clkin_ck>;
1115                 ti,max-div = <64>;
1116                 reg = <0x0130>;
1117                 ti,index-power-of-two;
1118         };
1119
1120         per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
1121                 #clock-cells = <0>;
1122                 compatible = "ti,divider-clock";
1123                 clocks = <&dpll_abe_m2_ck>;
1124                 ti,max-div = <64>;
1125                 reg = <0x0138>;
1126                 ti,index-power-of-two;
1127         };
1128
1129         timer_sys_clk_div: timer_sys_clk_div {
1130                 #clock-cells = <0>;
1131                 compatible = "ti,divider-clock";
1132                 clocks = <&sys_clkin1>;
1133                 reg = <0x0144>;
1134                 ti,max-div = <2>;
1135         };
1136
1137         video1_dpll_clk_mux: video1_dpll_clk_mux {
1138                 #clock-cells = <0>;
1139                 compatible = "ti,mux-clock";
1140                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1141                 reg = <0x01d0>;
1142         };
1143
1144         video2_dpll_clk_mux: video2_dpll_clk_mux {
1145                 #clock-cells = <0>;
1146                 compatible = "ti,mux-clock";
1147                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1148                 reg = <0x01d4>;
1149         };
1150
1151         wkupaon_iclk_mux: wkupaon_iclk_mux {
1152                 #clock-cells = <0>;
1153                 compatible = "ti,mux-clock";
1154                 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1155                 reg = <0x0108>;
1156         };
1157
1158         gpio1_dbclk: gpio1_dbclk {
1159                 #clock-cells = <0>;
1160                 compatible = "ti,gate-clock";
1161                 clocks = <&sys_32k_ck>;
1162                 ti,bit-shift = <8>;
1163                 reg = <0x1838>;
1164         };
1165
1166         dcan1_sys_clk_mux: dcan1_sys_clk_mux {
1167                 #clock-cells = <0>;
1168                 compatible = "ti,mux-clock";
1169                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1170                 ti,bit-shift = <24>;
1171                 reg = <0x1888>;
1172         };
1173
1174         timer1_gfclk_mux: timer1_gfclk_mux {
1175                 #clock-cells = <0>;
1176                 compatible = "ti,mux-clock";
1177                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1178                 ti,bit-shift = <24>;
1179                 reg = <0x1840>;
1180         };
1181
1182         uart10_gfclk_mux: uart10_gfclk_mux {
1183                 #clock-cells = <0>;
1184                 compatible = "ti,mux-clock";
1185                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1186                 ti,bit-shift = <24>;
1187                 reg = <0x1880>;
1188         };
1189 };
1190 &cm_core_clocks {
1191         dpll_pcie_ref_ck: dpll_pcie_ref_ck {
1192                 #clock-cells = <0>;
1193                 compatible = "ti,omap4-dpll-clock";
1194                 clocks = <&sys_clkin1>, <&sys_clkin1>;
1195                 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1196         };
1197
1198         dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
1199                 #clock-cells = <0>;
1200                 compatible = "ti,divider-clock";
1201                 clocks = <&dpll_pcie_ref_ck>;
1202                 ti,max-div = <31>;
1203                 ti,autoidle-shift = <8>;
1204                 reg = <0x0210>;
1205                 ti,index-starts-at-one;
1206                 ti,invert-autoidle-bit;
1207         };
1208
1209         apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1210                 compatible = "ti,mux-clock";
1211                 clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
1212                 #clock-cells = <0>;
1213                 reg = <0x021c 0x4>;
1214                 ti,bit-shift = <7>;
1215         };
1216
1217         apll_pcie_ck: apll_pcie_ck {
1218                 #clock-cells = <0>;
1219                 compatible = "ti,dra7-apll-clock";
1220                 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1221                 reg = <0x021c>, <0x0220>;
1222         };
1223
1224         optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1225                 compatible = "ti,divider-clock";
1226                 clocks = <&apll_pcie_ck>;
1227                 #clock-cells = <0>;
1228                 reg = <0x021c>;
1229                 ti,bit-shift = <8>;
1230                 ti,max-div = <2>;
1231         };
1232
1233         optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
1234                 compatible = "ti,gate-clock";
1235                 clocks = <&apll_pcie_ck>;
1236                 #clock-cells = <0>;
1237                 reg = <0x13b0>;
1238                 ti,bit-shift = <9>;
1239         };
1240
1241         optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
1242                 compatible = "ti,gate-clock";
1243                 clocks = <&optfclk_pciephy_div>;
1244                 #clock-cells = <0>;
1245                 reg = <0x13b0>;
1246                 ti,bit-shift = <10>;
1247         };
1248
1249         apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1250                 #clock-cells = <0>;
1251                 compatible = "fixed-factor-clock";
1252                 clocks = <&apll_pcie_ck>;
1253                 clock-mult = <1>;
1254                 clock-div = <1>;
1255         };
1256
1257         apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1258                 #clock-cells = <0>;
1259                 compatible = "fixed-factor-clock";
1260                 clocks = <&apll_pcie_ck>;
1261                 clock-mult = <1>;
1262                 clock-div = <1>;
1263         };
1264
1265         apll_pcie_m2_ck: apll_pcie_m2_ck {
1266                 #clock-cells = <0>;
1267                 compatible = "fixed-factor-clock";
1268                 clocks = <&apll_pcie_ck>;
1269                 clock-mult = <1>;
1270                 clock-div = <1>;
1271         };
1272
1273         dpll_per_byp_mux: dpll_per_byp_mux {
1274                 #clock-cells = <0>;
1275                 compatible = "ti,mux-clock";
1276                 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1277                 ti,bit-shift = <23>;
1278                 reg = <0x014c>;
1279         };
1280
1281         dpll_per_ck: dpll_per_ck {
1282                 #clock-cells = <0>;
1283                 compatible = "ti,omap4-dpll-clock";
1284                 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1285                 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1286         };
1287
1288         dpll_per_m2_ck: dpll_per_m2_ck {
1289                 #clock-cells = <0>;
1290                 compatible = "ti,divider-clock";
1291                 clocks = <&dpll_per_ck>;
1292                 ti,max-div = <31>;
1293                 ti,autoidle-shift = <8>;
1294                 reg = <0x0150>;
1295                 ti,index-starts-at-one;
1296                 ti,invert-autoidle-bit;
1297         };
1298
1299         func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1300                 #clock-cells = <0>;
1301                 compatible = "fixed-factor-clock";
1302                 clocks = <&dpll_per_m2_ck>;
1303                 clock-mult = <1>;
1304                 clock-div = <1>;
1305         };
1306
1307         dpll_usb_byp_mux: dpll_usb_byp_mux {
1308                 #clock-cells = <0>;
1309                 compatible = "ti,mux-clock";
1310                 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1311                 ti,bit-shift = <23>;
1312                 reg = <0x018c>;
1313         };
1314
1315         dpll_usb_ck: dpll_usb_ck {
1316                 #clock-cells = <0>;
1317                 compatible = "ti,omap4-dpll-j-type-clock";
1318                 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1319                 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1320         };
1321
1322         dpll_usb_m2_ck: dpll_usb_m2_ck {
1323                 #clock-cells = <0>;
1324                 compatible = "ti,divider-clock";
1325                 clocks = <&dpll_usb_ck>;
1326                 ti,max-div = <127>;
1327                 ti,autoidle-shift = <8>;
1328                 reg = <0x0190>;
1329                 ti,index-starts-at-one;
1330                 ti,invert-autoidle-bit;
1331         };
1332
1333         dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
1334                 #clock-cells = <0>;
1335                 compatible = "ti,divider-clock";
1336                 clocks = <&dpll_pcie_ref_ck>;
1337                 ti,max-div = <127>;
1338                 ti,autoidle-shift = <8>;
1339                 reg = <0x0210>;
1340                 ti,index-starts-at-one;
1341                 ti,invert-autoidle-bit;
1342         };
1343
1344         dpll_per_x2_ck: dpll_per_x2_ck {
1345                 #clock-cells = <0>;
1346                 compatible = "ti,omap4-dpll-x2-clock";
1347                 clocks = <&dpll_per_ck>;
1348         };
1349
1350         dpll_per_h11x2_ck: dpll_per_h11x2_ck {
1351                 #clock-cells = <0>;
1352                 compatible = "ti,divider-clock";
1353                 clocks = <&dpll_per_x2_ck>;
1354                 ti,max-div = <63>;
1355                 ti,autoidle-shift = <8>;
1356                 reg = <0x0158>;
1357                 ti,index-starts-at-one;
1358                 ti,invert-autoidle-bit;
1359         };
1360
1361         dpll_per_h12x2_ck: dpll_per_h12x2_ck {
1362                 #clock-cells = <0>;
1363                 compatible = "ti,divider-clock";
1364                 clocks = <&dpll_per_x2_ck>;
1365                 ti,max-div = <63>;
1366                 ti,autoidle-shift = <8>;
1367                 reg = <0x015c>;
1368                 ti,index-starts-at-one;
1369                 ti,invert-autoidle-bit;
1370         };
1371
1372         dpll_per_h13x2_ck: dpll_per_h13x2_ck {
1373                 #clock-cells = <0>;
1374                 compatible = "ti,divider-clock";
1375                 clocks = <&dpll_per_x2_ck>;
1376                 ti,max-div = <63>;
1377                 ti,autoidle-shift = <8>;
1378                 reg = <0x0160>;
1379                 ti,index-starts-at-one;
1380                 ti,invert-autoidle-bit;
1381         };
1382
1383         dpll_per_h14x2_ck: dpll_per_h14x2_ck {
1384                 #clock-cells = <0>;
1385                 compatible = "ti,divider-clock";
1386                 clocks = <&dpll_per_x2_ck>;
1387                 ti,max-div = <63>;
1388                 ti,autoidle-shift = <8>;
1389                 reg = <0x0164>;
1390                 ti,index-starts-at-one;
1391                 ti,invert-autoidle-bit;
1392         };
1393
1394         dpll_per_m2x2_ck: dpll_per_m2x2_ck {
1395                 #clock-cells = <0>;
1396                 compatible = "ti,divider-clock";
1397                 clocks = <&dpll_per_x2_ck>;
1398                 ti,max-div = <31>;
1399                 ti,autoidle-shift = <8>;
1400                 reg = <0x0150>;
1401                 ti,index-starts-at-one;
1402                 ti,invert-autoidle-bit;
1403         };
1404
1405         dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1406                 #clock-cells = <0>;
1407                 compatible = "fixed-factor-clock";
1408                 clocks = <&dpll_usb_ck>;
1409                 clock-mult = <1>;
1410                 clock-div = <1>;
1411         };
1412
1413         func_128m_clk: func_128m_clk {
1414                 #clock-cells = <0>;
1415                 compatible = "fixed-factor-clock";
1416                 clocks = <&dpll_per_h11x2_ck>;
1417                 clock-mult = <1>;
1418                 clock-div = <2>;
1419         };
1420
1421         func_12m_fclk: func_12m_fclk {
1422                 #clock-cells = <0>;
1423                 compatible = "fixed-factor-clock";
1424                 clocks = <&dpll_per_m2x2_ck>;
1425                 clock-mult = <1>;
1426                 clock-div = <16>;
1427         };
1428
1429         func_24m_clk: func_24m_clk {
1430                 #clock-cells = <0>;
1431                 compatible = "fixed-factor-clock";
1432                 clocks = <&dpll_per_m2_ck>;
1433                 clock-mult = <1>;
1434                 clock-div = <4>;
1435         };
1436
1437         func_48m_fclk: func_48m_fclk {
1438                 #clock-cells = <0>;
1439                 compatible = "fixed-factor-clock";
1440                 clocks = <&dpll_per_m2x2_ck>;
1441                 clock-mult = <1>;
1442                 clock-div = <4>;
1443         };
1444
1445         func_96m_fclk: func_96m_fclk {
1446                 #clock-cells = <0>;
1447                 compatible = "fixed-factor-clock";
1448                 clocks = <&dpll_per_m2x2_ck>;
1449                 clock-mult = <1>;
1450                 clock-div = <2>;
1451         };
1452
1453         l3init_60m_fclk: l3init_60m_fclk {
1454                 #clock-cells = <0>;
1455                 compatible = "ti,divider-clock";
1456                 clocks = <&dpll_usb_m2_ck>;
1457                 reg = <0x0104>;
1458                 ti,dividers = <1>, <8>;
1459         };
1460
1461         dss_32khz_clk: dss_32khz_clk {
1462                 #clock-cells = <0>;
1463                 compatible = "ti,gate-clock";
1464                 clocks = <&sys_32k_ck>;
1465                 ti,bit-shift = <11>;
1466                 reg = <0x1120>;
1467         };
1468
1469         dss_48mhz_clk: dss_48mhz_clk {
1470                 #clock-cells = <0>;
1471                 compatible = "ti,gate-clock";
1472                 clocks = <&func_48m_fclk>;
1473                 ti,bit-shift = <9>;
1474                 reg = <0x1120>;
1475         };
1476
1477         dss_dss_clk: dss_dss_clk {
1478                 #clock-cells = <0>;
1479                 compatible = "ti,gate-clock";
1480                 clocks = <&dpll_per_h12x2_ck>;
1481                 ti,bit-shift = <8>;
1482                 reg = <0x1120>;
1483         };
1484
1485         dss_hdmi_clk: dss_hdmi_clk {
1486                 #clock-cells = <0>;
1487                 compatible = "ti,gate-clock";
1488                 clocks = <&hdmi_dpll_clk_mux>;
1489                 ti,bit-shift = <10>;
1490                 reg = <0x1120>;
1491         };
1492
1493         dss_video1_clk: dss_video1_clk {
1494                 #clock-cells = <0>;
1495                 compatible = "ti,gate-clock";
1496                 clocks = <&video1_dpll_clk_mux>;
1497                 ti,bit-shift = <12>;
1498                 reg = <0x1120>;
1499         };
1500
1501         dss_video2_clk: dss_video2_clk {
1502                 #clock-cells = <0>;
1503                 compatible = "ti,gate-clock";
1504                 clocks = <&video2_dpll_clk_mux>;
1505                 ti,bit-shift = <13>;
1506                 reg = <0x1120>;
1507         };
1508
1509         gpio2_dbclk: gpio2_dbclk {
1510                 #clock-cells = <0>;
1511                 compatible = "ti,gate-clock";
1512                 clocks = <&sys_32k_ck>;
1513                 ti,bit-shift = <8>;
1514                 reg = <0x1760>;
1515         };
1516
1517         gpio3_dbclk: gpio3_dbclk {
1518                 #clock-cells = <0>;
1519                 compatible = "ti,gate-clock";
1520                 clocks = <&sys_32k_ck>;
1521                 ti,bit-shift = <8>;
1522                 reg = <0x1768>;
1523         };
1524
1525         gpio4_dbclk: gpio4_dbclk {
1526                 #clock-cells = <0>;
1527                 compatible = "ti,gate-clock";
1528                 clocks = <&sys_32k_ck>;
1529                 ti,bit-shift = <8>;
1530                 reg = <0x1770>;
1531         };
1532
1533         gpio5_dbclk: gpio5_dbclk {
1534                 #clock-cells = <0>;
1535                 compatible = "ti,gate-clock";
1536                 clocks = <&sys_32k_ck>;
1537                 ti,bit-shift = <8>;
1538                 reg = <0x1778>;
1539         };
1540
1541         gpio6_dbclk: gpio6_dbclk {
1542                 #clock-cells = <0>;
1543                 compatible = "ti,gate-clock";
1544                 clocks = <&sys_32k_ck>;
1545                 ti,bit-shift = <8>;
1546                 reg = <0x1780>;
1547         };
1548
1549         gpio7_dbclk: gpio7_dbclk {
1550                 #clock-cells = <0>;
1551                 compatible = "ti,gate-clock";
1552                 clocks = <&sys_32k_ck>;
1553                 ti,bit-shift = <8>;
1554                 reg = <0x1810>;
1555         };
1556
1557         gpio8_dbclk: gpio8_dbclk {
1558                 #clock-cells = <0>;
1559                 compatible = "ti,gate-clock";
1560                 clocks = <&sys_32k_ck>;
1561                 ti,bit-shift = <8>;
1562                 reg = <0x1818>;
1563         };
1564
1565         mmc1_clk32k: mmc1_clk32k {
1566                 #clock-cells = <0>;
1567                 compatible = "ti,gate-clock";
1568                 clocks = <&sys_32k_ck>;
1569                 ti,bit-shift = <8>;
1570                 reg = <0x1328>;
1571         };
1572
1573         mmc2_clk32k: mmc2_clk32k {
1574                 #clock-cells = <0>;
1575                 compatible = "ti,gate-clock";
1576                 clocks = <&sys_32k_ck>;
1577                 ti,bit-shift = <8>;
1578                 reg = <0x1330>;
1579         };
1580
1581         mmc3_clk32k: mmc3_clk32k {
1582                 #clock-cells = <0>;
1583                 compatible = "ti,gate-clock";
1584                 clocks = <&sys_32k_ck>;
1585                 ti,bit-shift = <8>;
1586                 reg = <0x1820>;
1587         };
1588
1589         mmc4_clk32k: mmc4_clk32k {
1590                 #clock-cells = <0>;
1591                 compatible = "ti,gate-clock";
1592                 clocks = <&sys_32k_ck>;
1593                 ti,bit-shift = <8>;
1594                 reg = <0x1828>;
1595         };
1596
1597         sata_ref_clk: sata_ref_clk {
1598                 #clock-cells = <0>;
1599                 compatible = "ti,gate-clock";
1600                 clocks = <&sys_clkin1>;
1601                 ti,bit-shift = <8>;
1602                 reg = <0x1388>;
1603         };
1604
1605         usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
1606                 #clock-cells = <0>;
1607                 compatible = "ti,gate-clock";
1608                 clocks = <&dpll_usb_clkdcoldo>;
1609                 ti,bit-shift = <8>;
1610                 reg = <0x13f0>;
1611         };
1612
1613         usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
1614                 #clock-cells = <0>;
1615                 compatible = "ti,gate-clock";
1616                 clocks = <&dpll_usb_clkdcoldo>;
1617                 ti,bit-shift = <8>;
1618                 reg = <0x1340>;
1619         };
1620
1621         usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
1622                 #clock-cells = <0>;
1623                 compatible = "ti,gate-clock";
1624                 clocks = <&sys_32k_ck>;
1625                 ti,bit-shift = <8>;
1626                 reg = <0x0640>;
1627         };
1628
1629         usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
1630                 #clock-cells = <0>;
1631                 compatible = "ti,gate-clock";
1632                 clocks = <&sys_32k_ck>;
1633                 ti,bit-shift = <8>;
1634                 reg = <0x0688>;
1635         };
1636
1637         usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
1638                 #clock-cells = <0>;
1639                 compatible = "ti,gate-clock";
1640                 clocks = <&sys_32k_ck>;
1641                 ti,bit-shift = <8>;
1642                 reg = <0x0698>;
1643         };
1644
1645         atl_dpll_clk_mux: atl_dpll_clk_mux {
1646                 #clock-cells = <0>;
1647                 compatible = "ti,mux-clock";
1648                 clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
1649                 ti,bit-shift = <24>;
1650                 reg = <0x0c00>;
1651         };
1652
1653         atl_gfclk_mux: atl_gfclk_mux {
1654                 #clock-cells = <0>;
1655                 compatible = "ti,mux-clock";
1656                 clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
1657                 ti,bit-shift = <26>;
1658                 reg = <0x0c00>;
1659         };
1660
1661         gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
1662                 #clock-cells = <0>;
1663                 compatible = "ti,divider-clock";
1664                 clocks = <&dpll_gmac_m2_ck>;
1665                 ti,bit-shift = <24>;
1666                 reg = <0x13d0>;
1667                 ti,dividers = <2>;
1668         };
1669
1670         gmac_rft_clk_mux: gmac_rft_clk_mux {
1671                 #clock-cells = <0>;
1672                 compatible = "ti,mux-clock";
1673                 clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
1674                 ti,bit-shift = <25>;
1675                 reg = <0x13d0>;
1676         };
1677
1678         gpu_core_gclk_mux: gpu_core_gclk_mux {
1679                 #clock-cells = <0>;
1680                 compatible = "ti,mux-clock";
1681                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1682                 ti,bit-shift = <24>;
1683                 reg = <0x1220>;
1684         };
1685
1686         gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
1687                 #clock-cells = <0>;
1688                 compatible = "ti,mux-clock";
1689                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1690                 ti,bit-shift = <26>;
1691                 reg = <0x1220>;
1692         };
1693
1694         l3instr_ts_gclk_div: l3instr_ts_gclk_div {
1695                 #clock-cells = <0>;
1696                 compatible = "ti,divider-clock";
1697                 clocks = <&wkupaon_iclk_mux>;
1698                 ti,bit-shift = <24>;
1699                 reg = <0x0e50>;
1700                 ti,dividers = <8>, <16>, <32>;
1701         };
1702
1703         mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
1704                 #clock-cells = <0>;
1705                 compatible = "ti,mux-clock";
1706                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1707                 ti,bit-shift = <28>;
1708                 reg = <0x1860>;
1709         };
1710
1711         mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
1712                 #clock-cells = <0>;
1713                 compatible = "ti,mux-clock";
1714                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1715                 ti,bit-shift = <28>;
1716                 reg = <0x1860>;
1717         };
1718
1719         mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
1720                 #clock-cells = <0>;
1721                 compatible = "ti,mux-clock";
1722                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1723                 ti,bit-shift = <22>;
1724                 reg = <0x1860>;
1725         };
1726
1727         mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
1728                 #clock-cells = <0>;
1729                 compatible = "ti,mux-clock";
1730                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1731                 ti,bit-shift = <24>;
1732                 reg = <0x1868>;
1733         };
1734
1735         mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
1736                 #clock-cells = <0>;
1737                 compatible = "ti,mux-clock";
1738                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1739                 ti,bit-shift = <22>;
1740                 reg = <0x1868>;
1741         };
1742
1743         mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
1744                 #clock-cells = <0>;
1745                 compatible = "ti,mux-clock";
1746                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1747                 ti,bit-shift = <24>;
1748                 reg = <0x1898>;
1749         };
1750
1751         mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
1752                 #clock-cells = <0>;
1753                 compatible = "ti,mux-clock";
1754                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1755                 ti,bit-shift = <22>;
1756                 reg = <0x1898>;
1757         };
1758
1759         mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
1760                 #clock-cells = <0>;
1761                 compatible = "ti,mux-clock";
1762                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1763                 ti,bit-shift = <24>;
1764                 reg = <0x1878>;
1765         };
1766
1767         mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
1768                 #clock-cells = <0>;
1769                 compatible = "ti,mux-clock";
1770                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1771                 ti,bit-shift = <22>;
1772                 reg = <0x1878>;
1773         };
1774
1775         mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
1776                 #clock-cells = <0>;
1777                 compatible = "ti,mux-clock";
1778                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1779                 ti,bit-shift = <24>;
1780                 reg = <0x1904>;
1781         };
1782
1783         mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
1784                 #clock-cells = <0>;
1785                 compatible = "ti,mux-clock";
1786                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1787                 ti,bit-shift = <22>;
1788                 reg = <0x1904>;
1789         };
1790
1791         mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
1792                 #clock-cells = <0>;
1793                 compatible = "ti,mux-clock";
1794                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1795                 ti,bit-shift = <24>;
1796                 reg = <0x1908>;
1797         };
1798
1799         mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
1800                 #clock-cells = <0>;
1801                 compatible = "ti,mux-clock";
1802                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1803                 ti,bit-shift = <22>;
1804                 reg = <0x1908>;
1805         };
1806
1807         mcasp8_ahclk_mux: mcasp8_ahclk_mux {
1808                 #clock-cells = <0>;
1809                 compatible = "ti,mux-clock";
1810                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1811                 ti,bit-shift = <22>;
1812                 reg = <0x1890>;
1813         };
1814
1815         mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
1816                 #clock-cells = <0>;
1817                 compatible = "ti,mux-clock";
1818                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1819                 ti,bit-shift = <24>;
1820                 reg = <0x1890>;
1821         };
1822
1823         mmc1_fclk_mux: mmc1_fclk_mux {
1824                 #clock-cells = <0>;
1825                 compatible = "ti,mux-clock";
1826                 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1827                 ti,bit-shift = <24>;
1828                 reg = <0x1328>;
1829         };
1830
1831         mmc1_fclk_div: mmc1_fclk_div {
1832                 #clock-cells = <0>;
1833                 compatible = "ti,divider-clock";
1834                 clocks = <&mmc1_fclk_mux>;
1835                 ti,bit-shift = <25>;
1836                 ti,max-div = <4>;
1837                 reg = <0x1328>;
1838                 ti,index-power-of-two;
1839         };
1840
1841         mmc2_fclk_mux: mmc2_fclk_mux {
1842                 #clock-cells = <0>;
1843                 compatible = "ti,mux-clock";
1844                 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1845                 ti,bit-shift = <24>;
1846                 reg = <0x1330>;
1847         };
1848
1849         mmc2_fclk_div: mmc2_fclk_div {
1850                 #clock-cells = <0>;
1851                 compatible = "ti,divider-clock";
1852                 clocks = <&mmc2_fclk_mux>;
1853                 ti,bit-shift = <25>;
1854                 ti,max-div = <4>;
1855                 reg = <0x1330>;
1856                 ti,index-power-of-two;
1857         };
1858
1859         mmc3_gfclk_mux: mmc3_gfclk_mux {
1860                 #clock-cells = <0>;
1861                 compatible = "ti,mux-clock";
1862                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1863                 ti,bit-shift = <24>;
1864                 reg = <0x1820>;
1865         };
1866
1867         mmc3_gfclk_div: mmc3_gfclk_div {
1868                 #clock-cells = <0>;
1869                 compatible = "ti,divider-clock";
1870                 clocks = <&mmc3_gfclk_mux>;
1871                 ti,bit-shift = <25>;
1872                 ti,max-div = <4>;
1873                 reg = <0x1820>;
1874                 ti,index-power-of-two;
1875         };
1876
1877         mmc4_gfclk_mux: mmc4_gfclk_mux {
1878                 #clock-cells = <0>;
1879                 compatible = "ti,mux-clock";
1880                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1881                 ti,bit-shift = <24>;
1882                 reg = <0x1828>;
1883         };
1884
1885         mmc4_gfclk_div: mmc4_gfclk_div {
1886                 #clock-cells = <0>;
1887                 compatible = "ti,divider-clock";
1888                 clocks = <&mmc4_gfclk_mux>;
1889                 ti,bit-shift = <25>;
1890                 ti,max-div = <4>;
1891                 reg = <0x1828>;
1892                 ti,index-power-of-two;
1893         };
1894
1895         qspi_gfclk_mux: qspi_gfclk_mux {
1896                 #clock-cells = <0>;
1897                 compatible = "ti,mux-clock";
1898                 clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
1899                 ti,bit-shift = <24>;
1900                 reg = <0x1838>;
1901         };
1902
1903         qspi_gfclk_div: qspi_gfclk_div {
1904                 #clock-cells = <0>;
1905                 compatible = "ti,divider-clock";
1906                 clocks = <&qspi_gfclk_mux>;
1907                 ti,bit-shift = <25>;
1908                 ti,max-div = <4>;
1909                 reg = <0x1838>;
1910                 ti,index-power-of-two;
1911         };
1912
1913         timer10_gfclk_mux: timer10_gfclk_mux {
1914                 #clock-cells = <0>;
1915                 compatible = "ti,mux-clock";
1916                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1917                 ti,bit-shift = <24>;
1918                 reg = <0x1728>;
1919         };
1920
1921         timer11_gfclk_mux: timer11_gfclk_mux {
1922                 #clock-cells = <0>;
1923                 compatible = "ti,mux-clock";
1924                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1925                 ti,bit-shift = <24>;
1926                 reg = <0x1730>;
1927         };
1928
1929         timer13_gfclk_mux: timer13_gfclk_mux {
1930                 #clock-cells = <0>;
1931                 compatible = "ti,mux-clock";
1932                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1933                 ti,bit-shift = <24>;
1934                 reg = <0x17c8>;
1935         };
1936
1937         timer14_gfclk_mux: timer14_gfclk_mux {
1938                 #clock-cells = <0>;
1939                 compatible = "ti,mux-clock";
1940                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1941                 ti,bit-shift = <24>;
1942                 reg = <0x17d0>;
1943         };
1944
1945         timer15_gfclk_mux: timer15_gfclk_mux {
1946                 #clock-cells = <0>;
1947                 compatible = "ti,mux-clock";
1948                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1949                 ti,bit-shift = <24>;
1950                 reg = <0x17d8>;
1951         };
1952
1953         timer16_gfclk_mux: timer16_gfclk_mux {
1954                 #clock-cells = <0>;
1955                 compatible = "ti,mux-clock";
1956                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1957                 ti,bit-shift = <24>;
1958                 reg = <0x1830>;
1959         };
1960
1961         timer2_gfclk_mux: timer2_gfclk_mux {
1962                 #clock-cells = <0>;
1963                 compatible = "ti,mux-clock";
1964                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1965                 ti,bit-shift = <24>;
1966                 reg = <0x1738>;
1967         };
1968
1969         timer3_gfclk_mux: timer3_gfclk_mux {
1970                 #clock-cells = <0>;
1971                 compatible = "ti,mux-clock";
1972                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1973                 ti,bit-shift = <24>;
1974                 reg = <0x1740>;
1975         };
1976
1977         timer4_gfclk_mux: timer4_gfclk_mux {
1978                 #clock-cells = <0>;
1979                 compatible = "ti,mux-clock";
1980                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1981                 ti,bit-shift = <24>;
1982                 reg = <0x1748>;
1983         };
1984
1985         timer9_gfclk_mux: timer9_gfclk_mux {
1986                 #clock-cells = <0>;
1987                 compatible = "ti,mux-clock";
1988                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1989                 ti,bit-shift = <24>;
1990                 reg = <0x1750>;
1991         };
1992
1993         uart1_gfclk_mux: uart1_gfclk_mux {
1994                 #clock-cells = <0>;
1995                 compatible = "ti,mux-clock";
1996                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1997                 ti,bit-shift = <24>;
1998                 reg = <0x1840>;
1999         };
2000
2001         uart2_gfclk_mux: uart2_gfclk_mux {
2002                 #clock-cells = <0>;
2003                 compatible = "ti,mux-clock";
2004                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2005                 ti,bit-shift = <24>;
2006                 reg = <0x1848>;
2007         };
2008
2009         uart3_gfclk_mux: uart3_gfclk_mux {
2010                 #clock-cells = <0>;
2011                 compatible = "ti,mux-clock";
2012                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2013                 ti,bit-shift = <24>;
2014                 reg = <0x1850>;
2015         };
2016
2017         uart4_gfclk_mux: uart4_gfclk_mux {
2018                 #clock-cells = <0>;
2019                 compatible = "ti,mux-clock";
2020                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2021                 ti,bit-shift = <24>;
2022                 reg = <0x1858>;
2023         };
2024
2025         uart5_gfclk_mux: uart5_gfclk_mux {
2026                 #clock-cells = <0>;
2027                 compatible = "ti,mux-clock";
2028                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2029                 ti,bit-shift = <24>;
2030                 reg = <0x1870>;
2031         };
2032
2033         uart7_gfclk_mux: uart7_gfclk_mux {
2034                 #clock-cells = <0>;
2035                 compatible = "ti,mux-clock";
2036                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2037                 ti,bit-shift = <24>;
2038                 reg = <0x18d0>;
2039         };
2040
2041         uart8_gfclk_mux: uart8_gfclk_mux {
2042                 #clock-cells = <0>;
2043                 compatible = "ti,mux-clock";
2044                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2045                 ti,bit-shift = <24>;
2046                 reg = <0x18e0>;
2047         };
2048
2049         uart9_gfclk_mux: uart9_gfclk_mux {
2050                 #clock-cells = <0>;
2051                 compatible = "ti,mux-clock";
2052                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2053                 ti,bit-shift = <24>;
2054                 reg = <0x18e8>;
2055         };
2056
2057         vip1_gclk_mux: vip1_gclk_mux {
2058                 #clock-cells = <0>;
2059                 compatible = "ti,mux-clock";
2060                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2061                 ti,bit-shift = <24>;
2062                 reg = <0x1020>;
2063         };
2064
2065         vip2_gclk_mux: vip2_gclk_mux {
2066                 #clock-cells = <0>;
2067                 compatible = "ti,mux-clock";
2068                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2069                 ti,bit-shift = <24>;
2070                 reg = <0x1028>;
2071         };
2072
2073         vip3_gclk_mux: vip3_gclk_mux {
2074                 #clock-cells = <0>;
2075                 compatible = "ti,mux-clock";
2076                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2077                 ti,bit-shift = <24>;
2078                 reg = <0x1030>;
2079         };
2080 };
2081
2082 &cm_core_clockdomains {
2083         coreaon_clkdm: coreaon_clkdm {
2084                 compatible = "ti,clockdomain";
2085                 clocks = <&dpll_usb_ck>;
2086         };
2087 };