arch/arm/boot/dts/dra7-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra74x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12
  13 / {
  14         model = "TI DRA742";
  15         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  16
  17         memory {
  18                 device_type = "memory";
  19                 reg = <0x80000000 0x60000000>; /* 1536 MB */
  20         };
  21
  22         mmc2_3v3: fixedregulator-mmc2 {
  23                 compatible = "regulator-fixed";
  24                 regulator-name = "mmc2_3v3";
  25                 regulator-min-microvolt = <3300000>;
  26                 regulator-max-microvolt = <3300000>;
  27         };
  28
  29         vtt_fixed: fixedregulator-vtt {
  30                 compatible = "regulator-fixed";
  31                 regulator-name = "vtt_fixed";
  32                 regulator-min-microvolt = <1350000>;
  33                 regulator-max-microvolt = <1350000>;
  34                 regulator-always-on;
  35                 regulator-boot-on;
  36                 enable-active-high;
  37                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
  38         };
  39 };
  40
  41 &dra7_pmx_core {
  42         pinctrl-names = "default";
  43         pinctrl-0 = <&vtt_pin>;
  44
  45         vtt_pin: pinmux_vtt_pin {
  46                 pinctrl-single,pins = <
  47                         0x3b4 (PIN_OUTPUT | MUX_MODE14) /* spi1_cs1.gpio7_11 */
  48                 >;
  49         };
  50
  51         i2c1_pins: pinmux_i2c1_pins {
  52                 pinctrl-single,pins = <
  53                         0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
  54                         0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
  55                 >;
  56         };
  57
  58         i2c2_pins: pinmux_i2c2_pins {
  59                 pinctrl-single,pins = <
  60                         0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
  61                         0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
  62                 >;
  63         };
  64
  65         i2c3_pins: pinmux_i2c3_pins {
  66                 pinctrl-single,pins = <
  67                         0x288 (PIN_INPUT | MUX_MODE9) /* gpio6_14.i2c3_sda */
  68                         0x28c (PIN_INPUT | MUX_MODE9) /* gpio6_15.i2c3_scl */
  69                 >;
  70         };
  71
  72         mcspi1_pins: pinmux_mcspi1_pins {
  73                 pinctrl-single,pins = <
  74                         0x3a4 (PIN_INPUT | MUX_MODE0) /* spi1_sclk */
  75                         0x3a8 (PIN_INPUT | MUX_MODE0) /* spi1_d1 */
  76                         0x3ac (PIN_INPUT | MUX_MODE0) /* spi1_d0 */
  77                         0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi1_cs0 */
  78                         0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs2.hdmi1_hpd */
  79                         0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi1_cs3.hdmi1_cec */
  80                 >;
  81         };
  82
  83         mcspi2_pins: pinmux_mcspi2_pins {
  84                 pinctrl-single,pins = <
  85                         0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
  86                         0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
  87                         0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
  88                         0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
  89                 >;
  90         };
  91
  92         uart1_pins: pinmux_uart1_pins {
  93                 pinctrl-single,pins = <
  94                         0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
  95                         0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
  96                         0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
  97                         0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
  98                 >;
  99         };
 100
 101         uart2_pins: pinmux_uart2_pins {
 102                 pinctrl-single,pins = <
 103                         0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
 104                         0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
 105                         0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
 106                         0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
 107                 >;
 108         };
 109
 110         uart3_pins: pinmux_uart3_pins {
 111                 pinctrl-single,pins = <
 112                         0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
 113                         0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
 114                 >;
 115         };
 116
 117         qspi1_pins: pinmux_qspi1_pins {
 118                 pinctrl-single,pins = <
 119                         0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
 120                         0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
 121                         0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
 122                         0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
 123                         0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
 124                         0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
 125                         0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
 126                         0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
 127                         0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
 128                         0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
 129                 >;
 130         };
 131
 132         usb1_pins: pinmux_usb1_pins {
 133                 pinctrl-single,pins = <
 134                         0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
 135                 >;
 136         };
 137
 138         usb2_pins: pinmux_usb2_pins {
 139                 pinctrl-single,pins = <
 140                         0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
 141                 >;
 142         };
 143
 144         nand_flash_x16: nand_flash_x16 {
 145                 /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
 146                  * So NAND flash requires following switch settings:
 147                  * SW5.9 (GPMC_WPN) = LOW
 148                  * SW5.1 (NAND_BOOTn) = HIGH */
 149                 pinctrl-single,pins = <
 150                         0x0     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad0     */
 151                         0x4     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad1     */
 152                         0x8     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad2     */
 153                         0xc     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad3     */
 154                         0x10    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad4     */
 155                         0x14    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad5     */
 156                         0x18    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad6     */
 157                         0x1c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad7     */
 158                         0x20    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad8     */
 159                         0x24    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad9     */
 160                         0x28    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad10    */
 161                         0x2c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad11    */
 162                         0x30    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad12    */
 163                         0x34    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad13    */
 164                         0x38    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad14    */
 165                         0x3c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad15    */
 166                         0xd8    (PIN_INPUT_PULLUP  | MUX_MODE0) /* gpmc_wait0   */
 167                         0xcc    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_wen     */
 168                         0xb4    (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0    */
 169                         0xc4    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_advn_ale */
 170                         0xc8    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_oen_ren  */
 171                         0xd0    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_be0n_cle */
 172                 >;
 173         };
 174 };
 175
 176 &i2c1 {
 177         status = "okay";
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&i2c1_pins>;
 180         clock-frequency = <400000>;
 181
 182         tps659038: tps659038@58 {
 183                 compatible = "ti,tps659038";
 184                 reg = <0x58>;
 185                 ti,palmas-override-powerhold;
 186                 ti,system-power-controller;
 187
 188                 tps659038_pmic {
 189                         compatible = "ti,tps659038-pmic";
 190
 191                         regulators {
 192                                 smps123_reg: smps123 {
 193                                         /* VDD_MPU */
 194                                         regulator-name = "smps123";
 195                                         regulator-min-microvolt = < 850000>;
 196                                         regulator-max-microvolt = <1250000>;
 197                                         regulator-always-on;
 198                                         regulator-boot-on;
 199                                 };
 200
 201                                 smps45_reg: smps45 {
 202                                         /* VDD_DSPEVE */
 203                                         regulator-name = "smps45";
 204                                         regulator-min-microvolt = < 850000>;
 205                                         regulator-max-microvolt = <1150000>;
 206                                         regulator-boot-on;
 207                                 };
 208
 209                                 smps6_reg: smps6 {
 210                                         /* VDD_GPU - over VDD_SMPS6 */
 211                                         regulator-name = "smps6";
 212                                         regulator-min-microvolt = <850000>;
 213                                         regulator-max-microvolt = <12500000>;
 214                                         regulator-boot-on;
 215                                 };
 216
 217                                 smps7_reg: smps7 {
 218                                         /* CORE_VDD */
 219                                         regulator-name = "smps7";
 220                                         regulator-min-microvolt = <850000>;
 221                                         regulator-max-microvolt = <1030000>;
 222                                         regulator-always-on;
 223                                         regulator-boot-on;
 224                                 };
 225
 226                                 smps8_reg: smps8 {
 227                                         /* VDD_IVAHD */
 228                                         regulator-name = "smps8";
 229                                         regulator-min-microvolt = < 850000>;
 230                                         regulator-max-microvolt = <1250000>;
 231                                         regulator-boot-on;
 232                                 };
 233
 234                                 smps9_reg: smps9 {
 235                                         /* VDDS1V8 */
 236                                         regulator-name = "smps9";
 237                                         regulator-min-microvolt = <1800000>;
 238                                         regulator-max-microvolt = <1800000>;
 239                                         regulator-always-on;
 240                                         regulator-boot-on;
 241                                 };
 242
 243                                 ldo1_reg: ldo1 {
 244                                         /* LDO1_OUT --> SDIO  */
 245                                         regulator-name = "ldo1";
 246                                         regulator-min-microvolt = <1800000>;
 247                                         regulator-max-microvolt = <3300000>;
 248                                         regulator-boot-on;
 249                                 };
 250
 251                                 ldo2_reg: ldo2 {
 252                                         /* VDD_RTCIO */
 253                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 254                                         regulator-name = "ldo2";
 255                                         regulator-min-microvolt = <3300000>;
 256                                         regulator-max-microvolt = <3300000>;
 257                                         regulator-boot-on;
 258                                 };
 259
 260                                 ldo3_reg: ldo3 {
 261                                         /* VDDA_1V8_PHY */
 262                                         regulator-name = "ldo3";
 263                                         regulator-min-microvolt = <1800000>;
 264                                         regulator-max-microvolt = <1800000>;
 265                                         regulator-always-on;
 266                                         regulator-boot-on;
 267                                 };
 268
 269                                 ldo9_reg: ldo9 {
 270                                         /* VDD_RTC */
 271                                         regulator-name = "ldo9";
 272                                         regulator-min-microvolt = <1050000>;
 273                                         regulator-max-microvolt = <1050000>;
 274                                         regulator-boot-on;
 275                                 };
 276
 277                                 ldoln_reg: ldoln {
 278                                         /* VDDA_1V8_PLL */
 279                                         regulator-name = "ldoln";
 280                                         regulator-min-microvolt = <1800000>;
 281                                         regulator-max-microvolt = <1800000>;
 282                                         regulator-always-on;
 283                                         regulator-boot-on;
 284                                 };
 285
 286                                 ldousb_reg: ldousb {
 287                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 288                                         regulator-name = "ldousb";
 289                                         regulator-min-microvolt = <3300000>;
 290                                         regulator-max-microvolt = <3300000>;
 291                                         regulator-boot-on;
 292                                 };
 293                         };
 294                 };
 295         };
 296 };
 297
 298 &i2c2 {
 299         status = "okay";
 300         pinctrl-names = "default";
 301         pinctrl-0 = <&i2c2_pins>;
 302         clock-frequency = <400000>;
 303 };
 304
 305 &i2c3 {
 306         status = "okay";
 307         pinctrl-names = "default";
 308         pinctrl-0 = <&i2c3_pins>;
 309         clock-frequency = <400000>;
 310 };
 311
 312 &mcspi1 {
 313         status = "okay";
 314         pinctrl-names = "default";
 315         pinctrl-0 = <&mcspi1_pins>;
 316 };
 317
 318 &mcspi2 {
 319         status = "okay";
 320         pinctrl-names = "default";
 321         pinctrl-0 = <&mcspi2_pins>;
 322 };
 323
 324 &uart1 {
 325         status = "okay";
 326         pinctrl-names = "default";
 327         pinctrl-0 = <&uart1_pins>;
 328         interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 329                               <&dra7_pmx_core 0x3e0>;
 330 };
 331
 332 &uart2 {
 333         status = "okay";
 334         pinctrl-names = "default";
 335         pinctrl-0 = <&uart2_pins>;
 336 };
 337
 338 &uart3 {
 339         status = "okay";
 340         pinctrl-names = "default";
 341         pinctrl-0 = <&uart3_pins>;
 342 };
 343
 344 &mmc1 {
 345         status = "okay";
 346         vmmc-supply = <&ldo1_reg>;
 347         bus-width = <4>;
 348 };
 349
 350 &mmc2 {
 351         status = "okay";
 352         vmmc-supply = <&mmc2_3v3>;
 353         bus-width = <8>;
 354 };
 355
 356 &cpu0 {
 357         cpu0-supply = <&smps123_reg>;
 358 };
 359
 360 &qspi {
 361         status = "okay";
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&qspi1_pins>;
 364
 365         spi-max-frequency = <48000000>;
 366         m25p80@0 {
 367                 compatible = "s25fl256s1";
 368                 spi-max-frequency = <48000000>;
 369                 reg = <0>;
 370                 spi-tx-bus-width = <1>;
 371                 spi-rx-bus-width = <4>;
 372                 spi-cpol;
 373                 spi-cpha;
 374                 #address-cells = <1>;
 375                 #size-cells = <1>;
 376
 377                 /* MTD partition table.
 378                  * The ROM checks the first four physical blocks
 379                  * for a valid file to boot and the flash here is
 380                  * 64KiB block size.
 381                  */
 382                 partition@0 {
 383                         label = "QSPI.SPL";
 384                         reg = <0x00000000 0x000010000>;
 385                 };
 386                 partition@1 {
 387                         label = "QSPI.SPL.backup1";
 388                         reg = <0x00010000 0x00010000>;
 389                 };
 390                 partition@2 {
 391                         label = "QSPI.SPL.backup2";
 392                         reg = <0x00020000 0x00010000>;
 393                 };
 394                 partition@3 {
 395                         label = "QSPI.SPL.backup3";
 396                         reg = <0x00030000 0x00010000>;
 397                 };
 398                 partition@4 {
 399                         label = "QSPI.u-boot";
 400                         reg = <0x00040000 0x00100000>;
 401                 };
 402                 partition@5 {
 403                         label = "QSPI.u-boot-spl-os";
 404                         reg = <0x00140000 0x00080000>;
 405                 };
 406                 partition@6 {
 407                         label = "QSPI.u-boot-env";
 408                         reg = <0x001c0000 0x00010000>;
 409                 };
 410                 partition@7 {
 411                         label = "QSPI.u-boot-env.backup1";
 412                         reg = <0x001d0000 0x0010000>;
 413                 };
 414                 partition@8 {
 415                         label = "QSPI.kernel";
 416                         reg = <0x001e0000 0x0800000>;
 417                 };
 418                 partition@9 {
 419                         label = "QSPI.file-system";
 420                         reg = <0x009e0000 0x01620000>;
 421                 };
 422         };
 423 };
 424
 425 &usb1 {
 426         dr_mode = "peripheral";
 427         pinctrl-names = "default";
 428         pinctrl-0 = <&usb1_pins>;
 429 };
 430
 431 &usb2 {
 432         dr_mode = "host";
 433         pinctrl-names = "default";
 434         pinctrl-0 = <&usb2_pins>;
 435 };
 436
 437 &elm {
 438         status = "okay";
 439 };
 440
 441 &gpmc {
 442         status = "okay";
 443         pinctrl-names = "default";
 444         pinctrl-0 = <&nand_flash_x16>;
 445         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 446         nand@0,0 {
 447                 reg = <0 0 4>;          /* device IO registers */
 448                 ti,nand-ecc-opt = "bch8";
 449                 ti,elm-id = <&elm>;
 450                 nand-bus-width = <16>;
 451                 gpmc,device-width = <2>;
 452                 gpmc,sync-clk-ps = <0>;
 453                 gpmc,cs-on-ns = <0>;
 454                 gpmc,cs-rd-off-ns = <80>;
 455                 gpmc,cs-wr-off-ns = <80>;
 456                 gpmc,adv-on-ns = <0>;
 457                 gpmc,adv-rd-off-ns = <60>;
 458                 gpmc,adv-wr-off-ns = <60>;
 459                 gpmc,we-on-ns = <10>;
 460                 gpmc,we-off-ns = <50>;
 461                 gpmc,oe-on-ns = <4>;
 462                 gpmc,oe-off-ns = <40>;
 463                 gpmc,access-ns = <40>;
 464                 gpmc,wr-access-ns = <80>;
 465                 gpmc,rd-cycle-ns = <80>;
 466                 gpmc,wr-cycle-ns = <80>;
 467                 gpmc,bus-turnaround-ns = <0>;
 468                 gpmc,cycle2cycle-delay-ns = <0>;
 469                 gpmc,clk-activation-ns = <0>;
 470                 gpmc,wait-monitoring-ns = <0>;
 471                 gpmc,wr-data-mux-bus-ns = <0>;
 472                 /* MTD partition table */
 473                 /* All SPL-* partitions are sized to minimal length
 474                  * which can be independently programmable. For
 475                  * NAND flash this is equal to size of erase-block */
 476                 #address-cells = <1>;
 477                 #size-cells = <1>;
 478                 partition@0 {
 479                         label = "NAND.SPL";
 480                         reg = <0x00000000 0x000020000>;
 481                 };
 482                 partition@1 {
 483                         label = "NAND.SPL.backup1";
 484                         reg = <0x00020000 0x00020000>;
 485                 };
 486                 partition@2 {
 487                         label = "NAND.SPL.backup2";
 488                         reg = <0x00040000 0x00020000>;
 489                 };
 490                 partition@3 {
 491                         label = "NAND.SPL.backup3";
 492                         reg = <0x00060000 0x00020000>;
 493                 };
 494                 partition@4 {
 495                         label = "NAND.u-boot-spl-os";
 496                         reg = <0x00080000 0x00040000>;
 497                 };
 498                 partition@5 {
 499                         label = "NAND.u-boot";
 500                         reg = <0x000c0000 0x00100000>;
 501                 };
 502                 partition@6 {
 503                         label = "NAND.u-boot-env";
 504                         reg = <0x001c0000 0x00020000>;
 505                 };
 506                 partition@7 {
 507                         label = "NAND.u-boot-env.backup1";
 508                         reg = <0x001e0000 0x00020000>;
 509                 };
 510                 partition@8 {
 511                         label = "NAND.kernel";
 512                         reg = <0x00200000 0x00800000>;
 513                 };
 514                 partition@9 {
 515                         label = "NAND.file-system";
 516                         reg = <0x00a00000 0x0f600000>;
 517                 };
 518         };
 519 };
 520
 521 &usb2_phy1 {
 522         phy-supply = <&ldousb_reg>;
 523 };
 524
 525 &usb2_phy2 {
 526         phy-supply = <&ldousb_reg>;
 527 };
 528
 529 &gpio7 {
 530         ti,no-reset-on-init;
 531         ti,no-idle-on-init;
 532 };