arch/arc/include/asm/io.h

   1 /*
   2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef _ASM_ARC_IO_H
  10 #define _ASM_ARC_IO_H
  11
  12 #include <linux/types.h>
  13 #include <asm/byteorder.h>
  14 #include <asm/page.h>
  15 #include <asm/unaligned.h>
  16
  17 #ifdef CONFIG_ISA_ARCV2
  18 #include <asm/barrier.h>
  19 #define __iormb()               rmb()
  20 #define __iowmb()               wmb()
  21 #else
  22 #define __iormb()               do { } while (0)
  23 #define __iowmb()               do { } while (0)
  24 #endif
  25
  26 extern void __iomem *ioremap(unsigned long physaddr, unsigned long size);
  27 extern void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,
  28                                   unsigned long flags);
  29 extern void iounmap(const void __iomem *addr);
  30
  31 #define ioremap_nocache(phy, sz)        ioremap(phy, sz)
  32 #define ioremap_wc(phy, sz)             ioremap(phy, sz)
  33 #define ioremap_wt(phy, sz)             ioremap(phy, sz)
  34
  35 /*
  36  * io{read,write}{16,32}be() macros
  37  */
  38 #define ioread16be(p)           ({ u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
  39 #define ioread32be(p)           ({ u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
  40
  41 #define iowrite16be(v,p)        ({ __iowmb(); __raw_writew((__force u16)cpu_to_be16(v), p); })
  42 #define iowrite32be(v,p)        ({ __iowmb(); __raw_writel((__force u32)cpu_to_be32(v), p); })
  43
  44 /* Change struct page to physical address */
  45 #define page_to_phys(page)              (page_to_pfn(page) << PAGE_SHIFT)
  46
  47 #define __raw_readb __raw_readb
  48 static inline u8 __raw_readb(const volatile void __iomem *addr)
  49 {
  50         u8 b;
  51
  52         __asm__ __volatile__(
  53         "       ldb%U1 %0, %1   \n"
  54         : "=r" (b)
  55         : "m" (*(volatile u8 __force *)addr)
  56         : "memory");
  57
  58         return b;
  59 }
  60
  61 #define __raw_readw __raw_readw
  62 static inline u16 __raw_readw(const volatile void __iomem *addr)
  63 {
  64         u16 s;
  65
  66         __asm__ __volatile__(
  67         "       ldw%U1 %0, %1   \n"
  68         : "=r" (s)
  69         : "m" (*(volatile u16 __force *)addr)
  70         : "memory");
  71
  72         return s;
  73 }
  74
  75 #define __raw_readl __raw_readl
  76 static inline u32 __raw_readl(const volatile void __iomem *addr)
  77 {
  78         u32 w;
  79
  80         __asm__ __volatile__(
  81         "       ld%U1 %0, %1    \n"
  82         : "=r" (w)
  83         : "m" (*(volatile u32 __force *)addr)
  84         : "memory");
  85
  86         return w;
  87 }
  88
  89 /*
  90  * {read,write}s{b,w,l}() repeatedly access the same IO address in
  91  * native endianness in 8-, 16-, 32-bit chunks {into,from} memory,
  92  * @count times
  93  */
  94 #define __raw_readsx(t,f) \
  95 static inline void __raw_reads##f(const volatile void __iomem *addr,    \
  96                                   void *ptr, unsigned int count)        \
  97 {                                                                       \
  98         bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0;        \
  99         u##t *buf = ptr;                                                \
 100                                                                         \
 101         if (!count)                                                     \
 102                 return;                                                 \
 103                                                                         \
 104         /* Some ARC CPU's don't support unaligned accesses */           \
 105         if (is_aligned) {                                               \
 106                 do {                                                    \
 107                         u##t x = __raw_read##f(addr);                   \
 108                         *buf++ = x;                                     \
 109                 } while (--count);                                      \
 110         } else {                                                        \
 111                 do {                                                    \
 112                         u##t x = __raw_read##f(addr);                   \
 113                         put_unaligned(x, buf++);                        \
 114                 } while (--count);                                      \
 115         }                                                               \
 116 }
 117
 118 #define __raw_readsb __raw_readsb
 119 __raw_readsx(8, b)
 120 #define __raw_readsw __raw_readsw
 121 __raw_readsx(16, w)
 122 #define __raw_readsl __raw_readsl
 123 __raw_readsx(32, l)
 124
 125 #define __raw_writeb __raw_writeb
 126 static inline void __raw_writeb(u8 b, volatile void __iomem *addr)
 127 {
 128         __asm__ __volatile__(
 129         "       stb%U1 %0, %1   \n"
 130         :
 131         : "r" (b), "m" (*(volatile u8 __force *)addr)
 132         : "memory");
 133 }
 134
 135 #define __raw_writew __raw_writew
 136 static inline void __raw_writew(u16 s, volatile void __iomem *addr)
 137 {
 138         __asm__ __volatile__(
 139         "       stw%U1 %0, %1   \n"
 140         :
 141         : "r" (s), "m" (*(volatile u16 __force *)addr)
 142         : "memory");
 143
 144 }
 145
 146 #define __raw_writel __raw_writel
 147 static inline void __raw_writel(u32 w, volatile void __iomem *addr)
 148 {
 149         __asm__ __volatile__(
 150         "       st%U1 %0, %1    \n"
 151         :
 152         : "r" (w), "m" (*(volatile u32 __force *)addr)
 153         : "memory");
 154
 155 }
 156
 157 #define __raw_writesx(t,f)                                              \
 158 static inline void __raw_writes##f(volatile void __iomem *addr,         \
 159                                    const void *ptr, unsigned int count) \
 160 {                                                                       \
 161         bool is_aligned = ((unsigned long)ptr % ((t) / 8)) == 0;        \
 162         const u##t *buf = ptr;                                          \
 163                                                                         \
 164         if (!count)                                                     \
 165                 return;                                                 \
 166                                                                         \
 167         /* Some ARC CPU's don't support unaligned accesses */           \
 168         if (is_aligned) {                                               \
 169                 do {                                                    \
 170                         __raw_write##f(*buf++, addr);                   \
 171                 } while (--count);                                      \
 172         } else {                                                        \
 173                 do {                                                    \
 174                         __raw_write##f(get_unaligned(buf++), addr);     \
 175                 } while (--count);                                      \
 176         }                                                               \
 177 }
 178
 179 #define __raw_writesb __raw_writesb
 180 __raw_writesx(8, b)
 181 #define __raw_writesw __raw_writesw
 182 __raw_writesx(16, w)
 183 #define __raw_writesl __raw_writesl
 184 __raw_writesx(32, l)
 185
 186 /*
 187  * MMIO can also get buffered/optimized in micro-arch, so barriers needed
 188  * Based on ARM model for the typical use case
 189  *
 190  *      <ST [DMA buffer]>
 191  *      <writel MMIO "go" reg>
 192  *  or:
 193  *      <readl MMIO "status" reg>
 194  *      <LD [DMA buffer]>
 195  *
 196  * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
 197  */
 198 #define readb(c)                ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 199 #define readw(c)                ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
 200 #define readl(c)                ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
 201 #define readsb(p,d,l)           ({ __raw_readsb(p,d,l); __iormb(); })
 202 #define readsw(p,d,l)           ({ __raw_readsw(p,d,l); __iormb(); })
 203 #define readsl(p,d,l)           ({ __raw_readsl(p,d,l); __iormb(); })
 204
 205 #define writeb(v,c)             ({ __iowmb(); writeb_relaxed(v,c); })
 206 #define writew(v,c)             ({ __iowmb(); writew_relaxed(v,c); })
 207 #define writel(v,c)             ({ __iowmb(); writel_relaxed(v,c); })
 208 #define writesb(p,d,l)          ({ __iowmb(); __raw_writesb(p,d,l); })
 209 #define writesw(p,d,l)          ({ __iowmb(); __raw_writesw(p,d,l); })
 210 #define writesl(p,d,l)          ({ __iowmb(); __raw_writesl(p,d,l); })
 211
 212 /*
 213  * Relaxed API for drivers which can handle barrier ordering themselves
 214  *
 215  * Also these are defined to perform little endian accesses.
 216  * To provide the typical device register semantics of fixed endian,
 217  * swap the byte order for Big Endian
 218  *
 219  * http://lkml.kernel.org/r/201603100845.30602.arnd@arndb.de
 220  */
 221 #define readb_relaxed(c)        __raw_readb(c)
 222 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
 223                                         __raw_readw(c)); __r; })
 224 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
 225                                         __raw_readl(c)); __r; })
 226
 227 #define writeb_relaxed(v,c)     __raw_writeb(v,c)
 228 #define writew_relaxed(v,c)     __raw_writew((__force u16) cpu_to_le16(v),c)
 229 #define writel_relaxed(v,c)     __raw_writel((__force u32) cpu_to_le32(v),c)
 230
 231 #include <asm-generic/io.h>
 232
 233 #endif /* _ASM_ARC_IO_H */