Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt

   1 QCOM GSBI (General Serial Bus Interface) Driver
   2
   3 The GSBI controller is modeled as a node with zero or more child nodes, each
   4 representing a serial sub-node device that is mux'd as part of the GSBI
   5 configuration settings.  The mode setting will govern the input/output mode of
   6 the 4 GSBI IOs.
   7
   8 Required properties:
   9 - compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
  10 - reg: Address range for GSBI registers
  11 - clocks: required clock
  12 - clock-names: must contain "iface" entry
  13 - qcom,mode : indicates MUX value for configuration of the serial interface.
  14   Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
  15
  16 Optional properties:
  17 - qcom,crci : indicates CRCI MUX value for QUP CRCI ports.  Please reference
  18   dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
  19
  20 Required properties if child node exists:
  21 - #address-cells: Must be 1
  22 - #size-cells: Must be 1
  23 - ranges: Must be present
  24
  25 Properties for children:
  26
  27 A GSBI controller node can contain 0 or more child nodes representing serial
  28 devices.  These serial devices can be a QCOM UART, I2C controller, spi
  29 controller, or some combination of aforementioned devices.
  30
  31 See the following for child node definitions:
  32 Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
  33 Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
  34 Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
  35
  36 Example for APQ8064:
  37
  38 #include <dt-bindings/soc/qcom,gsbi.h>
  39
  40         gsbi4@16300000 {
  41                 compatible = "qcom,gsbi-v1.0.0";
  42                 reg = <0x16300000 0x100>;
  43                 clocks = <&gcc GSBI4_H_CLK>;
  44                 clock-names = "iface";
  45                 #address-cells = <1>;
  46                 #size-cells = <1>;
  47                 ranges;
  48                 qcom,mode = <GSBI_PROT_I2C_UART>;
  49                 qcom,crci = <GSBI_CRCI_QUP>;
  50
  51                 /* child nodes go under here */
  52
  53                 i2c_qup4: i2c@16380000 {
  54                         compatible = "qcom,i2c-qup-v1.1.1";
  55                         reg = <0x16380000 0x1000>;
  56                         interrupts = <0 153 0>;
  57
  58                         clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
  59                         clock-names = "core", "iface";
  60
  61                         clock-frequency = <200000>;
  62
  63                         #address-cells = <1>;
  64                         #size-cells = <0>;
  65
  66                  };
  67
  68                 uart4:  serial@16340000 {
  69                         compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  70                         reg = <0x16340000 0x1000>,
  71                                 <0x16300000 0x1000>;
  72                         interrupts = <0 152 0x0>;
  73                         clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
  74                         clock-names = "core", "iface";
  75                         status = "ok";
  76                 };
  77         };
  78